JP2003309258A - Mos semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that realization of an MOS transistor excellent in high breakdown voltage characteristic is difficult on account of a shape of an N+ type diffusion region turning into a drain lead-out region, in a conventional MOS transistor. <P>SOLUTION: In this MOS transistor 21, a bird's beak shape part 281 of an LOCOS oxide film 28 on a drain electrode 37 side is formed large having a gentle gradient. By using the bird's beak shape part 281, the N+ type diffusion region 31 turning to the drain lead-out region is formed wide in a current passing direction having a concentration gradient. As a result, an electric field can be relived on a drain electrode 37 side to which a high voltage is applied, parasitic resistance in the drain region can be reduced, and the on-resistance of the MOS transistor 21 can be reduced. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention In the present invention, in a MOS transistor, an LO having bird's beaks with different slopes is provided.
By forming a COS oxide film and forming a lateral concentration gradient of the drain extraction region through the bird's beak,
The purpose is to realize electric field relaxation on the drain electrode side.

[0002]

2. Description of the Related Art Recently, in portable devices such as MD and CD, I
High integration, performance improvement, low power consumption, etc. due to the miniaturization of C are required. The power MOS transistor shown below as a conventional example is generally used in a portable device such as M
It is used as a battery drive motor driver IC for D and CD. And, it is researched and developed every day aiming at the above-mentioned development theme.

FIG. 10 shows a conventional N-channel MO.
3 is a cross-sectional view of the S transistor 1. FIG.

As shown in the figure, an N-type epitaxial layer having a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of 1.0 to 6.0 μm is formed on the P-type single crystal silicon substrate 2. 3 is formed. Then, the substrate 2 and the epitaxial layer 3 are N-doped by the P + type isolation region 4 penetrating them.
An island region 5 forming the channel type MOS transistor 1 is formed. Then, the substrate 2 and the epitaxial layer 3
An N + type buried layer 6 is formed between the and.

In the epitaxial layer 3 of the island region 5, a P-type diffusion region 7 as a channel forming region and an N + type diffusion region 8 serving as a drain region are formed. An N ++ type diffusion region 10 serving as a source region is formed in the P− type diffusion region 7. On the other hand, an N ++ type diffusion region 9 is formed in the N + type diffusion region 8.

Then, the gate electrode 11, the insulating layer 12 and the like are formed on the surface of the epitaxial layer 3. Through the contact hole formed in the insulating layer 12, the drain electrode 1
3 and the source electrode 14 are formed, and the N shown in FIG.
The channel type MOS transistor 1 is completed.

[0007]

As shown in the figure, the conventional M
In the OS transistor 1, the LOCOS oxide film 15 was formed between the source electrode 14 and the drain electrode 13. On the source electrode 14 side, this LOCOS oxide film 15
A part of the gate electrode 11 is formed so as to overlap therewith to relax the electric field to the gate oxide film. on the other hand,
On the drain electrode 13 side, the N + type diffusion region 8 to be the drain extraction region was formed up to the region below the bird's beak portion 151 of the LOCOS oxide film 15.
Then, in the conventional MOS transistor 1, a certain voltage is applied to the gate electrode 11 while a voltage higher than that applied to the source electrode 14 is applied to the drain electrode 13. Then, an N-type channel layer was formed and driven on the surface layer of the P-type diffusion region 7 located under the gate electrode 11. Then, by applying a high voltage to the drain electrode 13, the electric field was concentrated in this region.

However, N + on the drain electrode 13 side
In the diffusion region 8 of the mold, in the region below the bird's beak portion 151 of the LOCOS oxide film 15, the impurity concentration gradient becomes steep between the surface side and the deep portion. Therefore, the depletion layer extending from the boundary between the P− type diffusion region 7 and the epitaxial layer 3 extends to the vicinity of the N ++ type diffusion region 11. As a result, in the lower region of the bird's beak shaped portion 151, there is a problem that the above-mentioned electric field is concentrated at the boundary between the depletion layer and the N ++ type diffusion region 11.

Further, in the conventional MOS transistor 1, the epitaxial layer 3 in the lower region of the LOCOS oxide film 15 becomes the drain region, but the parasitic resistance R1 in this portion is high, and the parasitic resistance when the MOS transistor 1 is ON is high. There was a problem of increase.

[0010]

The present invention has been made in view of the above-mentioned conventional problems. In the MOS semiconductor device of the present invention, a semiconductor substrate of one conductivity type is laminated on at least the surface of the substrate. A reverse conductivity type epitaxial layer in which a part of the region serves as a drain region, a reverse conductivity type buried layer formed between the substrate and the epitaxial layer, and a drain extraction region in the epitaxial layer. A reverse conductivity type diffusion region of 1, and a conductivity type diffusion region serving as a channel formation region in the epitaxial layer,
A second diffusion region of opposite conductivity type that constitutes a source region and forms a double diffusion structure with the diffusion region of one conductivity type; and a gate electrode made of polycrystalline silicon on the surface of the epitaxial layer. L on the desired area of the surface
An OCOS oxide film is formed, the LOCOS oxide film has at least two bird's beak shaped portions having different gradients, and the first opposite conductivity type diffusion region is the LOCOS oxide film.
The lower region of the bird's beak shaped portion of the S oxide film is characterized by having a concentration gradient and a diffusion depth gradient.

In order to solve the above-mentioned problems, in the method of manufacturing a MOS semiconductor device of the present invention, a semiconductor substrate of one conductivity type is prepared, and impurities of opposite conductivity type are introduced into the surface of the substrate, and then, Deposit an epitaxial layer on the substrate,
Forming a buried layer so as to sandwich a boundary surface between the substrate and the epitaxial layer; and forming a LOCOS oxide film having at least two bird's beak shaped portions having different gradients in a desired region of the epitaxial layer,
A step of ion-implanting an impurity of opposite conductivity type from above the bird's beak shaped portion of the COS oxide film to form a first diffusion region of opposite conductivity type which becomes a drain extraction region, and after forming a gate oxide film on the surface of the epitaxial layer. Forming a gate electrode made of polycrystalline silicon on the gate oxide film, and forming a diffusion region of one conductivity type to be a channel formation region in the epitaxial layer, and then forming a second conductivity type to be a source region. And a step of forming a diffusion region of.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an example of a cross-sectional view of an N-channel type MOS transistor 21 in the present embodiment.

As shown in the figure, on the P-type single crystal silicon substrate 22, for example, a specific resistance of 0.1 to 3.5 Ω · cm,
N-type epitaxial layer 2 having a thickness of 1.0 to 6.0 μm
3 is formed. The substrate 22 and the epitaxial layer 23 have a P + type isolation region 2 penetrating them.
4 form an island region 25. Although only the island region 25 is shown in the present embodiment, a plurality of other island regions are formed.
S-transistor, P-channel type MOS transistor,
NPN type transistors and the like are formed.

The isolation region 24 is composed of a first isolation region 26 diffused from the surface of the substrate 22 in the vertical direction and a second isolation region 27 diffused from the surface of the epitaxial layer 23. Then, the two are connected to separate the epitaxial layer 23 into islands. Further, since the LOCOS oxide film 28 is formed on the P + type isolation region 24, more element isolation is achieved. The structure of the N-channel MOS transistor 21 according to the present invention will be described below.

As shown, an N-type epitaxial layer 23 is formed on the substrate 22. An N + type buried layer 29 is formed between the substrate 22 and the epitaxial layer 23 so as to sandwich the boundary surface therebetween. And
In the epitaxial layer 23, a P forming a channel forming region is formed.
A − type diffusion region 30 and an N + type diffusion region 31 to be a drain extraction region are formed. In the P− type diffusion region 30, the N ++ type diffusion region 3 serving as the source region is formed.
3 has a double diffusion structure. On the other hand, an N ++ type diffusion region 32 is formed in the N + type diffusion region 31 which becomes the drain extraction region.

On the epitaxial layer 23, a LOCOS oxide film 28 is formed between the source electrode 38 and the drain electrode 37, while a silicon oxide film 34 is formed in the other regions. This silicon oxide film 34
Plays a role as a gate oxide film in the lower region of the gate electrode 35. A gate electrode 35 made of, for example, polycrystalline silicon (polysilicon) is formed on a part of the gate oxide film and the LOCOS oxide film 28.

Then, a silicon oxide film is formed so as to cover the gate electrode 35, and an insulating layer 36 is formed on the surface of the epitaxial layer 23. A contact hole for an external electrode is formed in the insulating layer 36, and a drain electrode 37 and a source electrode 38 are formed through this contact hole.
Are formed of, for example, aluminum (Al). With this structure, the MOS transistor 2 as shown
1 is completed.

Then, the MOS transistor 21 of the present invention
Is characterized in that the epitaxial layer 23 between the drain electrode 37 and the source electrode 38 has at least two different gradient-shaped bird's beak shaped portions 281, 282.
Forming a LOCOS oxide film 28. The N + type diffusion region 31 that becomes the drain extraction region is formed by utilizing this bird's beak shaped portion 281.

Specifically, as shown in the drawing, the bird's beak-shaped portion 281 located on the drain electrode 37 side of the LOCOS oxide film 28 has a gentle gradient and is formed large. On the other hand, the bird's beak portion 281 located on the source electrode 38 side of the LOCOS oxide film 28 has a steep gradient and is formed small. That is, FIG.
In the cross-sectional view shown in FIG. 3, the LOCOS oxide film 28 has bird's beak shaped portions 281 and 282 having different gradients on the drain electrode 37 side and the source electrode 38 side. Then, as will be described later in detail in the manufacturing method, the N + type diffusion region 31 serving as a drain extraction region is formed by N type impurity ions passing through the bird's beak shaped portion 281. As a result, the impurity concentration distribution of the N + type diffusion region 31 in the lower region of the bird's beak shaped portion 281 is formed with a gentle concentration gradient similar to the gradient of the bird's beak shaped portion 281. Furthermore, the N + type diffusion region 31
Is also formed on the surface of the epitaxial layer 23 located at the bottom of the LOCOS oxide film 28, though it has a low concentration.

That is, the MOS transistor 21 of the present invention
In the above, the N + type diffusion region 31 serving as the drain extraction region is formed with an impurity concentration gradient in the current passing direction particularly in its surface region. LOCOS
In the region between the oxide film 28 and in contact with the drain electrode 37, the N ++ type diffusion region 32 is formed to form a high concentration N type region. On the other hand, on the surface of the epitaxial layer 23 at the bottom of the LOCOS oxide film 28, conversely,
Almost no impurities are ion-implanted to form a low concentration N-type region. And, as a feature of the present invention,
Epitaxial layer 23 at the bottom of bird's beak shaped portion 281
On the surface, the difference in the thickness of the oxide film of the bird's beak portion 281 is utilized to change the amount of impurity ion implantation. As a result, the impurity concentration in the lower region of the bird's beak shaped portion 281 is formed by a substantially uniform concentration gradient similar to the gradient of the bird's beak shaped portion 281.

Further, as shown in the figure, an N + type diffusion region 31 is provided.
In the region where the LOCOS oxide film 28 is formed and the region where the LOCOS oxide film 28 is not formed, the ion implantation depth of impurities is different. As a result, the N + type diffusion region 31 is not formed with a uniform diffusion depth, and the bird's beak shaped portion 28 of the LOCOS oxide film 28 is formed.
It is formed to have a gradient of 1.

As described above, the MOS transistor 21 of the present invention is characterized by the structure of the N + type diffusion region 31 which becomes the drain extraction region on the side of the drain electrode 37 to which a high voltage is applied. That is, the N + type diffusion region 31 has the LOC
The region below the bird's beak portion 281 of the OS oxide film 28 has a gentle concentration gradient and is formed to the bottom of the LOCOS oxide film 28. As a result, the effects described below can be obtained.

First, the first effect is that the MO of the present invention is used.
In the S-transistor 21, an electric field is concentrated in this region by applying a high voltage to the drain electrode 37.
Can be relaxed evenly in the lower region of the. This is because the N + type diffusion region 31 has the LOCOS oxide film 2 as described above.
8 has a gentle concentration gradient in the lower region of the bird's beak portion 281. As a result, unlike the structure of the conventional MOS transistor 1 (see FIG. 10), a low concentration region is not formed in the region near the N ++ type diffusion region 32.
That is, in the MOS transistor 21 of the present invention, the LOC
In the region below the bird's beak shaped portion 281 of the OS oxide film 28, it is possible to suppress the depletion layer from spreading to the vicinity of the N ++ type diffusion region 32. As a result, the region having the concentration gradient in the region below the bird's beak portion 281 of the LOCOS oxide film 28 can evenly disperse the electric field due to the high voltage applied to the drain electrode.
Then, electric field concentration near the N ++ type diffusion region in contact with the drain electrode in the conventional MOS transistor structure can be relaxed.

In the MOS transistor 21 of the present invention, the bird's beak-shaped portion 281 of the LOCOS oxide film 28 is formed.
Although the depletion layer forming region is somewhat reduced in the lower region, there is no particular influence on the breakdown voltage characteristics. Rather, as described above, the MOS transistor 21 is characterized in that it can maintain the withstand voltage characteristic and can alleviate the electric field.

The second effect is that the MO of the present invention is used.
In the S transistor 21, the P− type diffusion region 30 and the N +
The epitaxial layer 23 between it and the diffusion region 31 of the mold is used as a drain region. By forming the N + type diffusion region 31 having a low concentration in this region, the parasitic resistance in the drain region can be reduced. As described above, the N + type diffusion region 31 is
On the surface of the epitaxial layer 23 at the bottom of the LOCOS oxide film 28, impurities are hardly ion-implanted to form a low concentration N-type region. As a result, the impurity concentration of the epitaxial layer 23 serving as the drain region can be increased, and the parasitic resistance in this region can be reduced. As a result, the parasitic resistance of the MOS transistor 21 itself can be reduced, and the ON resistance during switching of the MOS transistor 21 can be reduced.

Another feature of the MOS transistor 21 is that the gate electrode 35 is formed so as to overlap a part of the LOCOS oxide film 28. With that,
On the side of the drain electrode 37 where electric field relaxation is required by applying a high voltage, a thick silicon oxide film is formed by the LOCOS oxide film 28. As a result, electric field relaxation can be achieved in this region. On the other hand, the source electrode 3
On the 8 side, a thin silicon oxide film 34 is formed so that the voltage applied to the gate electrode 35 is transmitted. As a result, the P− type diffusion region 3 located under the gate electrode 35 is formed.
The structure is such that it is easy to form an N-type channel region at 0.

The present invention is not limited to this embodiment, and various modifications can be made without departing from the gist of the present invention.

Next, a method of manufacturing the N-channel type MOS transistor 21 according to the embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS.
In the following description, the same components as the components described in the structure of the MOS transistor shown in FIG. 1 are designated by the same reference numerals.

First, as shown in FIG. 2, a P-type single crystal silicon substrate 22 is prepared, and the surface of the substrate 22 is thermally oxidized to form a silicon oxide film on the entire surface, for example, 0.03 to 0.
It is formed to about 05 μm. After that, by a known photolithography technique, a photoresist having an opening in a portion where the N + type buried layer 29 is to be formed is formed as a selective mask. Then, N-type impurities such as phosphorus (P)
Acceleration voltage of 20 to 65 keV, introduction amount of 1.0 × 10 ¹³ to
Ion implantation is performed at 1.0 × 10 ¹⁵ / cm ² and diffusion is performed. Then, the photoresist is removed.

Next, as shown in FIG. 3, using the silicon oxide film formed in FIG. 2, an opening is provided in a portion of the isolation region 24 where the first isolation region 26 is formed by a known photolithography technique. The photoresist is formed as a selective mask. Then, a P-type impurity such as boron (B) is introduced at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.
Ion implantation at 0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² ,
Spread. Then, the photoresist is removed.

Next, as shown in FIG. 4, the silicon oxide film formed in FIG. 2 is completely removed, and the substrate 22 is placed on the susceptor of the epitaxial growth apparatus. Then, the substrate 22 is heated to a high temperature of, for example, about 1000 ° C. by lamp heating, and SiH ₂ Cl ₂ gas and H ₂ are introduced into the reaction tube.
Introduce gas. Thereby, on the substrate 22, for example, a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of 1.0 to 6.
The epitaxial layer 23 of about 0 is grown. afterwards,
The surface of the epitaxial layer 23 is thermally oxidized to form a silicon oxide film, for example, about 0.03 to 0.05 μm.
After that, a photoresist having an opening formed in a portion of the isolation region 24 where the second isolation region 27 is to be formed is formed as a selection mask by a known photolithography technique.
Then, a P-type impurity, for example, boron (B) is accelerated at a voltage of 60 to 100 keV, and the introduction amount is 1.0 × 10 ^{13 to} 1.0 ×.
Ion implantation is performed at 10 ¹⁵ / cm ² and diffusion is performed. Then, the photoresist is removed.

Next, as shown in FIGS. 5A and 5B, the LOCOS oxide film 2 is formed on a desired region of the epitaxial layer 23.
8 is formed. First, as shown in FIG. 5A, the first silicon oxide film 39 is formed only on the portion of the surface of the epitaxial layer 23 where the gradual sloped bird's beak portion 281 of the LOCOS oxide film 28 is formed. After that, a second film is formed on the surface of the epitaxial layer 23 including the first silicon oxide film 39.
Forming a silicon oxide film 40. By this step, a silicon oxide film having two kinds of thickness, that is, a thick silicon oxide film portion and a thin silicon oxide film portion is formed on the surface of the epitaxial layer 23. Then, as shown in the figure, a silicon nitride film 41 is formed on the second silicon oxide film 40.
For example, after forming about 0.05 to 0.2 μm,
The silicon nitride film 41 is selectively removed so that an opening is provided in a portion where the OCOS oxide film 28 is formed.

Then, as shown in FIG. 5B, by using this silicon nitride film 41 as a mask, from above the first and second silicon oxide films 39 and 40, for example, 800-1
An oxide film is attached by steam oxidation at about 200 ° C. At the same time, heat treatment is applied to the entire substrate 22 to form the LOCOS oxide film 28. At this time, in particular, the biting of the oxide film occurs in the portions where the first and second silicon oxide films 39 and 40 are formed to be thick and overlap with each other. As a result, the LOCOS oxide film 2 in the portion where the silicon oxide film is thickly formed.
A large bird's beak 281 having a gentle slope is formed at 8. That is, the LO of the present embodiment in the illustrated cross section
In the COS oxide film 28, the left and right asymmetrical LOCOS
It becomes the oxide film 28. Further, in particular, by forming the LOCOS oxide film 28 on the P + type isolation region 24, more element isolation is achieved.

Here, the LOCOS oxide film 28 is formed to have a thickness of, for example, about 0.5 to 1.0 μm in the flat portion. In this step, the P + type second isolation region 27 is diffused at the same time, the first and second isolation regions are connected, and P
A + type isolation region 24 is formed.

Next, as shown in FIG. 6, a silicon oxide film 34 is formed on the surface of the epitaxial layer 23, for example, 0.01-.
The thickness is about 0.20 μm. Then, this silicon oxide film 34 is used as a gate oxide film below the gate electrode 35. Then, by a known photolithography technique, N
A photoresist having an opening in a portion where the + type diffusion region 31 is formed is formed as a selection mask. Then, an N-type impurity such as phosphorus (P) is added at a high acceleration voltage 10
0 to 200 keV, introduction amount 1.0 × 10 ^{13 to} 1.0 × 1
Ions are implanted at 0 ¹⁵ / cm ² and diffused. Then, the photoresist is removed. By this step, the N + type impurities are also implanted into the bird's beak portion 281 of the LOCOS oxide film 28, and at this time, the implantation amount of the impurity changes depending on the thickness of the oxide film of the bird's beak portion 281. That is, the present embodiment is characterized in that ion implantation is performed at a high acceleration voltage so that the impurity ions pass through the bird's beak portion 281. Then, a large amount of impurities are implanted in the bird's beak portion 281 where the oxide film is thin, and on the other hand, the amount of impurities implanted is small where the oxide film is thick. With this,
The N + type impurity concentration in the lower region of the bird's beak portion 281 of the LOCOS oxide film 28 is formed so that the impurity concentration gradient becomes gentler as compared with the conventional structure. As a result, a structure that can achieve the effects described above in the description of the MOS transistor 21 structure of the present invention is realized.

Next, as shown in FIG. 7, a polysilicon film is deposited on the silicon oxide film 34 formed in FIG. 6 to have a thickness of, for example, about 0.2 to 0.3 μm. Then, an N-type impurity such as phosphorus (P) is introduced into the polysilicon film at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ¹³ to.
Ion implantation is performed at 1.0 × 10 ¹⁵ / cm ² . Then, the polysilicon film other than the region where the gate electrode 35 is formed is removed by a known photolithography technique.

Thereafter, as shown in FIG.
Known photolithography using the silicon oxide film 34
In the portion where the P-type diffusion region 30 is formed by the technique
Using the photoresist with the opening as a selection mask
Form. And a P-type impurity such as boron (B)
Acceleration voltage 60 to 100 keV, introduction amount 1.0 × 10 ¹³
~ 1.0 x 10¹⁵/ Cm²Ion implantation is carried out and diffused.
Then, the photoresist is removed. At this time, the gate
By using the electrode 35 as a mask, it is more accurate.
On-injection can be performed. Also, in this process
Thus, the N + type diffusion region 31 is simultaneously diffused.

Next, as shown in FIG. 8, using the silicon oxide film 34 formed in FIG. 6, an opening is formed in the portion where the N ++ type diffusion regions 32 and 33 are formed by a known photolithography technique. A photoresist is formed as a selective mask. Then, an N-type impurity, for example, phosphorus (P) is added at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 ×.
Ion implantation is performed at 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² and diffusion is performed. Then, the photoresist is removed. By this step, the P− type diffusion region 30 is simultaneously diffused.

Next, as shown in FIG. 9, BPSG is formed as an insulating layer 36 on the epitaxial layer 23 or the like, for example, on the entire surface.
(Boron Phospho Silicate G
(lass) film, SOG (Spin On Glass)
Deposit a film, etc. After that, a contact hole for forming an external electrode is formed by a known photolithography technique.

Finally, through the contact hole formed in the insulating layer 36, the drain electrode 3 made of, for example, Al
7 and the source electrode 38 are formed, and the N-channel type MOS transistor 21 shown in FIG. 1 is completed.

In the above-described embodiment, the case where only the N-channel type MOS transistor is formed has been described, but the N-channel type MOS transistor is similarly formed in the other island regions.
A transistor, an NPN transistor, etc. can be formed at the same time. Besides, various modifications can be made without departing from the scope of the present invention.

[0043]

According to the present invention, firstly, in the MOS semiconductor device, the N + type diffusion region serving as the drain extraction region has a gentle concentration gradient in the region below the bird's beak-shaped portion of the LOCOS oxide film. This makes it possible to prevent the depletion layer from spreading directly to the drain electrode and spreading to the vicinity of the N ++ type diffusion region formed in this diffusion region. As a result, in the region near the drain electrode of the MOS semiconductor device to which a high voltage is applied, it is possible to suppress the expansion of the depletion layer due to the concentration gradient in this region. In the MOS semiconductor device of the present invention, the electric field can be evenly dispersed by the gentle concentration gradient in the lower region of the bird's beak portion while maintaining the withstand voltage characteristic.

Secondly, in the MOS semiconductor device of the present invention,
It is characterized in that an N + type diffusion region having a low concentration is formed in the low concentration epitaxial layer used as the drain region. As a result, the impurity concentration of the epitaxial layer serving as the drain region can be increased, and the parasitic resistance in this region can be reduced. As a result, MO
The parasitic resistance of the S transistor itself can also be reduced,
The ON resistance during switching of the MOS semiconductor device can be reduced.

Thirdly, in the method for manufacturing a MOS semiconductor device of the present invention, the LOCOS oxide film having at least two bird's beak portions having different gradients is formed by using the deposition process of the silicon oxide film at least twice. It is characterized by As a result, the N formed in this lower region
It can be formed in the + type diffusion region with a gentle concentration gradient.

Fourth, the method of manufacturing a MOS semiconductor device of the present invention is characterized in that impurity ions are implanted through the bird's beak portion of the LOCOS oxide film on the drain electrode side. Therefore, in particular, in the lower region of the bird's beak portion, it is possible to form an N + type diffusion region having a gentle concentration gradient in the impurity concentration by utilizing the difference in the thickness of the oxide film. As a result, in the MOS semiconductor device, it is possible to obtain various effects such as relaxation of the electric field and reduction of ON resistance while maintaining the withstand voltage characteristic.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a MOS semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 7 is a cross sectional view illustrating a method for manufacturing a MOS semiconductor device of the present invention.

FIG. 8 is a sectional view illustrating a method for manufacturing a MOS semiconductor device according to the present invention.

FIG. 9 is a cross sectional view illustrating a method for manufacturing a MOS semiconductor device of the present invention.

FIG. 10 is a cross-sectional view illustrating a conventional MOS semiconductor device.

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F140 AA25 AA30 AA39 AB03 AC21                       BA01 BA16 BC12 BD19 BF01                       BF04 BF44 BG27 BG32 BG37                       BH13 BH19 BH30 BH47 BJ01                       BJ05 BK13 BK25 CB01 CB02                       CC02 CC07 CD02 CF00

Claims (9)

[Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of the opposite conductivity type, which is laminated on at least the surface of the substrate and has a partial region serving as a drain region, and is formed between the substrate and the epitaxial layer. A reverse conductivity type buried layer, a first reverse conductivity type diffusion region serving as a drain extraction region in the epitaxial layer, a one conductivity type diffusion region serving as a channel forming region in the epitaxial layer, and the one conductivity type. A second diffusion region of opposite conductivity type, which forms a double diffusion structure and a source diffusion region, and a gate electrode made of polycrystalline silicon on the surface of the epitaxial layer. LOCOS
An oxide film is formed, and the LOCOS oxide film has at least two bird's beak shaped portions having different gradients.
The first reverse conductivity type diffusion region is formed with a concentration gradient in the lower region of the bird's beak portion of the LOCOS oxide film and with a diffusion depth gradient. apparatus. 2. The MOS semiconductor device according to claim 1, wherein a concentration gradient of the diffusion region of the first opposite conductivity type is provided in a current passing direction. 3. A third reverse conductivity type diffusion region having a higher concentration than that of the first reverse conductivity type diffusion region is formed on the surface of the first reverse conductivity type diffusion region, and the third reverse conductivity type diffusion region is formed. 3. The MOS semiconductor device according to claim 2, wherein the diffusion region of the opposite conductivity type is in contact with the drain electrode. 4. A semiconductor substrate of one conductivity type is prepared, impurities of opposite conductivity type are introduced into the surface of the substrate, an epitaxial layer is deposited on the substrate, and a boundary surface between the substrate and the epitaxial layer is formed. Forming a buried layer so as to sandwich it, and forming a LOCOS oxide film having at least two bird's beak shaped portions having different gradients in a desired region of the epitaxial layer, and forming a LOCOS oxide film from the bird's beak shaped portion of the opposite conductivity type on the bird's beak shaped portion. Forming a diffusion region of a first opposite conductivity type which becomes a drain extraction region by ion-implanting the impurity of the above step, and forming a gate oxide film on the surface of the epitaxial layer, and then forming polycrystalline silicon on the gate oxide film. Forming a gate electrode, and forming a diffusion region of one conductivity type to be a channel forming region in the epitaxial layer, and then forming a source region. And a step of forming a second opposite conductivity type diffusion region serving as a region. 5. The ion implantation step of forming the first diffusion region of the opposite conductivity type utilizes a bird's beak shaped portion of the LOCOS oxide film, and high-acceleration ion implantation in which impurity ions pass through at least the bird's beak shaped portion. 5. The method for manufacturing a MOS semiconductor device according to claim 4, which is a step. 6. The step of forming a bird's beak-shaped portion of the LOCOS oxide film comprises forming the silicon oxide film having at least two types of thickness by performing the silicon oxide film forming step at least twice. Item 4
Alternatively, the method for manufacturing the MOS semiconductor device according to claim 5. 7. The method of manufacturing a MOS semiconductor device according to claim 4, wherein at least a part of the gate electrode is formed so as to be located on the LOCOS oxide film. 8. The one-conductivity-type diffusion region and the second diffusion region.
5. The method for manufacturing a MOS semiconductor device according to claim 4, wherein the step of forming the diffusion region of the opposite conductivity type is performed by double diffusion using the gate electrode as a mask. 9. The third reverse conductivity type diffusion region having a higher concentration than that of the first reverse conductivity type diffusion region is formed on the surface of the first reverse conductivity type diffusion region. 9. The method for manufacturing a MOS semiconductor device according to claim 8, wherein the diffusion region of the opposite conductivity type is formed in the same step as the diffusion region of the second opposite conductivity type.