JPS6343343A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the isolation width of an element isolation region in a bipolar transistor by forming a P-type diffusion layer under a P<+> buried layer and inhibiting a punch-through phenomenon. CONSTITUTION:An N<+> region 2 on a P-type semiconductor substrate 1 is isolated by a P<+> buried layer 3. The layer 3 having high impurity concentration reaches down to a low concentration section in the substrate 1 and forms a P-type buried diffusion layer 30, and the depth Wy of the layer 30 is set to a required value or more, thus inhibiting a punch-through phenomenon, then increasing isolation breakdown strength. Accordingly, isolation width W2 can be reduced, thus augmenting the density of a bipolar transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a structure of a semiconductor device suitable for high integration in a region before an element of a bipolar transistor.

[Conventional technology]

In recent years, a so-called B i -CMO3 type semiconductor device has been proposed in which a bipolar transistor and an 0MO5 (complementary MO8) transistor are integrally formed on a single semiconductor substrate (Japanese Patent Laid-Open No. 59-948613).

FIG. 2 is an example of this, and the figure shows a plan view (A) and a cross-sectional view (A) of a bipolar transistor to which the present invention is applied.
B) in the same figure is shown. N+ on one P-type semiconductor substrate 1
(N-type high concentration) type implantation)? j2 and p+ (p-type high concentration) type buried layer 3 are formed, and an epitaxial layer 4 is grown on these, and then an N-type well 5.j2 is formed. A P-type well 6 is formed, in which a bipolar transistor QB, an N-type MO8 type transistor (not shown), and a P-type MOS transistor (not shown) are formed. Bipolar transistor Qa has an N-type collector layer 7. P-type base layer 8
．． It is composed of an N-type emitter layer 9.

NPN) - transistor. This bipolar transistor Qa is formed in an N-type well region 5 on an N-small buried layer 2 surrounded by a P-type buried layer 3.

Although not shown in FIG. 2, the P-type MOS transistor is an N-shaped buried layer 3 adjacent to the P-shaped buried layer 3. In the N type well region 5 on J2, the N type MOS transistor has a P÷ type source and an N type source layer on the P type well region 6 on the P type buried layer 3 adjacent to the N type buried layer 2, respectively. , drain and gate are formed.

The device isolation of the bipolar transistor Qa r P-type MOS transistor is achieved by using a thick oxide film (
Si02 film) and N0 buried layer2. P ten buried layer 3. N
Type well area5. They are separated by a PN junction in a P-type well region 6. So-called LOGO5 (Local 0x
idization of 5 silicon) and PN contact separation method. A channel stopper layer 11 is formed under the filled oxide film 10 in the P-type well region 6. 12 is polysilicon for drawing out the emitter electrode 13. 15 is an interlayer insulating film, 16 is an N-type emitter layer 9. P type base N! I8. These are the N-type erector layer 7, the P-type MoS transistor, the P-shaped skewer type of the N-type transistor, and the aluminum wiring for the N medium-sized source and drain contacts.

Above-mentioned Sita, N+embedded M2. p+embedded m3 is Bi-C
This is an essential configuration for MO5 type semiconductor devices.

That is, in the NPN transistor QB, since the N0 buried layer 2 exists under the N type well region, the collector resistance becomes small, which is advantageous for increasing the speed. Also, when viewed from the MOS transistor side, since the N0 buried layer 2 exists under the N well region 5 of the P-type transistor, bunching of the parasitic PNP)-transistor can be prevented. Since the buried layer 3 exists, the well resistance can be reduced to 0M.
The latch-up resistance characteristic of O5I transistors can be improved.

As described above, N0 buried layer 2. The design of P0 buried layer 3 is B
This greatly affects the performance of i-CMO5 type semiconductor devices.

Focusing on the performance of bipolar transistors, their higher speed and higher integration are due to the planar dimensions of the elements and the construction of the fir tree.

It largely depends on the element isolation method. The present invention provides a highly integrated semiconductor device by improving element isolation, and the element isolation width in FIG. 2 is determined by the distance between the N+ buried layers (indicated by Wt in the figure). . The N0 buried layer 2 is the collector layer of the bipolar transistor, and the P0 buried layer 3 is the collector layer of the bipolar transistor.
electrically isolated by Furthermore, it is determined by the distance (indicated by W2 in the figure) between the P base layer 8 and the P buried layer 3 of the bipolar transistor. (Or, although not shown in the figure, the distance between the P0 source or drain of the PMOS transistor and the P0 buried layer) The former depends on the impurity concentration of the P0 buried layer 3, and the latter depends on the impurity concentration of the N type well 5. do. Both as mentioned above.

Since it is related to the performance of the MO8 type transistor, it cannot be controlled independently.

The present invention aims at improving element isolation, and in particular, by minimizing the separation width between the N0 buried layers 2, that is, the width W1 of the N0 buried layer opening shown in FIG. 1, to achieve high integration. It is about providing. In the conventional structure shown in FIG. 1, the peak impurity concentration of N0 buried M2 is about 10" atm/al?, P÷ buried!I3
The peak impurity concentration of the P-type semiconductor substrate 1 is about 10" atoms/i, and the impurity concentration of the P-type semiconductor substrate 1 is 1015 atoms/i.
/ci. The isolation voltage is about 3 times the power supply voltage.
It is designed to be set to about twice the rated voltage, and the width W1 between the two N buried layers is limited by the punch-through pressure given the impurity concentration and breakdown voltage. FIG. 3 shows the relationship between the isolation width W1 (collector calendar - collector opening) between the N0 buried layers 2 of a bipolar transistor and the element isolation breakdown voltage.

In a region where Wl is long, the breakdown voltage is determined by the amount of ion implantation in the P buried layer, but in a region where Ws is short, the breakdown voltage is determined by the amount of ion implantation in the P buried layer.
The pressure resistance has deteriorated. Here, the withstand voltage in the long region of Wl is due to the avalanche withstand voltage between the element isolation junctions, and the breakdown voltage in the long region of Wl
The breakdown voltage in the short region is determined by the punch-through breakdown voltage between N0 and N2. Therefore, as the amount of ions implanted into the buried layer 3 increases (P÷), the avalanche breakdown voltage decreases (as the impurity concentration increases), but the punch-through breakdown voltage improves because the extension of the depletion layer is suppressed, and the breakdown voltage reaches a point where Ws is short. should be able to be secured. In order to investigate the cause of this, the inventor conducted a simulation or experiment on the impurity concentration of the element isolation layer, and obtained the following results.
This is because the impurity concentration in the P-type semiconductor substrate 1 is low compared to the region P÷buried layer 3.

Determined by the punch-through breakdown voltage of the depletion layer in this ■ region,
Even if the ion implantation amount of the P-buried layer 3 is changed within the practical range, the P
The punch-through breakdown voltage is determined by the type semiconductor substrate l concentration.

From the above results, in order to reduce the element isolation width, it is necessary to increase the impurity concentration of the P-type semiconductor substrate 1 to prevent punch-through development. However, increasing the impurity concentration of the P-type semiconductor substrate 1 increases the parasitic capacitance between the collector substrates, which is disadvantageous for increasing speed.

[Problem that the invention seeks to solve]

-1 The above-mentioned conventional technology has a relatively P No consideration was given to the punch-through withstand voltage with the P-type semiconductor substrate, which is lower than the impurity concentration of the buried layer, making it difficult to reduce the width by one isolation, posing a problem in achieving high integration.

An object of the present invention is to provide punch-through development with a P-type semiconductor substrate for PN junction separation between a P-buried layer and an adjacent N-buried layer of a bipolar transistor in a B i -CMO5-type semiconductor device. An object of the present invention is to provide an element isolation structure for a bipolar transistor that can suppress N0 buried layer isolation, improve the isolation breakdown voltage, reduce the isolation width, and achieve high integration.

(Means for solving the rJ illumination point) The above purpose is to increase the device isolation voltage between the P10 buried layer and the adjacent N10 buried layer by placing a relatively large amount of P under the P+ buried layer.
This is achieved by forming a P-type buried diffusion layer that has an impurity concentration higher than that of the P-type semiconductor substrate and extends beyond the P-type semiconductor substrate.

[Effect]

Punch-through development can be suppressed by forming a P-type buried diffusion layer under the P-type buried layer. Therefore, the N0 buried layer isolation breakdown voltage is determined by P÷ the impurity concentration of the buried layer,
Without being limited to punch-through with the P-type semiconductor substrate, the isolation breakdown voltage can be improved to the point where Wl is short as shown in FIG. 2, and the isolation width can be reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1.2 and 4.5. Where the symbols are the same as those described in the prior art, they are used as they are.

FIG. 1 is a diagram explaining the present invention in detail.

The figure is a detailed cross-sectional view of the N0 buried layer 2 (collector layer-to-collector layer) in the element isolation structure of a bipolar transistor. P ten buried layer M3o adjacent to N ten buried layer 2
has reached the low concentration region of the silicon substrate 1. In this example, the impurity concentration of N÷buried layer 2 is 1019 atoms.
/al at a depth of 2.0 μm.

The impurity concentration of the P buried layer 30 is 1 to 2×10”at,o
ra/(j, depth is N0 from 0.8 to 1.0 from buried layer 2
It is about μm. FIG. 4 is a diagram illustrating the effects of the embodiment. Width W between N0 embeddings M2, which is a feature of the present invention
1 (see FIG. 1), P in the semiconductor substrate 1 and the depth Wy of the buried layer 30 (see FIG. 1). In the figure, a line is shown where an element isolation breakdown voltage of 15V can be obtained. According to the conventional method (when wy = 0), the width W1 between N0 embeddings M2
When trying to obtain a pressure of 15 cm, the P-type semiconductor substrate 1
Due to the punch-through phenomenon, the conventional method requires a thickness of 5 μm.

However, when the present invention is applied, by setting the depth Wa of the P0 buried layer 30 to 0.8 μm, the width Wl between the N0 buried layers 2 is set to 0.8 μm.
can be set to 3 μm, a separation breakdown voltage of 15 V can be obtained, and the effect of suppressing the punch-through phenomenon described above has been shown. The width W1 between N0 and N2 is 3 μm, and P+ is buried! 3
The reason why the separation breakdown voltage remains constant even when the depth Wy of 0 is set to 0.8 μm or more is considered to be because it is determined by the punch-through breakdown voltage in the P◆ buried layer 2.

As described above, according to this embodiment, the P0 buried diffusion layer 30, which is a diffusion layer having a relatively higher impurity concentration than the P type semiconductor substrate 1, is formed under the P0 buried layer M3 adjacent to the N0 buried layer 2. Therefore, the punch-through phenomenon with the P-type semiconductor substrate 1 can be suppressed, the isolation voltage can be improved, and the isolation width between the N+ buried layers 2 can be reduced. Specifically, the separation width between the N buried layers is 5 μm compared to the conventional one.
can be reduced from 3 μm to 3 μm, reducing the overall separation width (W 1
W 2 ) was reduced to 2 μm, 11, and high integration of bipolar transistors was achieved.

FIG. 5 shows a manufacturing process when the present invention is applied to a B i -0MO5 (bipolar/complementary MOS mixed) type semiconductor device.

First, as shown in the same figure (A), an oxide film (SiOx film) 100 and a nitride film (Si3N2 film) are formed on the surface of a P-type semiconductor substrate 1.
After forming 101, a mask for N-type buried layer (not shown) is applied.
Patterning is performed using photolithography technology. Then, 5iOzfl100 and 5iaO4 film 1
S for 30 minutes at 1100-1200℃ using 01 as a mask
Antimony (sb) was deposited at 1000℃ by bzOg deposition.
, by selectively diffusing for about 45 minutes, a N0 buried layer 2 can be formed, and a thick 5iOz film 102 (see figure (B)) can be formed on its surface.
) can be formed.

After removing the Si3N2 film 101, as shown in the same figure (B), boron was irradiated with 501 (eV, 5X 10") using the self-line method using the Si02 film 102 as a mask.
/d to form an ion implantation layer 103a in a portion other than the N+ buried layer 2. The whole temperature is 1100℃
, heat treated in a non-oxidizing atmosphere for 3 hours, and the first P-type buried diffusion M! Form J30. Furthermore, in the same manner, boron was heated to 50 keV, 7
# is implanted to form an ion implantation layer 103b on the first P-type buried diffusion layer, and heat treated in a non-oxidizing atmosphere to form a second P-type buried layer 3 as shown in the same figure. Form.

By going through the above process, deep P-type buried diffusion, V
30 can be formed.

However, these N-type and P-type implants A! On ff2.3, an epitaxial layer 4 is formed by epitaxial growth as shown in FIG. To form the N-type well 5, phosphorus was applied at 125ksV and l.
Ion implantation was performed at approximately Xl0"/a#, and boron fluoride was implanted at 60 ke V + I
Ion implantation is performed at approximately 10"2/cl. After that, ion implantation for the channel stopper 11, etc. is performed, and then selective oxidation method (LOCO5) using a 5i30a film is performed.
A silicon oxide film 15 for the element portion is formed on the surface as shown in FIG. During this selective oxidation, heat treatment is performed at 1000° C. for 3 hours, including diffusion of impurities for the well 5° 6 and channel stopper 11. At this time, by connecting the shallow wells 5, 6 and the buried layers 2, 3, substantially deep wells 5, 6 are formed. Then, N
, a gate oxide film, gate electrode, source, and drain regions of a P-type MOS transistor are formed.

Bipolar transistors have a P-type base and an 8°N-type collector due to their compatibility with the above P and N-type MOS transistors! 7. An N-type emitter, Jiff9, is formed.

After that, interlayer insulation M15. Aluminum wiring 16 is formed. By going through the above process, the bipolar transistor QB and the P-type MOS transistor are placed in the N-type well 5 region on the N+ buried layer 2, and the P+ buried layer 2 is filled with the bipolar transistor QB and the P-type MOS transistor. !
An N-type MOS transistor is placed in the P-type layer 6 region above y3, and further field oxidation [10 thick 5iOz film and N0 buried layer 2°P0 buried layer 3. P-type buried diffusion layer 30.
A Bi CMO3 type semiconductor device can be constructed with elements separated by a PN junction between the N-type well 5 region and the P-type well 6 region.

The present invention can reduce the overall separation width (W 1 + W 2) by combining it with the second embodiment shown below.

FIG. 6 is a diagram illustrating another second embodiment of the present invention. N+embedded M, known from Japanese Patent Application Laid-Open No. 57-188862
A thick oxide film is formed in contact with the P2 or P1 buried M3. If the present invention is applied to an element isolation technique generally called an isoplanar structure, a structure as shown in the figure will be obtained. According to this structure, the thick oxide film is filled with P and M
3, it acts as the channel stopper 11 of FIG. 2, and it is noticeable that the separation width W2 between the P buried layer 3 and the P base M8 is reduced as shown in FIG.

That is, the distance between the P buried layer 3 and the P base M8 is substantially long (this makes it possible to prevent breakdown voltage deterioration due to punch-through of the N-type well region 5. Therefore, the separation width W2 is reduced from the conventional 1.5 μm). It was possible to reduce the size from 1.0 μm or less.

As described above, according to the second embodiment, by applying the present invention to a known isoplanar structure, the overall separation width (W
1+W2) could be reduced from the conventional 7.5 μm or more to 5 μm or less, and the bipolar transistor Qa could be highly integrated. According to another second embodiment, the drain (P layer) or the source (P'+
The separation width between the phantom) and the P buried layer can also be reduced for the above reason.6 [Effects of the Invention] According to the present invention, the PN between the N buried layers adjacent to or surrounded by the P buried layer can be reduced. Regarding element isolation by junction, P
A diffusion layer with a relatively higher impurity concentration than the type semiconductor substrate is
By forming it under the N-buried layer, the punch-through phenomenon with the P-type semiconductor substrate can be suppressed, the isolation withstand voltage between the N-buried layers can be improved, the element isolation width can be reduced, and the bipolar transistor can be highly integrated. can be achieved. Furthermore, in this embodiment, an example was described in which the method was applied to a Bi-CMO5 type semiconductor device, but it goes without saying that similar effects can be obtained.
That is, it is not limited to bipolar transistors.

[Brief explanation of the drawing]

FIG. 1 shows an element 9 for explaining the effects of the embodiment of the present invention.
2(A) and (B) are a plan view and a sectional view of a bipolar part of a conventional example of the present invention and a target B i -CMO3 type semiconductor device, and FIG. 3 is a device according to a conventional example. Diagram 4 explaining the relationship between separation width and separation withstand voltage
The figure is a diagram showing the relationship between separation width and separation depth for explaining the effects of the embodiment of the present invention. Figures 5 (A) to (F) show Bi-CMO to which the present invention is applied.
FIG. 6, which is a diagram showing the manufacturing process of a type 3 semiconductor device, is a cross-sectional view explaining another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N10 buried layer, 3...
・P+...Buried layer, 5...N type well, 6...P
Type well, /- and l1 salary base Z-N shunshai 4 3rd diagram division instigation vJt (, u masu name 4 mouth N+4shi's4rw＞=tsshi VJz (71n
) 5th

Claims (1)

[Claims] 1. A semiconductor layer of a predetermined conductivity type formed on a semiconductor substrate of a first conductivity type or a second conductivity type; The first layer is of the second conductivity type, and the impurity concentration decreases toward the semiconductor substrate.
a well region, a second well region of a first conductivity type that is formed surrounding the first well region on the surface of the semiconductor layer and whose impurity concentration decreases from the surface toward the semiconductor substrate; The first well region and the semiconductor substrate are provided adjacently to each other and are adjacent to each other.
a first buried region of a second conductivity type having an impurity concentration higher than that of the well region; and a first buried region of a second conductivity type provided adjacently between the second well region and the semiconductor substrate, and having a higher impurity concentration than the adjacent second well region. In a semiconductor device including a second buried region of a first conductivity type with an impurity concentration and a semiconductor element formed in the first well region and the second well region, the first buried region is connected to the second buried region. The second buried region is always in contact with the buried region and is formed in an island shape, and the adjacent first buried region is the boundary.
A semiconductor device characterized in that the semiconductor device is electrically isolated by a buried diffusion layer of a first conductivity type, which is selectively provided under a buried region. 2. In claim 1, the first buried region or the second buried region penetrates through the first well region or the second well region and is in contact with the first well region or the second well region. A semiconductor device characterized by being separated by an insulating material.