JP2009239096A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an MOSFET which is reducible in ON resistance. <P>SOLUTION: The semiconductor device 100 includes a semiconductor substrate SB, an n<SP>-</SP>epitaxial layer EP, a p-type back gate region BG, an n<SP>+</SP>source region SR, an n-type drain region DR, a gate electrode GE, and an n-type high-density region HR. The n<SP>+</SP>source region SR is formed on a principal surface 12 in the p-type back gate region BG. The n-type drain region DR is formed on the principal surface 12 opposite the n<SP>+</SP>source region SR with the p-type back gate region GB interposed. The gate electrode GE is formed on the p-type gack gate region BG. The n-type high-density region HR has higher n-type impurity density than the n<SP>-</SP>epitaxial layer EP, is disposed between the p-type back gate region BG and n-type drain region DR, and has peak density at a deeper position from the principal surface 12 than a pn junction portion of the p-type back gate region BG and n<SP>+</SP>source region SR. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

Conventionally, MOSFETs (metal-oxide-semiconductor field-effect transistors) including a source region, a drain region, and a gate electrode formed on a channel formation region located between these regions have been widely used. It is used. As such a MOSFET, for example, Patent Document 1 discloses a DMOS (Double-diffused MOS) power transistor for the purpose of improving a trade-off between a withstand voltage and an on-resistance (resistance in an on state). Yes. In this DMOS power transistor, a shallow n-type channel compensating implant is formed on the main surface of the semiconductor substrate.
US Pat. No. 6,700,160

  However, the configuration of Patent Document 1 has a problem that the on-resistance cannot be sufficiently reduced.

  The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device capable of sufficiently reducing on-resistance.

  The semiconductor device of this embodiment includes a semiconductor substrate, an epitaxial layer, a back gate region, a first region, a second region, a gate electrode, and a third region. The semiconductor substrate has a main surface. The epitaxial layer is formed on the main surface and is of the first conductivity type. The back gate region is formed on the main surface and is formed to form a pn junction with the epitaxial layer, and is of the second conductivity type. The first region is formed on the main surface in the back gate region and has the first conductivity type. The second region is formed on the main surface so as to face the first region across the back gate region on the main surface, and is of the first conductivity type. The gate electrode is formed on the back gate region located between the first region and the second region via an insulating film. The third region has an impurity concentration of the first conductivity type higher than that of the epitaxial layer, is located between the back gate region and the second region, and is a pn junction between the back gate region and the first region. It has a peak concentration at a position deeper than the main surface from the main surface.

  According to the semiconductor device of the present embodiment, the peak concentration is located between the back gate region and the second region, and the peak concentration is deeper from the main surface than the pn junction between the back gate region and the first region. A third region is formed so as to be. When a forward bias is applied to the semiconductor device of this embodiment, most of the carriers from the first region to the second region pass through the third region. Since the third region has a higher impurity concentration than the epitaxial layer, the resistance is low. For this reason, since the third region having a low resistance is formed in the current path, the on-resistance of the semiconductor device can be sufficiently reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 100 according to the present embodiment includes a semiconductor substrate SB having a main surface 12 and a MOSFET formed on the semiconductor substrate SB. This MOSFET is, for example, a DMOSFET. For example, a silicon substrate can be used as the semiconductor substrate SB.

The DMOSFET includes an n ⁻ epitaxial layer EP, a p-type back gate region BG, an n ⁺ source region SR as a first region, an n-type drain region DR as a second region, and a third region as a third region. The n-type high concentration region HR, the gate insulating film GI, and the gate electrode GE are included.

The semiconductor substrate SB has a p-type region IM1, and an n ⁺ buried layer BU is selectively formed on the p-type region IM1.

N ⁻ epitaxial layer EP is formed on p type region IM1 and n ⁺ buried layer BU and located on main surface 12 of semiconductor substrate SB.

The p-type back gate region BG is located on a part of the main surface 12 of the semiconductor substrate SB in the n ⁻ epitaxial layer EP so as to form a pn junction with the n ⁻ epitaxial layer EP on the lower surface.

N ⁺ source region SR is formed on main surface 12 in p type back gate region BG so as to form a pn junction with p type back gate region BG. N ⁺ source region SR is surrounded by p-type back gate region BG in main surface 12.

N-type drain region DR is formed on main surface 12 so as to sandwich p-type back gate region BG and n ⁻ epitaxial layer EP between n ⁺ source region SR.

N-type high concentration region HR is formed to be located between p-type back gate region BG and n-type drain region DR on main surface 12. N-type high concentration region HR surrounds p-type back gate region BG on main surface 12. This n-type high concentration region HR has a peak concentration deeper from the main surface 12 than the pn junction between the p-type back gate region BG and the n ⁺ source region SR. The n-type high concentration region HR has a peak concentration at a position shallower than the pn junction between the p-type back gate region BG and the n ⁻ epitaxial layer EP. The n-type high concentration region HR has an n-type impurity concentration higher than that of the n ⁻ epitaxial layer EP.

On the main surface 12 of the n-type high concentration region HR and the n-type drain region DR between the n ⁺ source region SR and the n-type drain region DR, a field insulating film FI made of, for example, a LOCOS (Local Oxidation of Silicon) oxide film is formed. Are selectively formed.

The gate electrode GE is formed on at least the p-type back gate region BG located between the n ⁺ source region SR and the n-type drain region DR via the gate insulating film GI. The gate electrode GE is formed on the n-type high concentration region HR via the gate insulating film GI, and one end of the gate electrode GE runs over the field insulating film FI. Thus, the gate electrode GE has a portion facing the n-type high concentration region HR across the gate insulating film GI and a portion facing the n ⁻ epitaxial layer EP across the field insulating film FI. A field plate effect is obtained. The gate electrode GE is made of, for example, a polycrystalline silicon film doped with impurities, silicon / tungsten, or the like. The gate insulating film GI is, for example, a silicon oxide film.

A p-type impurity region IM2 is formed on main surface 12 of semiconductor substrate SB in p-type back gate region BG so as to be adjacent to n ⁺ source region SR. The p-type impurity region IM2 has a higher p-type impurity concentration than the p-type back gate region BG, and is connected to the p-type back gate region BG on the lower surface thereof. P type impurity region IM2 is surrounded by n ⁺ source region SR on main surface 12.

  The semiconductor substrate SB has an isolation region for electrically isolating the region where the DMOSFET is formed from the region where a semiconductor element such as another MOSFET is formed. The other semiconductor element may be the same type of semiconductor element as the above-described DMOSFET, or may be a different type of semiconductor element.

The isolation region for isolating the DMOSFET is, for example, STI (Shallow Trench Isolation), and has a trench TR and a filling layer PG filling the trench TR. Trench TR is formed in semiconductor substrate SB so as to pass through n ⁻ epitaxial layer EP from main surface 12 and reach the inside of p type region IM1. The filling layer PG is, for example, a silicon oxide film.

A p ⁺ impurity region IM3 is formed in the vicinity of the lower end of trench TR. The p ⁺ impurity region IM3 has a conductivity type opposite to that of the n ⁻ epitaxial layer EP, and has a higher impurity concentration than the p type region IM1.

Interlayer insulating film OX is formed on main surface 12 so as to cover the DMOSFET. In the interlayer insulating film OX, contact holes CO reaching the n ⁺ source region SR, the p-type impurity region IM2, and the n-type drain region DR are formed. On the interlayer insulating film OX, wirings INC1 and INC2 are formed. The wiring INC1 is electrically connected to the n ⁺ source region SR and the p-type impurity region IM2 through the plug conductive layer PL in the contact hole CO. The wiring INC2 is electrically connected to the n-type drain region DR via the plug conductive layer PL in the contact hole CO. Plug conductive layer PL is made of a conductive material such as tungsten, and wirings INC1 and INC2 are made of aluminum, for example.

Subsequently, the concentration of each layer (region) of the DMOSFET constituting the semiconductor device 100 in the present embodiment shown in FIG. 1 will be described with reference to FIGS. 2 to 4 are diagrams showing impurity concentration profiles in portions along lines II-II, III-III, and IV-IV in FIG. 1, respectively. 2 to 4, the horizontal axis indicates positions along the II-II line, the III-III line, and the IV-IV line in FIG. 1, respectively, and the left end indicates the main surface 12. The numerical value on the horizontal axis is an index indicating the position of each layer, and the same numerical value is given to the same position. The vertical axis indicates the impurity concentration (unit log (cm ⁻³ )) at each position. The impurity shown in FIGS. 2 and 4 is, for example, phosphorus. The impurity in the n-type region shown in FIG. 3 is, for example, phosphorus, and the impurity in the p-type region is, for example, boron.

As shown in FIG. 2, the n-type high concentration region HR has an n-type impurity concentration of 5.0 × 10 ¹⁵ cm ^{−3 to} 4.0 × 10 ¹⁶ cm ⁻³ . The n-type high concentration region HR has a peak concentration (about 4.0 × 10 ¹⁶ cm ⁻³ ), for example, at a depth of 0.16 μm from the main surface 12 at the depth of the horizontal axis in FIG. Yes. The n-type high concentration region HR has an impurity concentration distribution that decreases from the depth position of the peak concentration toward the junction with the n ⁻ epitaxial layer EP.

As shown in FIG. 3, the n ⁺ source region SR has an n-type impurity concentration of 2.5 × 10 ¹⁷ cm ^{−3 to} 1.1 × 10 ²⁰ cm ⁻³ . In the n ⁺ source region SR, the n-type impurity concentration distribution has a peak concentration on the main surface 12 and has an impurity concentration distribution that decreases from the main surface 12 toward the junction with the p-type back gate region BG. is doing.

The p-type back gate region BG has a p-type impurity concentration of 4.0 × 10 ¹⁵ cm ^{−3 to} 1.0 × 10 ¹⁸ cm ⁻³ . The p-type impurity concentration distribution in the p-type back gate region BG has a peak concentration between the junction with the n ⁺ source region SR and the n ⁻ epitaxial layer EP, and peaks from the junction with the n ⁺ source region SR. The impurity concentration distribution increases toward the concentration and decreases from the peak concentration toward the junction with the n ⁻ epitaxial layer EP.

The pn junction between n ⁺ source region SR and p-type back gate region BG is located, for example, at a depth of 0.14 μm from main surface 12 at the depth of the horizontal axis in FIG. For this reason, as shown in FIGS. 2 and 3, the depth position (for example, 0.16 μm) of the peak concentration of the n-type high concentration region HR is the pn between the n ⁺ source region SR and the p-type back gate region BG. It is located deeper than the depth position (for example, 0.14 μm) of the joint. The depth position of the peak concentration of the n-type high concentration region HR is located shallower than the depth position (for example, 0.63 μm) of the pn junction between the p-type back gate region BG and the n ⁻ epitaxial layer EP. ing.

As shown in FIGS. 2 and 4, the n ⁻ epitaxial layer EP has an n-type impurity concentration of 3.4 × 10 ¹⁴ cm ^{3 to} 5.0 × 10 ¹⁵ cm ⁻³ .

  As the above-described n-type impurity, for example, P (phosphorus), As (arsenic), or the like can be used. As the p-type impurity, for example, B (boron) or the like can be used.

  In the present embodiment, as described later, the first and second conductivity types are determined so that the n-type channel is formed. However, the first and second conductivity types are defined so that the p-type channel is formed. The mold may be determined in reverse to the above description.

In the present embodiment, the n-type high concentration region HR is formed so that the peak concentration is shallower than the pn junction between the p-type back gate region BG and the n ⁻ epitaxial layer EP. It is not limited to. If the peak concentration of the n-type high concentration region HR is deeper than the pn junction between the p-type back gate region BG and the n ⁺ source region SR, then the peak concentration from the pn junction between the p-type back gate region BG and the n ⁻ epitaxial layer EP. May be deep.

Next, a method for manufacturing the semiconductor device 100 in the present embodiment will be described.
5 to 9 are schematic cross-sectional views showing the method of manufacturing the semiconductor device in the present embodiment in the order of steps. As shown in FIG. 5, first, a semiconductor substrate SB made of a p-type region IM1 is prepared. The surface of the semiconductor substrate SB is oxidized, and a silicon oxide film (not shown) having a thickness of, for example, 300 nm to 1000 nm is formed on the surface. A photoresist pattern (not shown) is formed on the silicon oxide film by a normal photolithography technique. Using this resist pattern as a mask, the silicon oxide film is etched and patterned. Thereafter, the resist pattern is removed by, for example, ashing.

For example, antimony (Sb) is ion-implanted into the main surface of the p-type semiconductor substrate SB using the patterned silicon oxide film as a mask. Thereafter, heat treatment is performed at a temperature of 1240 ° C., for example, to form n ⁺ buried layer BU on the main surface of semiconductor substrate SB. Thereafter, the silicon oxide film on the main surface of semiconductor substrate SB is removed.

Next, epitaxial growth is performed on the main surface of semiconductor substrate SB on which n ⁺ buried layer BU is formed, and n ⁻ epitaxial layer EP is formed on the main surface of semiconductor substrate SB.

The surface of n ⁻ epitaxial layer EP (main surface 12 of semiconductor substrate SB) is oxidized, and a silicon oxide film (not shown) having a thickness of, for example, 300 nm to 1000 nm is formed on the surface. A photoresist pattern (not shown) is formed on the silicon oxide film by a normal photolithography technique. Using this resist pattern as a mask, the silicon oxide film is etched and patterned. Thereafter, the resist pattern is removed by, for example, ashing.

Using the patterned silicon oxide film as a mask, the surface of the n ⁻ epitaxial layer EP is etched. Thereafter, the silicon oxide film on the main surface of n ⁻ epitaxial layer EP is removed.

  Next, as shown in FIG. 6, a field insulating film FI is selectively formed on the main surface of the semiconductor substrate SB by the LOCOS method. After oxidation of 300 nm to 1000 nm, a resist pattern is formed by photolithography, and the field insulating film FI is selectively etched away using the resist pattern as a mask. Thereafter, the resist pattern is removed by, for example, ashing.

Next, the semiconductor substrate SB is etched using the selectively removed field insulating film FI as a mask, and a trench TR is formed in the semiconductor substrate SB. Oxidation is performed to form a silicon oxide film having a thickness of, for example, 20 nm to 30 nm on the wall surface of trench TR. Thereafter, boron is ion-implanted to form ap ⁺ impurity region in the semiconductor substrate SB so as to surround the lower end portion of the trench TR. Thereafter, a silicon oxide film is deposited to form a filling layer PG filling the trench TR.

  Next, as shown in FIG. 7, a resist pattern is formed by photolithography, and phosphorus, for example, is ion-implanted into the main surface of the semiconductor substrate SB using the resist pattern as a mask. Thereafter, heat treatment is performed at a temperature of 800 ° C., for example, to form n-type drain region DR on the main surface of semiconductor substrate SB. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 8, a resist pattern RP having an opening up to a portion in contact with the field insulating film FI on the outer peripheral side in the n-type drain region DR is formed by photolithography. For example, phosphorus is ion-implanted into the main surface of semiconductor substrate SB using resist pattern RP as a mask. Thereby, an n-type high concentration region HR is formed on the main surface of the semiconductor substrate SB. Thereafter, the resist pattern RP is removed.

  Next, as shown in FIG. 9, the silicon oxide film is etched by several tens of nm to expose the main surface of the semiconductor substrate SB in the region where the field insulating film FI is not formed. Thereafter, by thermal oxidation, a gate insulating film GI made of a silicon oxide film having a thickness of, for example, several tens of nm is formed on the exposed main surface of the semiconductor substrate SB.

Thereafter, a polycrystalline silicon film doped with impurities (hereinafter referred to as a doped polysilicon film) and a tungsten silicide (WSi ₂ ) layer are sequentially stacked on the entire surface. The laminated doped polysilicon film and the tungsten silicide layer are patterned by a normal photolithography technique and etching technique to form the gate electrode GE.

  Next, a resist pattern is formed by photolithography, and boron, for example, is ion-implanted into the main surface of the semiconductor substrate SB using the resist pattern, the gate electrode, and the like as a mask. Thereby, the p-type back gate region BG is formed on the main surface of the semiconductor substrate SB. Thereafter, the resist pattern is removed.

Next, as shown in FIG. 1, a resist pattern is formed by photolithography, and for example, arsenic is ion-implanted into the main surface of the semiconductor substrate SB using the resist pattern, gate electrode, and the like as a mask. Thereby, n ⁺ source region SR is formed on the main surface of semiconductor substrate SB. Thereafter, the resist pattern is removed.

  Next, a resist pattern is formed by photolithography, and boron, for example, is ion-implanted into the main surface of the semiconductor substrate SB using the resist pattern, the gate electrode, and the like as a mask. Thereby, p-type impurity region IM2 is formed on the main surface of semiconductor substrate SB. Thereafter, the resist pattern is removed.

Next, an interlayer insulating film OX made of, for example, a silicon oxide film is formed with a thickness of 500 nm to 1000 nm. Thereafter, contact holes CO reaching the n-type drain region DR, the n ⁺ source region SR, and the p-type impurity region IM2 are formed in the interlayer insulating film OX by a normal photolithography technique and etching technique.

  Etching is performed so as to remain only in the contact hole CO after a laminated film of a titanium (Ti) layer and a titanium nitride (TiN) layer and a tungsten (W) film are formed so as to fill the contact hole CO, for example. Applied. Thereby, the plug conductive layer PL filling the contact hole CO is formed.

  Next, after a conductive layer made of, for example, AlCu or AlSiCu is deposited on the interlayer insulating film OX, the conductive layer is patterned by a normal photoengraving technique and etching technique to form wirings INC1 and INC2.

  Thus, the semiconductor device 100 of the present embodiment shown in FIG. 1 is manufactured. When this semiconductor device 100 is actually used, it is used, for example, as shown in FIGS. FIG. 10 is a schematic plan view showing an application example of the semiconductor device 100 in the present embodiment. In FIG. 10, the interlayer insulating film OX, the wirings INC1 and INC2, and the plug conductive layer PL in the contact hole CO are omitted. A dotted line indicating the n-type high concentration region HR in FIG. 10 is an opening of the resist pattern RP formed on the surface of the semiconductor substrate SB in FIG. 8 showing the step of forming the n-type high concentration region HR described above. 11 is a cross-sectional view taken along line XI-XI in FIG.

Then, the effect of the semiconductor device 100 of this Embodiment is demonstrated.
In order to investigate the effect of reducing the on-resistance in this embodiment, electron mobility simulation was performed on the configuration of the semiconductor device in FIGS. The results are shown in FIGS.

Here, FIG. 12 is a schematic cross-sectional view showing a configuration in which the n-type high concentration region HR is omitted from the configuration of the present embodiment shown in FIG. FIG. 13 is a schematic cross-sectional view showing a configuration when the peak concentration position of n-type high concentration region HR is shallower than the lower end position of n ⁺ source region SR in the configuration of the present embodiment shown in FIG. In the semiconductor device of FIGS. 12 and 13, the configuration other than the n-type high concentration region HR is the same as that of the present embodiment shown in FIG.

FIG. 14 is a diagram showing a profile of impurity concentration in a portion along the line XIV-XIV in FIG. In FIG. 14, the left end shows the main surface 12. The numerical value on the horizontal axis is an index indicating the position of each layer, and the same numerical value is attached to the same position as in FIGS. The vertical axis indicates the impurity concentration (unit log (cm ⁻³ )) at each position.

As shown in FIG. 14, the n-type high concentration region HR has an n-type impurity concentration of 4.0 × 10 ¹⁵ cm ^{−3 to} 0.4 × 10 ¹⁷ cm ⁻³ . The n-type high concentration region HR has a peak concentration (about 0.4 × 10 ¹⁷ cm ⁻³ ), for example, at a depth of 0.01 μm from the main surface 12 at the depth of the horizontal axis in FIG. Yes. As described above, the pn junction between n ⁺ source region SR and p-type back gate region BG is located, for example, at a depth of 0.14 μm from main surface 12 at the depth of the horizontal axis in FIG. Therefore, as shown in FIGS. 3 and 14, the peak concentration depth position (for example, 0.01 μm) of the n-type high concentration region HR is pn between the n ⁺ source region SR and the p-type back gate region BG. It is located shallower than the depth position of the junction (for example, 0.14 μm). As shown in FIGS. 2 and 14, the position of the peak concentration (for example, 0.01 μm) of the n-type high concentration region HR formed in the semiconductor device shown in FIG. 13 is the semiconductor device 100 of the present embodiment. Is closer to the main surface 12 of the semiconductor substrate SB than the peak concentration position (for example, 0.016 μm) of the n-type high concentration region HR formed in FIG.

Each of FIGS. 15 to 17 is a diagram showing electron mobility when a forward bias voltage is applied to the semiconductor device 100 in the present embodiment shown in FIG. 1 and the semiconductor devices of FIGS. 12 and 13. The numerical values described in FIGS. 15 to 17 are electron mobility (unit: cm ² V ⁻¹ s ⁻¹ ).

In the semiconductor device 100 in the present embodiment shown in FIG. 1, when a relatively positive voltage is applied to the gate electrode GE, an n-type that is an inversion layer on the surface of the p-type back gate region BG under the gate electrode GE. A channel is formed. Thereby, electrons as n-type carriers are injected from the n ⁺ source region SR into the n-type drain region DR through the inversion layer, the n-type high concentration region HR, and the n ⁻ epitaxial layer EP.

Here, comparing FIGS. 15 to 17, for example, the line indicating the mobility of electrons of 4.50 × 10 ⁻⁷ cm ² V ⁻¹ s ⁻¹ is more similar to that in FIGS. It extends deep from the main surface 12 of the SB. In other words, the semiconductor device in FIG. 15 has a wider area for obtaining higher electron mobility than the semiconductor devices in FIGS. From this, it can be seen that the semiconductor device 100 in the present embodiment shown in FIG. 1 can reduce the on-resistance more than the configuration shown in FIGS.

  The reason why the on-resistance can be reduced in the configuration of the present embodiment shown in FIG. 1 compared to the configurations shown in FIGS. 12 and 13 is considered as follows.

As described above, when the DMOSFET is on, electrons as n-type carriers are injected from the n ⁺ source region SR into the n-type drain region DR through the inversion layer, the n-type high concentration region HR, and the n ⁻ epitaxial layer EP. When electrons pass through the n-type high concentration region HR, most of the electrons are located deeper than the pn junction between the n ⁺ source region SR and the n-type back gate region BG in the n-type high concentration region HR. It is thought to pass. Therefore, it is considered that the on-resistance is reduced in the configuration of FIG. 1 in which the n-type high concentration region HR having the peak concentration is provided at a position deeper than the pn junction.

  2 and FIG. 13, since the n-type high concentration region HR does not exist in the passage path of most electrons in the n-type high concentration region HR, the on-resistance is higher than that in the configuration of FIG. It is thought that it became.

  Next, an effect that the semiconductor device 100 according to the present embodiment can reduce the variation in the current mirror circuit will be described.

  The current mirror circuit is mainly used for current control such as overcurrent detection output current control of a semiconductor element such as a MOSFET. For example, in the detection of an overcurrent flowing to the MOSFET by several A, it is impossible to directly detect the overcurrent when a current flows beyond the standard due to a malfunction or the like. For this reason, in the current mirror circuit, as shown in FIG. 18A, a reference transistor for flowing a current smaller than that of the MOSFET (output transistor) to be detected (for example, a current that is 1/1000 of the current flowing through the MOSFET flows). And an overcurrent is detected by measuring the current flowing through the reference transistor. In the current control, as shown in FIG. 18B, a current larger than that of the reference transistor can be passed through the output transistor by passing a current through the reference transistor (for example, a current 1000 times the current flowing through the MOSFET). Flows). For this reason, in the current mirror circuit, the current control of the MOSFET can be easily performed by passing a current of, for example, several hundred μA to several mA to the reference transistor. FIG. 18A is a schematic diagram showing a current mirror circuit for detecting an overcurrent. FIG. 18B is a schematic diagram showing a current mirror circuit for detecting current control.

  In this current mirror circuit, when a current of 10 μA is passed through the reference transistor, the current mirror ratio (output) obtained from the current value flowing in each of the DMOSFET and HVMOS (High-Voltage MOS) FET as the output transistor (Current / input current) is shown in FIG. 18 (c) and Table 1 below. FIG. 18C is a diagram showing the distribution of the current mirror ratio of the DMOSFET and the HVMOSFET. In FIG. 18C, the horizontal axis indicates the current mirror ratio, and the vertical axis indicates the standard normal distribution f (x).

  As shown in FIG. 18C and Table 1, it can be seen that the current mirror ratio of the DMOSFET has a larger variation than the current mirror ratio of the HVMOSFET. Further, as shown in Table 1, it can be seen that the variation (3σ / average) of the DMOSFET is about four times the variation of the HVMOSFET. From this, it can be seen that the variation in overcurrent is larger in the DMOSFET than in the HVMOSFET.

  Table 2 below shows threshold voltages VTH of the reference transistors that cause current to flow in the drain regions of the respective reference transistors when a current of 10 μA is passed through the reference transistors of the DMOSFET and the HVMOSFET. Note that the gate voltages of the reference transistors of the DMOSFET and the HVMOSFET when a current of 10 μm is supplied to the reference transistor are values that exceed the threshold voltage VTH by several hundred mV.

  Table 3 below shows threshold voltages VTH of the DMOSFETs and HVMOSFETs that are output transistors at this time.

  From Tables 2 and 3, the variation (3σ / average) in the threshold voltage VTH of each of the reference transistor and the output transistor is approximately the same as 2, 3%. However, as shown in Table 2, the threshold voltage σ (standard deviation) of the reference transistor of the DMOSFET is 1.8 times the σ of the threshold voltage of the reference transistor of the HVMOSFET. Further, as shown in Table 3, the threshold voltage σ of the output-side DMOSFET is 1.5 times the threshold voltage σ of the HVMOSFET. From this, it can be seen that the variation in current control is larger in the DMOSFET than in the HVMOSFET.

  Therefore, it can be seen from the variations in overcurrent detection and current control in Tables 1 to 3 that the variation in the current mirror circuit of the DOMOSFET is generally larger than the variation in the current mirror circuit of the HVMOSFET.

Here, the semiconductor device 100 including the DMOSFET of the present embodiment includes an n-type high concentration region HR formed by injecting an n-type impurity into a region where carriers move. Therefore, for example, if the amount of phosphorus implanted in the n-type high concentration region HR is 2 × 10 ¹² cm ⁻³ to 4 × 10 ¹² cm ⁻³ , the threshold voltage VTH of the DMOSFET is reduced to 1.0 V to 1.3 V. be able to. Since the threshold voltage of the conventional DMOSFET is about 1.6 V, the threshold voltage can be reduced in the DMOSFET of this embodiment. For this reason, according to the semiconductor device 100 of the present embodiment, variations in the current mirror circuit can be reduced.

Next, the effect that the semiconductor device 100 in this Embodiment can suppress the fall of a proof pressure is demonstrated. In the semiconductor device 100, when a reverse bias is applied to the p-type back gate region BG and the n-type drain region DR, the pn junction between the p-type back gate region BG and the n ⁻ epitaxial layer EP, and the p-type back gate A depletion layer extends from the pn junction between the region BG and the n-type high concentration region HR to the n ⁻ epitaxial layer EP. In the present embodiment, the peak concentration of the n-type high concentration region HR is shallower than the pn junction between the p-type back gate region BG and the n ⁻ epitaxial layer EP. Due to the n-type high concentration region HR having a higher impurity concentration than the n ⁻ epitaxial layer EP, there are few regions where the spread of the depletion layer is suppressed. For this reason, the fall of a proof pressure can be suppressed. That is, in order to ensure a breakdown voltage, depletion may be performed in the n ⁻ epitaxial layer EP extending from the n ⁺ source region SR to the n type drain region DR, so that the n type high concentration region HR is formed on the main surface 12 of the semiconductor substrate SB. Even if is formed, it is possible to suppress a decrease in breakdown voltage.

  Next, functions and effects that can reduce the size of the semiconductor device 100 according to the present embodiment will be described.

  In semiconductor device 100 in the present embodiment, trench isolation is used for isolation between DMOSFET and other semiconductor elements. For this reason, the plane occupation area required for isolating DMOSFET can be made smaller than the case where DMOSFET and another semiconductor element are isolate | separated by diffusion of an impurity. Therefore, the device can be reduced in size.

  In the semiconductor device 100, the region for isolating the elements includes the trench TR and the filling layer PG filling the trench TR. For this reason, the DMOSFET and other semiconductor elements can be more reliably electrically separated by the filling layer PG while reducing the size of the semiconductor device 100.

(Embodiment 2)
FIG. 19 is a schematic cross-sectional view showing the configuration of the semiconductor device in the present embodiment. As shown in FIG. 19, the semiconductor device 101 in the present embodiment includes, for example, a DMOSFET.

  As shown in FIG. 19, the semiconductor device 101 in the present embodiment has basically the same configuration as the semiconductor device 100 in the first embodiment shown in FIG. 1, but the end portion of the field insulating film FI. The difference is that the n-type high concentration region HR is arranged at an interval from the (edge) 14.

Specifically, the n-type high concentration region HR is opposed to the field insulating film FI with the n ⁻ epitaxial layer EP interposed therebetween.

  The n-type high concentration region HR is separated from the end portion 14 of the field insulating film FI by, for example, 0.3 μm or more and 0.7 μm or less, preferably about 0.5 μm. Here, the end portion 14 of the field insulating film FI is a so-called bird's beak, which is a starting point where the width narrows from a portion that forms a certain wide width. The electric field concentrates on the end portion 14 of the field insulating film FI.

FIG. 20 is a diagram showing a profile of impurity concentration along the line XX-XX in FIG. In FIG. 20, the left end shows the end portion 14 of the field insulating film FI. The numerical value on the horizontal axis is an index indicating the position of each layer. The vertical axis indicates the impurity concentration (unit log (cm ⁻³ )) at each position. The impurity shown in FIG. 20 is, for example, phosphorus.

As shown in FIG. 20, the n-type high concentration region HR has an n-type impurity concentration of 3.2 × 10 ¹⁵ cm ^{−3 to} 7.5 × 10 ¹⁶ cm ⁻³ . The n-type high concentration region HR has a peak concentration near the pn junction with the p-type back gate region BG, and the impurity concentration increases from the end 14 of the field insulating film FI toward the p-type back gate region BG. It has an impurity concentration distribution. Further, an n-type impurity of 7.5 × 10 ¹⁶ cm ⁻³ is implanted into the p-type back gate region BG.

  Since the configuration other than the above shown in FIG. 19 is substantially the same as the configuration shown in FIG. 1 described above, the same components are denoted by the same reference numerals, and description thereof will not be repeated.

Next, a method for manufacturing the semiconductor device 101 in this embodiment will be described.
FIG. 21 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device 101 in the present embodiment. The manufacturing method of the semiconductor device 101 in the present embodiment basically has the same configuration as the manufacturing method of the semiconductor device 100 in the first embodiment, but differs in the region where the n-type high concentration region HR is formed. ing.

  Specifically, as shown in FIG. 21, a resist pattern RP having an opening in a region surrounded by the inner peripheral side of the thick field insulating film FI is formed by photolithography. That is, the resist pattern RP is formed so that ions are not implanted into the end portion 14 of the field insulating film FI. For example, phosphorus is ion-implanted into the main surface of semiconductor substrate SB using resist pattern RP as a mask. As a result, an n-type high concentration region HR is formed on the main surface of the semiconductor substrate SB at a distance from the end portion 14 of the field insulating film FI. Thereafter, the resist pattern RP is removed.

  Since the manufacturing method of the present embodiment is almost the same as the manufacturing method of the first embodiment with respect to the steps other than those described above, the description thereof will not be repeated.

  Thus, the semiconductor device 101 of the present embodiment shown in FIG. 19 is manufactured. When this semiconductor device 101 is actually used, it is used, for example, as shown in FIGS. FIG. 22 is a schematic plan view showing an application example of the semiconductor device 101 in the present embodiment. In FIG. 22, the interlayer insulating film OX, the wirings INC1 and INC2, and the plug conductive layer PL in the contact hole CO are omitted. A dotted line indicating the n-type high concentration region HR in FIG. 22 is an opening of the resist pattern RP formed on the surface of the semiconductor substrate SB in FIG. 21 showing the step of forming the n-type high concentration region HR described above. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG.

Then, the effect of the semiconductor device 101 of this Embodiment is demonstrated.
First, the effect that the semiconductor device 101 in this embodiment can suppress a decrease in breakdown voltage will be described.

In the semiconductor device 101, the n-type high-concentration region HR is disposed at a distance from the end portion 14 of the field insulating film FI. Since the electric field concentrates in a region called a bird's beak including the end portion 14 of the field insulating film FI, the breakdown voltage decreases. Since the n ⁻ epitaxial layer EP having an impurity concentration lower than that of the n-type high concentration region HR is disposed at the end portion 14, it is possible to suppress a decrease in breakdown voltage.

  Next, an effect that the semiconductor device 101 in this embodiment can reduce the on-resistance will be described.

In order to investigate the effect of reducing the on-resistance in this embodiment, electron mobility simulation was performed on the structure of the semiconductor device 101 in FIG. The result is shown in FIG. FIG. 24 is a diagram showing the mobility of electrons when a forward bias voltage is applied to the semiconductor device 101 in the present embodiment shown in FIG. The numerical value described in FIG. 24 is the electron mobility (unit: cm ² V ⁻¹ s ⁻¹ ).

In the semiconductor device 102 in the present embodiment shown in FIG. 24, when a relatively positive voltage is applied to the gate electrode GE, an n-type that is an inversion layer on the surface of the p-type back gate region BG below the gate electrode GE. A channel is formed. Thereby, electrons as n-type carriers are injected from the n ⁺ source region SR into the n-type drain region DR through the inversion layer, the n-type high concentration region HR, and the n ⁻ epitaxial layer EP.

16 and 17 shown in Embodiment 1 are compared with FIG. 24, the line indicating the mobility of electrons of, for example, 4.50 × 10 ⁻⁷ cm ² V ⁻¹ s ⁻¹ is shown in FIG. 16 and FIG. 24 extends deeper from the main surface 12 of the semiconductor substrate SB in FIG. That is, the region through which current flows in the semiconductor device in FIG. 24 is larger than the region through which current flows in the semiconductor devices in FIGS. From this, it can be seen that the semiconductor device 102 in the present embodiment shown in FIG. 2 can sufficiently reduce the on-resistance as compared with the configuration shown in FIGS.

  Furthermore, as described above, the n-type high concentration region HR is disposed at a distance from the end portion 14 of the field insulating film FI, so that a decrease in breakdown voltage can be suppressed. For this reason, an n-type impurity having a high impurity concentration can be implanted into the n-type high concentration region HR. Therefore, the resistance of the n-type high concentration region HR can be further reduced.

(Embodiment 3)
FIG. 25 is a schematic cross-sectional view showing the configuration of the semiconductor device in the present embodiment. As shown in FIG. 25, the semiconductor device 102 in the present embodiment includes, for example, a DMOSFET.

  As shown in FIG. 25, the semiconductor device 102 in the present embodiment has basically the same configuration as the semiconductor device 100 in the first embodiment shown in FIG. 1, but the lower surface 15 of the field insulating film FI. This is different in that it further includes a p-type impurity region IM4 (fourth region) in which a p-type impurity is implanted in a region in contact with.

  Specifically, the p-type impurity region IM4 is provided so as to be in contact with the region extending from the lower surface 15 of the field insulating film FI through the end portion 14 to the junction with the main surface 12 of the semiconductor substrate SB. That is, the p-type impurity region IM4 is provided in contact with a region called a bird's beak. The p-type impurity region IM4 is provided to alleviate electric field concentration at the end portion 14 of the field insulating film FI.

In the present embodiment, p-type impurity region IM4 is a region having a conductivity type opposite to that of n ⁺ source region SR, n-type high concentration region HR, and n-type drain region DR. However, p type impurity region IM4 may have the same conductivity type as n ⁺ source region SR, n type high concentration region HR, and n type drain region DR. In this case, since a p-type impurity is implanted into the p-type impurity region IM4, the n-type impurity concentration is lower than that of the n ⁻ epitaxial layer.

Further, the n-type high concentration region HR is arranged at a distance from the end portion 14 of the field insulating film FI as in the second embodiment. Similar to the first embodiment, the n-type high concentration region HR may be provided so as to be in contact with the end portion 14 of the field insulating film FI. The n-type high concentration region HR and the p-type impurity region IM4 may be in contact with each other or may not be in contact with each other. If not in contact, for example, n ⁻ epitaxial layer EP is arranged between p-type impurity region IM4 and n-type high concentration region HR.

Next, with reference to FIG. 26, the concentration of the p-type impurity region constituting the semiconductor device 102 in the present embodiment will be described. FIG. 26 is a diagram showing a profile of impurity concentration along the line XXVI-XXVI in FIG. In FIG. 26, the left end shows the lower surface 15 of the field insulating film FI. The vertical axis indicates the impurity concentration (unit log (cm ⁻³ )) at each position. The impurity shown in FIG. 26 is, for example, boron.

As shown in FIG. 26, the p-type impurity region IM4 has a p-type impurity concentration of 3.1 × 10 ¹⁵ cm ⁻³ or less. The p-type impurity concentration distribution in the p-type impurity region IM4 has a peak concentration between the junction with the lower surface 15 of the field insulating film FI and the junction with the n ⁻ epitaxial layer EP. The impurity concentration distribution increases from the junction with the lower surface 15 toward the peak concentration and decreases from the peak concentration toward the junction with the n ⁻ epitaxial layer EP.

  Since the configuration other than the above shown in FIG. 25 is substantially the same as the configuration shown in FIG. 1 described above, the same components are denoted by the same reference numerals, and description thereof will not be repeated.

Next, a method for manufacturing the semiconductor device 102 in this embodiment will be described.
FIG. 27 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device 102 in the present embodiment. The manufacturing method of the semiconductor device 102 in the present embodiment basically has the same configuration as the manufacturing method of the semiconductor device 100 in the first embodiment, but the region for forming the n-type high concentration region HR and p It differs in that the type impurity region IM4 is further formed.

  Specifically, as described in the second embodiment with reference to FIG. 21, the n-type high concentration region HR is formed on the main surface of the semiconductor substrate SB at a distance from the end portion 14 of the field insulating film FI. The

  Next, as shown in FIG. 27, a resist pattern RP having an opening on a region near the n-type high concentration region HR on the lower surface 15 of the field insulating film FI is formed by photolithography. For example, boron is ion-implanted into the main surface of semiconductor substrate SB using resist pattern RP as a mask. As a result, the p-type impurity region IM4 is formed in the region in contact with the lower surface 15 of the field insulating film FI on the main surface of the semiconductor substrate SB. Thereafter, the resist pattern RP is removed.

  Since the manufacturing method of the present embodiment is almost the same as the manufacturing method of the first embodiment with respect to the steps other than those described above, the description thereof will not be repeated.

  Thus, the semiconductor device 102 of the present embodiment shown in FIG. 25 is manufactured. When this semiconductor device 102 is actually used, it can be used, for example, as shown in FIGS. FIG. 28 is a schematic plan view showing an application example of the semiconductor device 102 in the present embodiment. In FIG. 28, the interlayer insulating film OX, the wirings INC1 and INC2, and the plug conductive layer PL in the contact hole CO are omitted. A dotted line indicating the n-type high concentration region HR in FIG. 28 is an opening of the resist pattern RP formed on the surface of the semiconductor substrate SB in FIG. 27 showing the step of forming the n-type high concentration region HR described above. 29 is a cross-sectional view taken along line XXIX-XXIX in FIG.

Then, the effect of the semiconductor device 102 of this Embodiment is demonstrated.
First, an effect that the semiconductor device 102 in this embodiment can suppress a decrease in breakdown voltage will be described.

In the present embodiment, p-type impurity region IM4 is formed in a region in contact with lower surface 15 of field insulating film FI. The p-type impurity regions IM4 is, n-type high-concentration region HR and the n ^- constitute the epitaxial layer EP and pn junction, this pn junction n-type high-concentration region HR and the n ^- depletion layer in the epitaxial layer EP It has already occurred. The p-type impurity region IM4 can function as a pseudo depletion layer because it has a floating potential and a low concentration. Therefore, when the reverse bias is applied, a depletion layer formed by a pn junction between the p-type impurity region IM4, the n-type high concentration region HR and the n ⁻ epitaxial layer EP, and a pseudo depletion layer formed by the p-type impurity region IM4. Already exist, a depletion layer extends from the pn junction of the p-type back gate region BG, the n-type high concentration region HR, and the n ⁻ epitaxial layer EP into the n ⁻ epitaxial layer EP. Accordingly, since the spread of the entire depletion layer is increased, the breakdown voltage of the semiconductor device 102 can be improved.

  Note that even if the p-type impurity region IM4 is n-type, it can function as a pseudo depletion layer because it has a floating potential and a low concentration. This has the effect of improving the breakdown voltage of the semiconductor device 102.

  Next, an effect that the semiconductor device 102 in this embodiment can reduce on-resistance will be described.

In the semiconductor device 101, when a relatively positive voltage is applied to the gate electrode GE, electrons as n-type carriers are transferred from the n ⁺ source region SR to the p-type back gate region BG and the n-type high concentration region HR. Through the n-type drain region DR. In this current path, there are few carriers passing through the p-type impurity region IM4 in contact with the lower surface 15 of the field insulating film FI, and there are many carriers passing through the n-type high concentration region HR. Therefore, even if the n-type high concentration region HR is not formed in the region in contact with the lower surface 15 of the field insulating film FI, the semiconductor device in which the n-type high concentration region HR of FIG. 12 is not formed is shown in FIG. Compared with the semiconductor device in which the n-type high concentration region HR is formed at a shallow position, the semiconductor device 102 in the present embodiment can sufficiently reduce the on-resistance.

  Here, the inventor examined the on-resistance and breakdown voltage of the semiconductor devices 100 to 102 of the first to third embodiments described above and the semiconductor device in which the n-type high concentration region HR in FIG. 12 is not formed. . The contents will be described below.

Specifically, the n-type high concentration region HR of the semiconductor device 100 of the first embodiment shown in FIG. 1 and the semiconductor device 101 of the second embodiment shown in FIG. 19 is 1 × 10 ¹² / cm ² and 3 × 10. ^It has two types of n-type impurity concentration of ¹² / cm ² . The n-type high concentration region HR of the semiconductor device 102 of the third embodiment shown in FIG. 25 has one type of n-type impurity concentration of 3 × 10 ¹² / cm ² . The n-type impurity implanted into the n-type high concentration region HR is phosphorus. Further, the semiconductor device shown in FIG. 12 does not include an n-type high concentration region. The on-resistance and breakdown voltage of each semiconductor device are shown in Table 4 below.

As shown in Table 4, when the implantation amount of phosphorus was 3 × 10 ¹² / cm ² , the peak concentration was formed at a position deeper than the pn junction between the p-type back gate region BG and the n ⁺ source region SR. In the first to third embodiments in which the n-type high concentration region HR is formed, the on-resistance can be reduced as compared with the semiconductor device of the comparative example in which the n-type high concentration region HR is not formed. In the semiconductor device 100 of the first embodiment in which the n-type high concentration region HR is located on the entire surface between the p-type back gate region BG and the n ⁺ source region SR on the main surface 12 of the semiconductor substrate SB, 0 A low on-resistance of .720 mΩcm ² can be realized.

Further, the on-resistance can be further reduced by increasing the impurity concentration of the n-type high concentration region HR by comparing the amount of phosphorus implanted between 3 × 10 ¹² / cm ² and 1 × 10 ¹² / cm ² .

  Note that the p-type impurity region IM4 is formed in a region in contact with the lower surface 15 of the semiconductor device 101 and the field insulating film FI according to the second embodiment in which the n-type high concentration region HR is disposed at a distance from the end 14 of the field insulating film FI. The arranged semiconductor device 102 in the third embodiment has lower on-resistance than the semiconductor device of the comparative example in which the n-type high concentration region HR is not formed, and can improve the breakdown voltage compared to the first embodiment.

The resistors constituting the current path are the resistance of the p-type back gate region BG (the resistance of the region P1 in FIG. 25), and the resistance of the region located between the p-type back gate region BG and the n-type drain region DR (FIG. 25). In FIG. 25) and the resistance of the n ⁻ epitaxial layer EP located under the field insulating film FI (the resistance of the region P3 in FIG. 25). From the above description, it has been found that the resistance of the region located between the p-type back gate region BG and the n-type drain region DR among these three resistors greatly contributes to the reduction of the on-resistance. That is, if this region is made high in concentration, as shown in FIG. 25, even if the p-type impurity region IM4 serving as a pseudo depletion layer is provided below the field insulating film FI, the on-resistance can be sufficiently resisted. all right.

(Embodiment 4)
FIG. 30 is a schematic cross-sectional view showing the configuration of the semiconductor device in the present embodiment. As shown in FIG. 30, the semiconductor device 103 in the present embodiment includes, for example, an HVMOSFET.

  As shown in FIG. 30, the semiconductor device 103 in the present embodiment has basically the same configuration as that of the semiconductor device 100 in the first embodiment shown in FIG. It differs in shape and arrangement of the n-type high concentration region HR.

Specifically, the n-type high concentration region HR is arranged at a distance from the p-type back gate region BG. That is, the n-type high concentration region HR faces the p-type back gate region BG with the n ⁻ epitaxial layer EP interposed therebetween.

  Further, the position of the peak concentration of the p-type back gate region BG is deeper from the main surface 12 of the semiconductor substrate SB than the position of the peak concentration of the p-type back gate region BG of the semiconductor device 100 of the first embodiment shown in FIG. . More specifically, the peak concentration of p-type back gate region BG of semiconductor device 103 as the HVMOS in the present embodiment is located, for example, from 1 μm to 3 μm from main surface 12. On the other hand, the peak concentration of p-type back gate region BG of semiconductor devices 100 to 102 including DMOSFETs of the first to third embodiments is located, for example, less than 1 μm (about 0.16 μm in FIG. 2) from main surface 12. Yes.

  The configuration other than the above shown in FIG. 30 is substantially the same as the configuration shown in FIG. 1 described above, so the same elements are denoted by the same reference numerals and description thereof will not be repeated.

Next, a method for manufacturing the semiconductor device 103 in this embodiment will be described.
31 to 34 are schematic cross-sectional views illustrating the method of manufacturing the semiconductor device 103 according to the present embodiment in the order of steps. The manufacturing method of the semiconductor device 103 in the present embodiment basically has the same configuration as the manufacturing method of the semiconductor device 100 in the first embodiment, but the p-type back gate region BG and the n-type high concentration region. It differs in the process of forming HR.

  Specifically, first, as shown in FIGS. 5 to 7 and described in the first embodiment, the field insulating film FI is formed on the main surface of the semiconductor substrate SB, and n is formed on the main surface of the semiconductor substrate SB. A type drain region DR is formed.

Next, as shown in FIG. 31, a resist pattern RP is formed by opening a region not covered with the thick field insulating film FI by photolithography. For example, boron is ion-implanted into n ⁻ epitaxial layer EP on the main surface of semiconductor substrate SB using resist pattern RP as a mask. Thereafter, a heat treatment is performed at a temperature of 800 ° C., for example, to form a p-type impurity region to be p-type back gate region BG on the main surface of semiconductor substrate SB. Thereafter, for example, boron is further ion-implanted into the main surface of the semiconductor substrate SB in order to determine the threshold voltage VTH of the p-type back gate region BG. Thereby, the p-type back gate region BG is formed from the p-type impurity region. Thereafter, the resist pattern RP is removed.

  Next, as shown in FIG. 32, a resist having an opening from a position spaced from the p-type back gate region BG to a position in contact with the outer peripheral side of the n-type drain region DR in the field insulating film FI. A pattern RP is formed. For example, phosphorus is ion-implanted into the main surface of semiconductor substrate SB using resist pattern RP as a mask. Thereby, an n-type high concentration region HR is formed on the main surface of the semiconductor substrate SB. Thereafter, the resist pattern RP is removed.

Next, as in the first embodiment, the gate insulating film GI shown in FIG. 33 and the gate electrode GE shown in FIG. 34 are formed on the main surface of the semiconductor substrate SB. Next, as in the first embodiment, as shown in FIG. 30, n ⁺ source region SR is formed on the main surface of semiconductor substrate SB.

  Since the manufacturing method of the present embodiment is almost the same as the manufacturing method of the first embodiment with respect to the steps other than those described above, the description thereof will not be repeated.

  Thus, the semiconductor device 103 of the present embodiment shown in FIG. 30 is manufactured. This semiconductor device 103 is used as shown in FIGS. 35 and 36, for example. FIG. 35 is a schematic plan view showing an application example of the semiconductor device 103 in the present embodiment. In FIG. 35, the interlayer insulating film OX, the wirings INC1 and INC2, and the plug conductive layer PL in the contact hole CO are omitted. The dotted line indicating the n-type high concentration region HR in FIG. 35 is an opening of the resist pattern RP formed on the surface of the semiconductor substrate SB in FIG. 32 showing the step of forming the n-type high concentration region HR described above. 36 is a cross-sectional view taken along line XXXVI-XXXVI in FIG.

  As described above, according to the semiconductor device 103 in the present embodiment, when a forward voltage is applied, as in the first to third embodiments, there are many carriers passing through the n-type high concentration region HR. Therefore, it is possible to realize the semiconductor device 103 including the HVMOSFET that sufficiently reduces the on-resistance.

(Embodiment 5)
FIG. 37 is a schematic cross-sectional view showing the configuration of the semiconductor device in the present embodiment. As shown in FIG. 37, the semiconductor device 104 in the present embodiment includes, for example, an HVMOSFET.

  As shown in FIG. 37, the semiconductor device 104 in the present embodiment has basically the same configuration as that of the semiconductor device 103 in the fourth embodiment shown in FIG. 4, but the end portion of the field insulating film FI. 14 is different in that an n-type high concentration region HR is arranged at a distance.

Specifically, as in the second embodiment, the n-type high concentration region HR is opposed to the field insulating film FI with the n ⁻ epitaxial layer EP interposed therebetween. The interval between the n-type high concentration region HR and the field insulating film FI is the same as that in the second embodiment.

  Since the manufacturing method of the present embodiment is almost the same as the manufacturing method of Embodiment 1 or 4 with respect to the steps other than those described above, description thereof will not be repeated.

  Next, a method for manufacturing the semiconductor device 104 in this embodiment will be described. FIG. 38 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device 104 in the present embodiment. Referring to FIG. 38, the manufacturing method of semiconductor device 104 in the present embodiment basically has the same configuration as the manufacturing method of semiconductor device 103 in the fourth embodiment, but the n-type high concentration region. It differs in the process of forming HR.

  Specifically, as shown in FIG. 38, a resist having an opening from a position spaced from the p-type back gate region BG to the outer peripheral side to a position spaced from the end 14 of the field insulating film FI. A pattern RP is formed. For example, phosphorus is ion-implanted into the main surface of semiconductor substrate SB using resist pattern RP as a mask. As a result, an n-type high concentration region HR is formed on the main surface of the semiconductor substrate SB at a distance from the end 14 of the field insulating film FI. Thereafter, the resist pattern RP is removed.

  The manufacturing method of the present embodiment is substantially the same as the manufacturing method of the first embodiment shown in FIGS. 5 to 7 or the fourth embodiment shown in FIGS. Do not repeat.

  Thus, the semiconductor device 104 of the present embodiment shown in FIG. 37 is manufactured. When this semiconductor device 104 is actually used, it is used as shown in FIGS. 39 and 40, for example. FIG. 39 is a schematic plan view showing an application example of the semiconductor device 104 in the present embodiment. In FIG. 39, the interlayer insulating film OX, the wirings INC1 and INC2, and the plug conductive layer PL in the contact hole CO are omitted. A dotted line indicating the n-type high concentration region HR in FIG. 39 is an opening portion of the resist pattern RP used in the step of forming the n-type high concentration region HR described above. 40 is a cross-sectional view taken along line XL-XL of FIG.

As described above, according to the semiconductor device 104 in the present embodiment, when a forward voltage is applied, as in the first to third embodiments, there are many carriers passing through the n-type high concentration region HR. For this reason, on-resistance can be reduced. Similarly to the second embodiment, in the semiconductor device 104, the n-type high concentration region HR is disposed with a gap from the end portion 14 of the field insulating film FI. For this reason, since the n ⁻ epitaxial layer EP having an impurity concentration lower than that of the n-type high concentration region HR is disposed at the end portion 14 of the field insulating film FI where the electric field is concentrated, a decrease in breakdown voltage can be suppressed. Therefore, the semiconductor device 104 including the HVMOSFET that sufficiently reduces the on-resistance and improves the breakdown voltage can be realized.

(Embodiment 6)
FIG. 41 is a schematic cross-sectional view showing the configuration of the semiconductor device in the present embodiment. As shown in FIG. 41, the semiconductor device 105 in the present embodiment includes, for example, an HVMOSFET.

  As shown in FIG. 41, the semiconductor device 105 in the present embodiment has basically the same configuration as the semiconductor device 103 in the fourth embodiment shown in FIG. 4, but the lower surface 15 of the field insulating film FI. A difference is that a p-type impurity region IM4 (third region) into which a p-type impurity is implanted is further provided in a region in contact with the substrate.

  Specifically, as in the third embodiment, p-type impurity region IM4 is in contact with the region extending from bottom surface 15 of field insulating film FI to the junction with main surface 12 of semiconductor substrate SB through end portion 14. Is provided. Further, the n-type high concentration region HR is arranged at a distance from the end portion 14 of the field insulating film FI as in the second embodiment.

  Next, a method for manufacturing the semiconductor device 105 in this embodiment will be described. FIG. 42 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device 105 in the present embodiment. Referring to FIG. 42, the manufacturing method of semiconductor device 105 in the present embodiment basically has the same configuration as the manufacturing method of semiconductor device 103 in the fourth embodiment, but the n-type high concentration region. The difference is that a region for forming HR and a p-type impurity region IM4 are further formed.

  Specifically, as described in the fourth embodiment with reference to FIG. 38, the n-type high concentration region HR is formed on the main surface of the semiconductor substrate SB at a distance from the end portion 14 of the field insulating film FI. The

  Next, as shown in FIG. 42, a resist pattern RP having an opening on a region near the n-type high concentration region HR on the lower surface 15 of the field insulating film FI is formed by photolithography. For example, boron is ion-implanted into the main surface of semiconductor substrate SB using resist pattern RP as a mask. As a result, the p-type impurity region IM4 is formed in the region in contact with the lower surface 15 of the field insulating film FI on the main surface of the semiconductor substrate SB. Thereafter, the resist pattern RP is removed.

  The manufacturing method of the present embodiment is the manufacturing method of the first embodiment shown in FIGS. 5 to 7, the fourth embodiment shown in FIGS. 31, 33 to 35, or the fifth embodiment shown in FIG. The description will not be repeated.

  Thus, the semiconductor device 105 of the present embodiment shown in FIG. 41 is manufactured. When this semiconductor device 105 is actually used, it is used as shown in FIGS. 43 and 44, for example. FIG. 43 is a schematic plan view showing an application example of the semiconductor device 105 in the present embodiment. In FIG. 43, the interlayer insulating film OX, the wirings INC1 and INC2, and the plug conductive layer PL in the contact hole CO are omitted. A dotted line indicating the n-type high concentration region HR in FIG. 43 is an opening of the resist pattern RP used in the above-described step of forming the n-type high concentration region HR. 44 is a cross-sectional view taken along line XLIV-XLIV in FIG.

  As described above, according to the semiconductor device 104 in the present embodiment, when a forward voltage is applied, as in the first to third embodiments, there are many carriers passing through the n-type high concentration region HR. For this reason, the on-resistance can be sufficiently reduced.

Similarly to the third embodiment, since the p-type impurity region IM4 is formed in the region in contact with the lower surface 15 of the field insulating film FI, the p-type impurity region IM4 and the n-type high concentration are applied when a reverse bias is applied. The p-type back gate region BG and the n-type high-concentration region HR and the p-type back gate region BG in a state where a depletion layer due to a pn junction with the region HR and the n ⁻ epitaxial layer EP and a pseudo depletion layer due to the p-type impurity region IM4 already exist. the n ^- that the depletion layer into the epitaxial layer EP extends ^- n from the pn junction between the epitaxial layer EP. Accordingly, since the spread of the entire depletion layer is increased, the breakdown voltage of the semiconductor device 102 can be improved. Therefore, the semiconductor device 104 including the HVMOSFET that sufficiently reduces the on-resistance and improves the breakdown voltage can be realized.

  Here, the inventor examined the on-resistance and breakdown voltage of the semiconductor devices 103 to 105 of the above-described fourth to sixth embodiments and the semiconductor device in which the n-type high concentration region HR in FIG. 45 is not formed. . The contents will be described below.

  FIG. 45 is a schematic cross-sectional view showing a semiconductor device in which an n-type high concentration region is not formed. The semiconductor device in FIG. 45 is the same as that in the fourth embodiment shown in FIG. 30 except for the n-type high concentration region HR.

Specifically, the n-type high concentration region HR of the semiconductor device 103 of the fourth embodiment shown in FIG. 30, the semiconductor device 104 of the fifth embodiment shown in FIG. 37, and the semiconductor device 105 of the sixth embodiment shown in FIG. Has an n-type impurity concentration of 1 × 10 ¹² / cm ² . The n-type impurity implanted into the n-type high concentration region HR is phosphorus. The on-resistance and breakdown voltage of each semiconductor device are shown in Table 5 below.

As shown in Table 5, the n-type high concentration region HR having a peak concentration formed deeper than the pn junction between the p-type back gate region BG and the n ⁺ source region SR is formed. -6 can reduce on-resistance compared with the semiconductor device of the comparative example in which the n-type high concentration region is not formed. In the semiconductor device 103 of the fourth embodiment in which the n-type high concentration region HR is located on the entire surface between the p-type back gate region BG and the n ⁺ source region SR on the main surface 12 of the semiconductor substrate SB, 1 A low on-resistance of 108 mΩcm ² can be realized.

  Note that the semiconductor device 105 according to the sixth embodiment in which the p-type impurity region IM4 is arranged in the region in contact with the lower surface 15 of the field insulating film FI is more resistant to on-resistance than the semiconductor device of the comparative example in which the n-type high concentration region is not formed. The breakdown voltage can be improved as compared with the fourth embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

It is a schematic sectional drawing which shows a structure of the semiconductor device in Embodiment 1 of this invention. It is a figure which shows the profile of the impurity concentration of the part in alignment with the II-II line | wire of FIG. It is a figure which shows the profile of the impurity concentration of the part in alignment with the III-III line | wire of FIG. It is a figure which shows the profile of the impurity concentration of the part in alignment with the IV-IV line | wire of FIG. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 1 of this invention in order of a process. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 1 of this invention in order of a process. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 1 of this invention in order of a process. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 1 of this invention in order of a process. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 1 of this invention in order of a process. It is a schematic plan view which shows the example of application of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which follows the XI-XI line of FIG. It is a schematic sectional drawing which shows the structure which abbreviate | omitted n type high concentration area | region HR from the structure of Embodiment 1 of this invention. 5 is a schematic cross-sectional view showing a configuration when the peak concentration position of the n-type high concentration region HR is shallower than the lower end position of the n ⁺ source region SR in the configuration of the first embodiment of the present invention. FIG. It is a figure which shows the profile of the impurity concentration of the part in alignment with the XIV-XIV line | wire of FIG. It is a figure which shows the mobility of an electron when the voltage of a forward bias is applied to the semiconductor device in Embodiment 1 of this invention. FIG. 13 is a diagram showing electron mobility when a forward bias voltage is applied to the semiconductor device of FIG. 12. It is a figure which shows the mobility of an electron when the voltage of a forward bias is applied to the semiconductor device of FIG. (A) is a schematic diagram showing a current mirror circuit for detecting overcurrent, (b) is a schematic diagram showing a current mirror circuit for detecting current control, and (c) is a diagram of DMOSFET and HVMOSFET. It is a figure which shows distribution of a current mirror ratio. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 2 of this invention. It is a figure which shows the profile of the impurity concentration which follows the XX-XX line of FIG. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic plan view which shows the example of application of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which follows the XXIII-XXIII line | wire of FIG. It is a figure which shows the mobility of an electron when the voltage of a forward bias is applied to the semiconductor device in Embodiment 2 of this invention. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 3 of this invention. It is a figure which shows the profile of the impurity concentration which follows the XXVI-XXVI line | wire of FIG. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 3 of this invention. It is a schematic plan view which shows the example of application of the semiconductor device in Embodiment 3 of this invention. It is sectional drawing which follows the XXIX-XXIX line | wire of FIG. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 4 of this invention. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 4 of this invention in order of a process. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 4 of this invention in order of a process. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 4 of this invention in order of a process. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 4 of this invention in order of a process. It is a schematic plan view which shows the example of application of the semiconductor device in Embodiment 4 of this invention. FIG. 36 is a cross-sectional view taken along line XXXVI-XXXVI in FIG. 35. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 5 of this invention. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 5 of this invention. It is a schematic plan view which shows the example of application of the semiconductor device in Embodiment 5 of this invention. It is sectional drawing which follows the XL-XL line | wire of FIG. It is a schematic sectional drawing which shows the structure of the semiconductor device in Embodiment 6 of this invention. It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device in Embodiment 6 of this invention. It is a schematic plan view which shows the example of application of the semiconductor device in Embodiment 6 of this invention. It is sectional drawing which follows the XLIV-XLIV line | wire of FIG. It is a schematic sectional drawing which shows the semiconductor device in which the n-type high concentration area | region is not formed.

Explanation of symbols

12 main surface, 14 end, 15 bottom surface, 100 to 105 semiconductor device, BG p-type back gate region, BU n ⁺ buried layer, CO contact hole, DR n-type drain region, EP epitaxial layer, FI field insulating film, GE gate electrode, GI gate insulating film, HR n-type high concentration region, IM1 p-type region, IM2 p-type impurity region, IM3 p ⁺ -type impurity region, IM4 p-type impurity region, INC1, INC2 wiring, OX interlayer insulating film, PG filling layer, PL plug conductive layer, RP resist pattern, SB semiconductor substrate, SR n ⁺ source region, TR trench.

Claims (3)

A semiconductor substrate having a main surface;
An epitaxial layer of a first conductivity type formed on the main surface;
A second conductivity type back gate region formed on the main surface and formed to form a pn junction with the epitaxial layer;
A first region of a first conductivity type formed on the main surface in the back gate region;
A second region of the first conductivity type formed on the main surface so as to face the first region across the back gate region on the main surface;
A gate electrode formed on the back gate region located between the first region and the second region via an insulating film;
A pn junction between the back gate region and the first region, having an impurity concentration of the first conductivity type higher than that of the epitaxial layer, located between the back gate region and the second region And a third region having a peak concentration at a position deeper than the main surface. A field insulating film formed on the main surface between the second region and the third region;
2. The semiconductor device according to claim 1, wherein the third region is arranged at an interval from an end of the field insulating film. A field insulating film formed on the main surface between the second region and the third region;
2. The semiconductor device according to claim 1, further comprising a fourth region formed in a region in contact with the lower surface of the field insulating film and implanted with a second conductivity type impurity.

Images