JP2019117883A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a semiconductor device and a manufacturing method thereof that can improve the on-breakdown voltage.SOLUTION: A pback gate region BGR is sandwiched between ndrain regions DRA and DRB. An nsource region SR is adjacent to the pback gate region BGR in the channel width direction. The nsource region SR includes a first region SRA and a second region SRB located closer to the ndrain region DRB than the first region SRA. A buried insulating layer BI1 in which a recess portion TR1 is buried extends deeper from the main surface MS of a semiconductor substrate SB than the first region SRA and the second region SRB between the first region SRA and the second region SRB.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a semiconductor device and a method of manufacturing the same.

  The elements required to have a high withstand voltage are disclosed, for example, in WO 2012/127960 (Patent Document 1), WO 2011/161748 (Patent Document 2) and JP 2013-135188 (Patent Document 3). It is done.

  Patent Document 1 discloses a structure in which the source is surrounded by a drain in plan view, and the source and the back gate are repeated while being adjacent in the channel width direction. Patent Documents 2 and 3 disclose structures in which a source and a back gate are arranged in the channel length direction, and an insulating film is sandwiched between the source and the back gate.

International Publication No. 2012/127960 International Publication No. 2011/161748 JP, 2013-135188, A

  In Patent Document 1, parasitic hole current flows into the source and the back gate from each of the drains on both sides. For this reason, the potential of the back gate is likely to be raised, and the on-breakdown voltage may be reduced.

  Further, in Patent Documents 2 and 3, the insulating film between the source and the back gate is for electrical separation between the source and the back gate, and has no effect on improvement of the on-breakdown voltage.

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  The semiconductor device according to one embodiment includes a semiconductor substrate having a main surface, an element having an insulated gate field effect transistor portion, and an insulating layer. The element includes a first impurity region, at least one back gate region of a first conductivity type, and at least one second impurity region of a second conductivity type. The first impurity region has a first portion and a second portion aligned with each other in the channel length direction of the device on the main surface, and is either a drain or a collector. At least one back gate region is disposed on the main surface so as to be sandwiched between the first portion and the second portion. The at least one second impurity region is adjacent to the at least one back gate region in the channel width direction of the device on the main surface, and is either the source or the emitter. The at least one second impurity region has a first region disposed on the main surface, and a second region disposed on the main surface and closer to the second portion than the first region. The insulating layer extends from the main surface to a deeper position than the first region and the second region between the first region and the second region.

  In a method of manufacturing a semiconductor device according to one embodiment, a step of forming a recess on a main surface of a semiconductor substrate, a step of forming an insulating layer in the recess, and an insulated gate field effect transistor portion on the main surface of a semiconductor substrate And forming an element having the The steps of forming the device include the following steps.

  A first impurity region having a first portion and a second portion aligned with each other in the channel length direction of the element on the main surface and which is either a drain or a collector is formed. At least one back gate region of the first conductivity type is formed on the main surface so as to be sandwiched between the first portion and the second portion. At least one second impurity region of the second conductivity type, which is adjacent to at least one back gate region in the channel width direction of the device on the main surface and which is either the source or the emitter, is formed. The at least one second impurity region is formed to have the first region and a second region located closer to the second portion than the first region on the main surface. The first region and the second region are formed so as to sandwich the recess in which the insulating layer is embedded and to be shallower than the recess.

  According to the one embodiment, a semiconductor device capable of improving the on-breakdown voltage and a method of manufacturing the same are provided.

FIG. 1 is a plan view schematically showing a configuration of a semiconductor device in a chip state according to a first embodiment. FIG. 1 is a plan view schematically showing a configuration of a semiconductor device in a first embodiment. It is an enlarged plan view which expands and shows field R1 of FIG. It is sectional drawing in alignment with the IV-IV line of FIG. It is sectional drawing in alignment with the VV line | wire of FIG. FIG. 7 is a cross-sectional view showing a first step of a method of manufacturing a semiconductor device in the first embodiment. FIG. 14 is a cross-sectional view showing a second step of the method of manufacturing a semiconductor device in the first embodiment. FIG. 14 is a cross-sectional view showing a third step of the method of manufacturing a semiconductor device in the first embodiment. FIG. 14 is a cross-sectional view showing a fourth step of the method of manufacturing a semiconductor device in the first embodiment. FIG. 16 is a cross-sectional view showing a fifth step of the method of manufacturing a semiconductor device in the first embodiment. It is a top view which shows the structure of a comparative example. It is sectional drawing in alignment with the XII-XII line of FIG. It is a figure which shows the Id-Vd waveform in each of Embodiment 1 and a comparative example. It is a figure which shows the current density distribution in each of a comparative example (A) and Embodiment 1 (B). It is a figure which shows the potential distribution in each of a comparative example (A) and Embodiment 1 (B). FIG. 6 is a diagram for explaining an effect in the first embodiment. FIG. 16 is a cross sectional view showing a configuration of a semiconductor device in a second embodiment. FIG. 18 is a cross-sectional view showing a first step of a method of manufacturing a semiconductor device in the second embodiment. FIG. 17 is a cross-sectional view showing a second step of the method of manufacturing a semiconductor device in the second embodiment. FIG. 17 is a cross-sectional view showing a third step of the method of manufacturing a semiconductor device in the second embodiment. It is a figure which shows the current density distribution in each of Embodiment 1 (A) and Embodiment 2 (B). It is a figure which shows the potential distribution in each of Embodiment 1 (A) and Embodiment 2 (B). It is a top view which shows an example of the structure which a recessed part traverses the several source region located in a line with the channel width direction. It is sectional drawing which follows the XXIV-XXIV line of FIG. It is a top view which shows the other example of the structure which a recessed part traverses the several source region located in a line with the channel width direction. FIG. 21 is a plan view showing still another example of the configuration in which the recess traverses a plurality of source regions aligned in the channel width direction. FIG. 24 is a cross-sectional view corresponding to the cross section along the line XXIV-XXIV of FIG. 23; FIG. 10 is a cross-sectional view showing a configuration in which the contact hole extends into the recess. It is a top view showing the state where a crevice is located only in a source field, and has not reached back gate field.

Hereinafter, the present embodiment will be described based on the drawings.
Embodiment 1
As shown in FIG. 1, the semiconductor device of this embodiment is, for example, in a chip state, and has a semiconductor substrate. On the surface of the semiconductor substrate, formation regions such as a driver circuit DRC, a pre-driver circuit PDC, an analog circuit ANC, a power supply circuit PWC, a logic circuit LOC, and an input / output circuit IOC are arranged.

  The semiconductor device of the present embodiment is not limited to the semiconductor chip, and may be in a wafer state, or may be in a package state sealed with a sealing resin.

  As shown in FIGS. 2 and 3, a plurality of elements having an insulated gate field effect transistor portion are formed on the main surface MS of the semiconductor substrate SB. Each of the plurality of elements is, for example, a lateral high-breakdown voltage transistor, and is an n-channel MOS (Metal Oxide Semiconductor) transistor TR.

Each of the plurality of MOS transistors TR mainly includes a gate electrode layer GE, an n ⁺ drain region DR (first impurity region), an n ⁺ source region SR (second impurity region), and ap ⁺ back gate region BGR. Have to. In plan view, gate electrode layer GE is arranged to surround n ⁺ drain region DR. The gate electrode layer GE has a rectangular frame shape in plan view. The frame shape of the gate electrode layer GE has a shape in which the dimension in the channel width direction is larger than the dimension in the channel length direction. Gate electrode layer GE is made of, for example, polycrystalline silicon doped with an impurity (hereinafter referred to as doped polysilicon).

The gate electrode layer GE may have a non-annular shape that does not surround the n ⁺ drain region DR in plan view. The gate electrode layer GE may be, for example, only a portion extending in a straight line in a plan view.

A plurality of n ⁺ source regions SR are arranged in the channel width direction outside the frame of the gate electrode layer GE in plan view. In addition, a plurality of p ⁺ back gate regions BGR are arranged in the channel width direction outside the frame of the gate electrode layer GE in plan view. The plurality of n ⁺ source regions SR and the plurality of p ⁺ back gate regions BGR are arranged such that the n ⁺ source regions SR and the p ⁺ back gate regions BGR are alternately arranged.

  A plurality of frame-shaped gate electrode layers GE are provided. The plurality of gate electrode layers GE include, for example, three gate electrode layers GEA, GEB, and GEC. In addition, a plurality of drain regions DR are provided. The plurality of drain regions DR include, for example, three drain regions DRA, DRB, and DRC.

  The drain region DRA is surrounded by the gate electrode layer GEA in plan view. The drain region DRB is surrounded by the gate electrode layer GEB in plan view. The drain region DRC is surrounded by the gate electrode layer GEC in plan view.

  The plurality of gate electrode layers GE may be two other than three, or four or more. The plurality of drain regions DR may be two in addition to three, or four or more.

  In the present specification, the term “plan view” means a viewpoint as viewed from a direction perpendicular to the main surface MS of the semiconductor substrate SB.

  As shown in FIGS. 4 and 5, a substrate region SBR is disposed in the semiconductor substrate SB. An n-type buried region BL is disposed on the main surface MS side of the substrate region SBR. On the main surface MS side of the n-type buried region BL, the p-type epitaxial region EP is arranged to form a pn junction with the n-type buried region BL.

  A p-type well region WR1 is disposed inside the p-type epitaxial region EP. A p-type well region WR2 is disposed inside the p-type epitaxial region EP and on the main surface MS side of the p-type well region WR1.

  An n-type drift region WR3 is disposed on the main surface MS of the semiconductor substrate SB. The n-type drift region WR3 constitutes a pn junction with each of the p-type epitaxial region EP and the p-type well region WR2.

  An STI (Shallow Trench Isolation) structure ST2 is disposed on the main surface in the n-type drift region WR3. The STI structure ST2 has a trench TR2 disposed on the main surface MS of the semiconductor substrate SB, and a buried insulating layer BI2 filling the trench TR2. The STI structure ST2 has a rectangular frame shape in plan view as shown in FIGS. 2 and 3.

An n ⁺ drain region DR is disposed on the main surface MS of the semiconductor substrate SB surrounded by the STI structure ST2. The n ⁺ drain region DR is disposed on the main surface MS in the n-type drift region WR3 and is in contact with the n-type drift region WR3. The n ⁺ drain region DR has an n-type impurity concentration higher than that of the n-type drift region WR3.

  A p-type body region WR4 is disposed on the main surface MS of the semiconductor substrate SB. The p-type body region WR4 is located directly above the p-type well region WR2. The p-type body region WR4 is surrounded by the p-type epitaxial region EP and is in contact with the p-type epitaxial region EP.

As shown in FIG. 4, p ⁺ back gate region BGR is formed on main surface MS of semiconductor substrate SB so as to be surrounded by p type body region WR4. The p ⁺ back gate region BGR has a higher p-type impurity concentration than the p-type body region WR4.

In the cross section shown in FIG. 4, on main surface MS of semiconductor substrate SB, n ⁺ drain region DRA (first portion) and n ⁺ drain region DRB (second portion) are mutually spaced in the channel length direction of MOS transistor TR. Are arranged side by side. Each of the p ⁺ back gate region BGR and the p type body region WR4 is sandwiched between the n ⁺ drain region DRA and the n ⁺ drain region DRB.

As shown in FIG. 5, an n ⁺ source region SR is formed on main surface MS of semiconductor substrate SB so as to be surrounded by p type body region WR4. The n ⁺ source region SR constitutes a pn junction with the p type body region WR4.

In the cross section shown in FIG. 5, each of n ⁺ source region SR and p type body region WR 4 is sandwiched between n ⁺ drain region DRA and n ⁺ drain region DRB. The n ⁺ source region SR is adjacent to the p ⁺ back gate region BGR and the channel width direction of the MOS transistor TR as shown in FIGS. 2 and 3. The n ⁺ source region SR and the p ⁺ back gate region BGR constitute a pn junction.

As shown in FIG. 5, the n ⁺ source region SR includes a first region SRA and a second region SRB. The second region SRB is located closer to the n ⁺ drain region DRB than the first region SRA. The first region SRA and the second region SRB have the same n-type impurity concentration distribution as each other.

  The STI structure ST1 is disposed on the main surface MS of the semiconductor substrate SB between the first region SRA and the second region SRB. The STI structure ST1 has a recess TR1 and a buried insulating layer BI1 (insulating layer).

  The recess portion TR1 is formed on the main surface MS of the semiconductor substrate SB between the first region SRA and the second region SRB. The recess TR1 extends from the main surface MS to a deeper position than each of the first region SRA and the second region SRB. Therefore, the bottom of the recess TR1 extends deeper than the pn junction between each of the first region SRA and the second region SRB and the p-type body region WR4, and is located in the p-type body region WR4. . The recess TR1 may have the same depth as the trench TR2 of the STI structure ST2. In addition, the recess TR1 may extend to a position deeper than the p-type body region WR4.

  The buried insulating layer BI1 fills the entire interior of the recess TR1. Therefore, the buried insulating layer BI1 extends from the main surface MS to a deeper position than each of the first region SRA and the second region SRB. The buried insulating layer BI1 may have the same depth as the buried insulating layer BI2 of the STI structure ST2. The buried insulating layer BI1 may extend to a position deeper than the p-type body region WR4. The upper surface of the buried insulating layer BI1 may protrude above the main surface MS of the semiconductor substrate SB.

As shown in FIGS. 2 and 3, each of the recesses TR1 and the buried insulating layer BI1 is located in n ⁺ source region SR, reaches the n ⁺ source region SR to p ⁺ back gate region BGR . Specifically, each of recess TR1 and embedded insulating layer BI1 has the same n-type impurity concentration in n ⁺ source region SR and p-type impurity concentration in p ⁺ back gate region BGR in main surface MS of semiconductor substrate SB. Or to a position inside the p ⁺ back gate region BGR more than that position.

  Each of the recess part TR1 and the embedded insulating layer BI1 has a rectangular shape in plan view. One back gate region BGR is in contact with one of a pair of wall surfaces facing each other in the channel width direction among the wall surfaces constituting the recess portion TR1, and the other back gate region BGR is in contact with the other of the pair of wall surfaces. I am in contact with you.

As shown in FIG. 5, the first region SRA is in contact with the side wall (one of a pair of wall surfaces facing each other in the channel length direction) of the recess TR1 on the n ⁺ drain region DRA side. The second region SRB is in contact with the side wall on the n ⁺ drain region DRB side of the recess TR 1 (the other of the pair of wall surfaces facing each other in the channel length direction).

  As shown in FIGS. 4 and 5, gate electrode layer GE (GEA, GEB, GEC: FIG. 2) is disposed on main surface MS of semiconductor substrate SB with gate insulating layer GI interposed.

As shown in FIG. 5, gate electrode layer GEA includes gate insulating layer GI in each of p type body region WR4 and p type epitaxial region EP sandwiched between n ⁺ drain region DRA and first region SRA. Are facing each other. Further, as shown in FIG. 4, gate electrode layer GEA is formed of a gate insulating layer GI in each of p type body region WR4 and p type epitaxial region EP sandwiched between n ⁺ drain region DRA and p ⁺ back gate region BGR. Are facing each other.

As shown in FIG. 5, in gate electrode layer GEB, gate insulating layer GI is interposed in each of p type body region WR4 and p type epitaxial region EP sandwiched between n ⁺ drain region DRB and second region SRB. Are facing each other. Further, as shown in FIG. 4, gate electrode layer GEB is formed of a gate insulating layer GI in each of p type body region WR4 and p type epitaxial region EP sandwiched between n ⁺ drain region DRB and p ⁺ back gate region BGR. Are facing each other.

  Sidewall insulating layers SW are disposed on the side surfaces of the gate electrode layer GE. Over main surface MS of semiconductor substrate SB, interlayer insulating layer II is arranged to cover gate electrode layer GE. A plurality of contact holes CH1, CH2 and CH3 are arranged in the interlayer insulating layer II.

The contact hole CH1 (FIG. 5) reaches the n ⁺ source region SR from the upper surface of the interlayer insulating layer II. The contact hole CH2 (FIG. 4) reaches the p ⁺ back gate region BGR from the upper surface of the interlayer insulating layer II. The contact hole CH3 reaches the n ⁺ drain region DR from the upper surface of the interlayer insulating layer II.

  The insides of the plurality of contact holes CH1, CH2 and CH3 are filled with plug conductive layers PL1, PL2 and PL3, respectively.

Wiring layers IC1 and IC2 are disposed on the upper surface of interlayer insulating layer II. Wiring layer IC1 is electrically connected to each of n ⁺ source region SR and p ⁺ back gate region BGR via contact holes CH1 and CH2, respectively. The wiring layer IC2 is electrically connected to the n ⁺ drain region DR via the contact hole CH3.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS.
As shown in FIG. 6, an n-type buried region BL is formed on the substrate region SBR. A p-type epitaxial region EP is formed on the n-type buried region BL. In the p-type epitaxial region EP, a p-type well region WR1, a p-type well region WR2, an n-type drift region WR3 and a p-type body region WR4 are formed.

  As shown in FIG. 7, STI structures ST1 and ST2 are formed on the main surface MS of the semiconductor substrate SB. Specifically, first, the recess TR1 and the trench TR2 are formed on the main surface of the semiconductor substrate SB by the normal photolithography and etching techniques. Recesses TR1 and trenches TR2 may be formed by the same photolithographic technique and etching technique as each other, or may be formed by different photolithographic technique and etching technique from each other. Thereafter, a buried insulating layer BI2 is formed to fill each of the recess TR1 and the trench TR2.

  As shown in FIG. 8, main surface MS of semiconductor substrate SB is thermally oxidized, for example. Thereby, gate insulating layer GI is formed on main surface MS of semiconductor substrate SB. A conductive layer CL to be a gate electrode layer is formed over the gate insulating layer GI. Conductive layer CL is formed of, for example, doped polysilicon. Thereafter, conductive layer CL is patterned by the usual photolithography and etching techniques.

  As shown in FIG. 9, the gate electrode layer GE is formed from the conductive layer CL by the above patterning. The gate electrode layer GE is formed such that a part of the gate electrode layer GE rides on the STI structure ST2. Thereafter, sidewall insulating layer SW is formed on the sidewall of gate electrode layer GE.

As shown in FIG. 10, n ⁺ -type impurity ions are implanted into main surface MS of semiconductor substrate SB to form n ⁺ drain region DR and n ⁺ source region SR. Further, p ^{+ -type} back gate region BGR (not shown) is formed by ion-implanting p-type impurities into main surface MS of semiconductor substrate SB. p ⁺ back gate region BGR may be formed after the formation of the n ⁺ drain region DR and the n ⁺ source region SR, or may be formed before the formation of the n ⁺ drain region DR and the n ⁺ source region SR.

  As shown in FIGS. 4 and 5, interlayer insulating layer II is formed on main surface MS of semiconductor substrate SB. Thereafter, contact holes CH1, CH2 and CH3 are formed in the interlayer insulating layer II by ordinary photolithography and etching. Plug conductive layers PL1, PL2, PL3 are embedded in the contact holes CH1, CH2, CH3 respectively.

Thereafter, a conductive layer is formed on the upper surface of interlayer insulating layer II, and this conductive layer is patterned by the usual photolithography and etching techniques. Thus, the wiring layers IC1 and IC2 are formed from the conductive layer. Wiring layer IC1 is electrically connected to n ⁺ source region SR via plug conductive layer PL1, and is electrically connected to p ⁺ back gate region BGR via plug conductive layer PL2. It is formed. Wiring layer IC2 is formed to be electrically connected to n ⁺ drain region DR via plug conductive layer PL3.

Thus, the semiconductor device of the present embodiment is manufactured.
Next, the operation and effect of the semiconductor device of the present embodiment will be described in comparison with the comparative example shown in FIGS. 11 and 12.

As shown in FIGS. 11 and 12, the semiconductor device of the comparative example is different from the semiconductor device of the present embodiment in that it has no recess in the n ⁺ source region SR. The configuration of the comparative example other than the above is substantially the same as the configuration of the present embodiment described above, and therefore, the same elements will be denoted by the same reference numerals and the description thereof will not be repeated.

  The inventor examined the Id-Vd waveform, the current density distribution, and the potential distribution for the configuration of the present embodiment and the configuration of the comparative example. These were examined by TCAD (Technology Computer-Aided Design) simulation. The results of the Id-Vd waveform obtained as described above are shown in FIG. 13, the results of the current density distribution are shown in FIG. 14, and the results of the potential distribution are shown in FIG.

  As shown in FIG. 13, it can be seen that the value of Id of the present embodiment indicated by the solid line is lower than the Id of the comparative example indicated by the broken line at the same value of Vd. .

  FIG. 14 (A) shows the current density distribution of the comparative example, and FIG. 14 (B) shows the current density distribution of the present embodiment. As shown in FIGS. 14A and 14B, in the present embodiment, the STI structure ST1 is disposed in the source region SR, so that the current density is lower immediately below the source region SR than in the comparative example. It turns out that it has become.

  FIG. 15 (A) shows the potential distribution of the comparative example, and FIG. 15 (B) shows the potential distribution of the present embodiment. As shown in FIGS. 15A and 15B, in the present embodiment, by disposing the STI structure ST1 in the source region SR, the potential is lower immediately below the source region SR than in the comparative example. Know that

From the results of FIG. 14, in the present embodiment, by disposing the STI structure ST1 in the n ⁺ source region SR, it becomes difficult for a hole current to flow in the vicinity of the STI structure ST1. Thus, as shown in FIG. 15, the rise of the potential of the p-type body region WR4 in the vicinity of the STI structure ST1 at the lower end of the n ⁺ source region SR is suppressed. By the suppression effect of the potential rise, as shown in FIG. 15, the potential rise of the whole under the n ⁺ source region SR is also suppressed. By this series of effects, as shown in FIG. 13, in the present embodiment, the on-breakdown voltage can be improved as compared with the comparative example. The above TCAD simulation was performed with the depth of the STI structure ST1 in the present embodiment being twice the depth of the n ⁺ drain region DR.

As described above, in the present embodiment, as shown in FIG. 16, the recess TR1 of the STI structure ST1 and the buried insulating layer BI1 between the first region SRA and the second region SRB of the n ⁺ source region SR. Is provided. Therefore, for example, as indicated by a broken line in the figure, the hole current passing from the n ⁺ drain region DRB to the lower side of the second region SRB and entering the first region SRA can be blocked by the STI structure ST1. . By providing the STI structure ST1 as described above, it is possible to reduce the path in which the hole current enters the source region SR. As a result, the on-breakdown voltage BV _ON can be improved.

Further, in the present embodiment, as shown in FIGS. 2 and 3, each of recess TR1 and buried insulating layer BI1 is formed of two p ⁺ back gate regions BGR sandwiching n ⁺ source region SR in the channel width direction. Each has reached. Thus, the n ⁺ source region SR can be separated into the first region SRA and the second region SRB. Therefore, the path of the hole current to the first region SRA and the second region SRB can be further reduced by the STI structure ST1.

  Further, in the present embodiment, as shown in FIGS. 4 and 5, the entire inside of the recess portion TR1 is embedded by the embedded insulating layer BI1. Therefore, the STI structure ST1 can be easily manufactured, and the size of the STI structure ST1 can be reduced.

Further, in the present embodiment, as shown in FIGS. 2 and 3, a plurality of p ⁺ back gate regions BGR and a plurality of n ⁺ source regions SR are alternately arranged. This makes it possible to fix the potential of the p type body region WR4 in the plurality of p ⁺ back gate regions BGR.

Second Embodiment
As shown in FIG. 17, the configuration of the semiconductor device of the present embodiment is different from the configuration of the first embodiment in that the conductive layer of the source potential is inserted in the recess TR1 of the STI structure ST1. It is different.

  In the present embodiment, the buried insulating layer BI1 is disposed in the recess TR1 of the STI structure ST1. A hole TRE extending in the recess TR1 is disposed on the upper surface of the buried insulating layer BI1. The bottom of the hole TRE is located inside the buried insulating layer BI1, and the buried insulating layer BI1 remains between the bottom of the hole TRE and the bottom of the recess TR1.

  A buried conductive layer BC is disposed to fill the hole TRE. Thus, a part of the buried conductive layer BC is disposed in the recess TR1. A buried insulating layer BI1 is disposed between the buried conductive layer BC and the wall surface of the recess TR1. Buried conductive layer BC is made of, for example, doped polysilicon.

  The buried conductive layer BC protrudes above the upper surface of the buried insulating layer BI1. A sidewall insulating layer SW2 is disposed on the side wall of the portion of the buried conductive layer BC which is upward from the upper surface of the buried insulating layer BI1. In the interlayer insulating layer II, a contact hole CH4 reaching the embedded conductive layer BC from the upper surface of the interlayer insulating layer II is disposed.

The plug conductive layer PL4 is embedded in the contact hole CH4. The wiring layer IC1 is electrically connected to the embedded conductive layer BC via the plug conductive layer PL4. Thus, the buried conductive layer BC has the same potential as the n ⁺ source region SR and the p ⁺ back gate region BGR.

  Since the configuration of the present embodiment other than the above is substantially the same as the configuration of the first embodiment, the same components as those of the first embodiment are denoted by the same reference numerals in the second embodiment, and the description thereof will be given. Do not repeat

  Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS.

  The method of manufacturing a semiconductor device according to the present embodiment first goes through the steps shown in FIGS. Thereafter, as shown in FIG. 18, the hole portion TRE is formed on the upper surface of the buried insulating layer BI1 by a normal photolithographic technique and an etching technique. Thereafter, main surface MS of semiconductor substrate SB is thermally oxidized, for example, to form gate insulating layer GI on main surface MS of semiconductor substrate SB. A conductive layer CL to be a gate electrode layer is formed to fill hole TRE and to be located on gate insulating layer GI. Conductive layer CL is formed of, for example, doped polysilicon. Thereafter, conductive layer CL is patterned by the usual photolithography and etching techniques.

  As shown in FIG. 19, the gate electrode layer GE and the buried conductive layer BC are formed from the conductive layer CL by the above patterning. The gate electrode layer GE is formed such that a part of the gate electrode layer GE rides on the STI structure ST2. The embedded conductive layer BC is formed to be embedded in the hole TRE and to project upward from the hole TRE. Thereafter, sidewall insulating layer SW is formed on the sidewall of gate electrode layer GE, and sidewall insulating layer SW2 is formed on the sidewall of embedded conductive layer BC.

As shown in FIG. 20, n ⁺ -type impurity ions are implanted into main surface MS of semiconductor substrate SB to form n ⁺ drain region DR and n ⁺ source region SR. Further, p ^{+ -type} back gate region BGR (not shown) is formed by ion-implanting p-type impurities into main surface MS of semiconductor substrate SB. p ⁺ back gate region BGR may be formed after the formation of the n ⁺ drain region DR and the n ⁺ source region SR, or may be formed before the formation of the n ⁺ drain region DR and the n ⁺ source region SR.

  As shown in FIG. 17, interlayer insulating layer II is formed on main surface MS of semiconductor substrate SB. After that, contact holes CH1, CH2, CH3 and CH4 are formed in the interlayer insulating layer II by the usual photolithographic technique and etching technique. Plug conductive layers PL1, PL2, PL3, and PL4 are embedded in the contact holes CH1, CH2, CH3, and CH4, respectively.

Thereafter, a conductive layer is formed on the upper surface of interlayer insulating layer II, and this conductive layer is patterned by the usual photolithography and etching techniques. Thus, the wiring layers IC1 and IC2 are formed from the conductive layer. Wiring layer IC1 is electrically connected to p ⁺ back gate region BGR via plug conductive layer PL2 so as to be electrically connected to n ⁺ source region SR via plug conductive layer PL1. And, it is formed to be electrically connected to the buried conductive layer BC via the plug conductive layer PL4. Wiring layer IC2 is formed to be electrically connected to n ⁺ drain region DR via plug conductive layer PL3.

Thus, the semiconductor device of the present embodiment is manufactured.
Next, the operation and effect of the semiconductor device according to the present embodiment will be described in comparison with the first embodiment shown in FIGS.

  The inventor examined the current density distribution and the potential distribution for the configuration of the present embodiment and the configuration of the first embodiment. The results of the current density distribution obtained as described above are shown in FIG. 21, and the results of the potential distribution are shown in FIG.

  FIG. 21A shows the current density distribution of the first embodiment, and FIG. 21B shows the current density distribution of the present embodiment. As shown in FIGS. 21 (A) and 21 (B), in the present embodiment, by burying conductive layer BC in recessed portion TR1, the current is higher than that in the first embodiment immediately under source region SR. It can be seen that the density is low.

  22 (A) shows the potential distribution of the first embodiment, and FIG. 22 (B) shows the potential distribution of the present embodiment. As shown in FIGS. 22A and 22B, in the present embodiment, the buried conductive layer BC is disposed in the recess portion TR1 so that the potential is lower than that of the first embodiment immediately below the source region SR. It can be seen that the

From the results of FIG. 21, in the present embodiment, the hole conductive current is more difficult to flow in the vicinity of the STI structure ST1 because the embedded conductive layer BC is disposed in the recess TR1. Thus, as shown in FIG. 22, the rise of the potential of the p-type body region WR4 in the vicinity of the STI structure ST1 at the lower end of the n ⁺ source region SR is further suppressed. By the suppression effect of the potential rise, as shown in FIG. 22, the potential rise of the whole under the n ⁺ source region SR is further suppressed. Due to this series of effects, the on-breakdown voltage BV _ON can be improved in the present embodiment compared to the first embodiment.

Third Embodiment
As shown in FIG. 23, in the configuration of the semiconductor device of the present embodiment, the STI structure ST1 (concave portion TR1, buried insulating layer BI1) has a plurality of n ⁺ source regions SR in comparison with the configuration of the first embodiment. And a plurality of p ⁺ back gate regions BGR in the channel width direction.

The dimension in the channel width direction of the STI structure ST1 (recess portion TR1, buried insulating layer BI1) is smaller than, for example, the dimension in the channel width direction of the n ⁺ drain region DR. In this case, STI structures ST1 (recess TR1, buried insulating layer BI1) ends of the channel width direction is positioned on the outermost side among the plurality of n ⁺ source regions SR arranged in the channel width direction n ⁺ source region SR (hereinafter, It may reach within the endmost source region SR). Thus, the STI structure ST1 (recess portion TR1) divides all of the plurality of n ⁺ source regions SR aligned in the channel width direction.

In this configuration, as shown in FIG. 5, the n ⁺ source region SR is divided into two by the STI structure ST1 (recess portion TR1, buried insulating layer BI1). Further, as shown in FIG. 24, the p ⁺ back gate region BGR is also divided into two by the STI structure ST1 (recess portion TR1, buried insulating layer BI1).

  Since the configuration of the present embodiment other than the above is substantially the same as the configuration of the first embodiment, the same components as those of the first embodiment are denoted by the same reference numerals in the second embodiment, and the description thereof will be given. Do not repeat

Further, as shown in FIG. 25, the dimension in the channel width direction of the STI structure ST1 (recess portion TR1, buried insulating layer BI1) may be the same as the dimension in the channel width direction of the n ⁺ drain region DR. In this case, the end in the channel width direction of the STI structure ST1 (concave portion TR1, buried insulating layer BI1) is p ⁺ back gate region BGR located further outside than the endmost source region SR (hereinafter, endmost portion back (This may be called a gate region).

Further, as shown in FIG. 26, the dimension in the channel width direction of the STI structure ST1 (concave portion TR1, buried insulating layer BI1) may be larger than the dimension in the channel width direction of the n ⁺ drain region DR. In this case, the end in the channel width direction of the STI structure ST1 (the recess TR1 and the buried insulating layer BI1) may reach the outermost end in the channel width direction of the outermost back gate region BGR.

  According to the configurations shown in FIGS. 23, 25 and 26, there is no need to divide STI structure ST1 (concave portion TR1) into a plurality of parts in the channel width direction, so the layout and process are the same as in the first embodiment. It becomes easy.

Further, with the configuration of FIG. 23, the STI structure ST1 can be formed in all of the plurality of n ⁺ source regions SR aligned in the channel width direction. Thus, in all of the plurality of n ⁺ source regions SR arranged in the channel width direction, since the hole current as described with reference to FIG. 16, it is possible to reduce the route to enter the source region SR, improve the on-state breakdown voltage BV _ON It becomes possible.

  Further, with the configuration of FIG. 25, the STI structure ST1 can be disposed in the entire current path between the drain and the source.

  Further, with the configuration shown in FIG. 26, the influence of variations in layout and process on the region where current flows between the drain and the source is eliminated, so that the STI structure ST1 can be surely disposed in the hole current path. it can.

  From the configuration of FIG. 23 to FIG. 26, the end in the channel width direction of STI structure ST1 (recessed portion TR1) is the outermost end in the channel width direction of the outermost end back gate region BGR from the endmost source region SR. It may be located in the area to the end.

  The cross section taken along the line V-V in FIG. 23 may have the configuration shown in FIG. 17 and the cross section taken along the line XXIV-XXIV in FIG. 23 may have the configuration shown in FIG.

As shown in FIGS. 17 and 27, the buried conductive layer BC of the source potential is inserted in the recess TR1 of the STI structure ST1. Buried conductive layer BC traverses a plurality of n ⁺ source regions SR and a plurality of p ⁺ back gate regions BGR in the channel width direction in FIG.

Contact holes CH4 (plug conductive layer PL4) electrically connecting interconnection layer IC1 and buried conductive layer BC shown in FIGS. 17 and 27 are also shown in FIG. 23 with a plurality of n.sup. ⁺ Source regions SR and a plurality of ^p.sup. The back gate region BGR is traversed in the channel width direction.

  Since the configuration of FIG. 27 other than the above is substantially the same as the configuration of FIG. 24, the same elements as those shown in FIG. 24 are denoted by the same reference numerals in FIG.

(Modification)
As shown in FIG. 28, contact hole CH5 may extend through interlayer insulating layer II into buried insulating layer BI1, and plug conductive layer PL5 may be filled in contact hole CH5. Thus, the plug conductive layer PL5 extends into the recess TR1. The plug conductive layer PL5 has the same potential as the n ⁺ source region SR and the p ⁺ back gate region BGR by being electrically connected to the interconnection layer IC1.

  Since the configuration of FIG. 28 other than the above is substantially the same as the configuration of FIG. 5, the same elements as those shown in FIG. 5 are denoted by the same reference numerals in FIG. 28 and their description will not be repeated.

  Further, the manufacturing method of the configuration of FIG. 28 goes through the same steps as the steps of the first embodiment shown in FIGS. Thereafter, as shown in FIG. 28, interlayer insulating layer II is formed on main surface MS of semiconductor substrate SB. Thereafter, contact holes CH1, CH2, CH3 and CH5 are simultaneously formed in the interlayer insulating layer II by the usual photolithographic technique and etching technique.

  The buried insulating layer BI1 of the STI structure ST1 is etched by over-etching when forming the contact hole CH5. Thereby, the contact hole CH5 is formed to extend inside the recess part TR1.

  Thereafter, plug conductive layers PL1, PL2, PL3, and PL5 are embedded in the contact holes CH1, CH2, CH3, and CH5, respectively.

Thereafter, a conductive layer is formed on the upper surface of interlayer insulating layer II, and this conductive layer is patterned by the usual photolithography and etching techniques. Thus, the wiring layers IC1 and IC2 are formed from the conductive layer. Wiring layer IC1 is electrically connected to p ⁺ back gate region BGR via plug conductive layer PL2 so as to be electrically connected to n ⁺ source region SR via plug conductive layer PL1. And, it is formed to be electrically connected to plug conductive layer PL5. Wiring layer IC2 is formed to be electrically connected to n ⁺ drain region DR via plug conductive layer PL3.

Thus, the semiconductor device shown in FIG. 28 is manufactured.
According to the semiconductor device shown in FIG. 28, the plug conductive layer PL5 of the source potential can be formed in the recess part TR1 by a simple manufacturing process.

The contact hole CH5 and the plug conductive layer PL5 may be provided separately for each of a plurality of n ⁺ source regions SR arranged in the channel width direction. Contact hole CH5 and plug conductive layer PL5 may be provided to cross a plurality of n ⁺ source regions SR arranged in the channel width direction.

In FIGS. 2 and 3, although the structure in which STI structure ST1 reaches p ⁺ back gate region BGR in plan view has been described, STI structure ST1 is only in n ⁺ source region SR as shown in FIG. It does not have to be disposed and reach the p ⁺ back gate region BGR in plan view. In this case, the main surface MS of the semiconductor substrate SB, the entire periphery of the STI structure ST1 surrounds the n ⁺ source region SR, the n ⁺ source region SR between the STI structures ST1 and the p ⁺ back gate region BGR positioned.

Although the n-channel MOS transistor has been described in the above embodiment, the STI structure ST1 can be applied to a p-channel MOS transistor as well. Specifically, even if a structure similar to the STI structure ST1 is formed in the p ⁺ source region, the same effect as that of the above embodiment can be obtained.

Although the MOS transistor has been described in the above embodiment, the STI structure ST1 may be formed in the emitter region of an IGBT (Insulated Gate Bipolar Transistor). Specifically, in the IGBT, n ⁺ drain region DR in FIGS. 4, 5, 17, 24, 27 and 28 is replaced with p ⁺ collector region, and n ⁺ source region SR is n ⁺ emitter It is replaced by the area.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. Needless to say.

ANC analog circuit, BC embedded conductive layer, BGR back gate region, BI1, BI2 embedded insulating layer, BL n-type embedded region, CH1, CH2, CH3, CH4, CH5 contact hole, CL conductive layer, DR, DRA, DRB, DRC n ⁺ drain region, DRC driver circuit, EP p-type epitaxial region, GE, GEA, GEB, GEC gate electrode layer, GI gate insulating layer, IC1, IC2 wiring layer, II interlayer insulating layer, IOC input / output circuit, LOC logic circuit , MS main surface, PC power supply circuit, PDC pre-driver circuit, PL1, PL2, PL3, PL4, PL5 plug conductive layer, PWC power supply circuit, SB semiconductor substrate, SBR substrate region, SR n ⁺ source region, SRA first region, SRB second area, ST1, ST2 STI structure, SW, S W2 sidewall insulating layer, TR MOS transistor, TR1 recess, TR2 trench, TRE hole, WR1, WR2 p-type well region, WR3 n-type drift region, WR4 p-type body region.

Claims (11)

A semiconductor substrate having a main surface;
An element having an insulated gate field effect transistor portion,
The element is
A first impurity region having a first portion and a second portion aligned with each other in the channel length direction of the element on the main surface and being either a drain or a collector;
At least one back gate region of the first conductivity type disposed on the main surface so as to be sandwiched between the first portion and the second portion;
And at least one second impurity region of the second conductivity type adjacent to the at least one back gate region in the channel width direction of the device on the main surface and being either a source or an emitter;
The at least one second impurity region includes a first region disposed on the main surface, and a second region disposed on the main surface and located closer to the second portion than the first region. A semiconductor device, further comprising: an insulating layer extending from the main surface to a deeper position than the first region and the second region between the first region and the second region. The insulating layer is arranged to reach the at least one back gate region at the main surface,
The semiconductor device according to claim 1, wherein the first region and the second region are divided by the insulating layer. The semiconductor substrate has a recess disposed on the main surface between the first region and the second region,
The semiconductor device according to claim 1, wherein the insulating layer fills the entire inside of the recess. The semiconductor substrate has a recess disposed on the main surface between the first region and the second region,
The semiconductor device further comprises a buried conductive layer disposed inside the recess and electrically connected to the at least one second impurity region,
The semiconductor device according to claim 1, wherein the insulating layer is disposed between a wall surface of the recess and the embedded conductive layer.   The semiconductor device according to claim 1, wherein the dimension in the channel width direction of the insulating layer is shorter than the dimension in the channel width direction of the first impurity region.   The semiconductor device according to claim 1, wherein a dimension of the insulating layer in the channel width direction is the same as a dimension of the first impurity region in the channel width direction.   The semiconductor device according to claim 1, wherein the dimension in the channel width direction of the insulating layer is longer than the dimension in the channel width direction of the first impurity region. The at least one back gate region includes a plurality of back gate regions aligned in the channel width direction,
The at least one second impurity region includes a plurality of second impurity regions arranged in the channel width direction,
The semiconductor device according to claim 1, wherein the plurality of back gate regions and the plurality of second impurity regions are arranged such that the back gate region and the second impurity region are alternately arranged.   The semiconductor device according to claim 8, wherein the insulating layer traverses the plurality of second impurity regions aligned in the channel width direction. Forming a recess in the main surface of the semiconductor substrate;
Forming an insulating layer in the recess;
Forming an element having an insulated gate field effect transistor portion on the main surface of the semiconductor substrate;
The process of forming the element is
Forming a first impurity region having a first portion and a second portion arranged in the channel length direction of the device on the main surface and being either a drain or a collector;
Forming at least one back gate region of the first conductivity type disposed on the main surface so as to be sandwiched between the first portion and the second portion;
Forming at least one second impurity region of the second conductivity type adjacent to the at least one back gate region in the channel width direction of the device on the main surface and being either a source or an emitter; Including
The at least one second impurity region is formed to have a first region and a second region located closer to the second portion than the first region on the main surface.
The method of manufacturing a semiconductor device, wherein the first region and the second region sandwich the recess in which the insulating layer is embedded and are formed shallower than the recess. Forming a conductive layer so as to be located on the main surface and in the recess;
The conductive layer is patterned to form, from the conductive layer, a gate electrode layer included in the element and a buried conductive layer which is embedded in the recess and electrically connected to the at least one second impurity region. The method of manufacturing a semiconductor device according to claim 10, further comprising the step of:

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