JP6908515B2 - Semiconductor devices and their manufacturing methods - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same.

Elements that require high withstand voltage are disclosed in, for example, International Publication No. 2012/127960 (Patent Document 1), International Publication No. 2011/161748 (Patent Document 2), and Japanese Patent Application Laid-Open No. 2013-135188 (Patent Document 3). Has been done.

Patent Document 1 discloses a structure in which the source is surrounded by a drain in a plan view, and the source and the back gate are repeated while being adjacent to each other in the channel width direction. Further, Patent Documents 2 and 3 disclose a structure in which a source and a back gate are arranged in the channel length direction and an insulating film is sandwiched between the source and the back gate.

International Publication No. 2012/127960 International Publication No. 2011/161748 Japanese Unexamined Patent Publication No. 2013-135188

In Patent Document 1, a parasitic hole current flows into the source and the back gate from each of the drains on both sides. Therefore, the potential of the back gate tends to float, and the on-voltage withstand voltage may decrease.

Further, in Patent Documents 2 and 3, the insulating film between the source and the back gate is for electrical separation between the source and the back gate, and has no effect on improving the on-voltage withstand voltage.

Other challenges and novel features will become apparent from the description and accompanying drawings herein.

The semiconductor device of one embodiment includes a semiconductor substrate having a main surface, an element having an insulated gate type field effect transistor portion, and an insulating layer. The device includes a first impurity region, at least one backgate region of the first conductive type, and at least one second impurity region of the second conductive type. The first impurity region has a first portion and a second portion aligned with each other in the channel length direction of the device on the main surface, and is either a drain or a collector. At least one backgate region is arranged on the main surface so as to be sandwiched between the first portion and the second portion. The at least one second impurity region is adjacent to at least one backgate region in the channel width direction of the device on the main surface and is either a source or an emitter. At least one second impurity region has a first region arranged on the main surface and a second region arranged on the main surface and located closer to the second portion than the first region. The insulating layer extends from the main surface between the first region and the second region to a position deeper than the first region and the second region.

The method for manufacturing a semiconductor device of one embodiment includes a step of forming a recess on the main surface of the semiconductor substrate, a step of forming an insulating layer in the recess, and an insulated gate type field effect transistor portion on the main surface of the semiconductor substrate. It has a step of forming an element having the above. The step of forming the element has the following steps.

A first impurity region is formed on the main surface that has first and second portions aligned with each other in the channel length direction of the device and is either a drain or a collector. At least one backgate region of the first conductive type arranged on the main surface so as to be sandwiched between the first portion and the second portion is formed. At least one second impurity region of the second conductive type, which is adjacent to at least one backgate region in the channel width direction of the device on the main surface and is either a source or an emitter, is formed. At least one second impurity region is formed so as to have a first region and a second region located closer to the second portion than the first region on the main surface. The first region and the second region are formed so as to sandwich a recess in which an insulating layer is embedded and to be shallower than the recess.

According to the above-described embodiment, a semiconductor device capable of improving the on-voltage withstand voltage and a method for manufacturing the same are provided.

FIG. 5 is a plan view schematically showing a configuration of a semiconductor device in a chip state according to the first embodiment. It is a top view which shows schematic structure of the semiconductor device in Embodiment 1. FIG. It is an enlarged plan view which shows the area R1 of FIG. 2 enlarged. It is sectional drawing which follows the IV-IV line of FIG. It is sectional drawing which follows the VV line of FIG. It is sectional drawing which shows the 1st step of the manufacturing method of the semiconductor device in Embodiment 1. FIG. It is sectional drawing which shows the 2nd step of the manufacturing method of the semiconductor device in Embodiment 1. FIG. It is sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1. FIG. It is sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in Embodiment 1. FIG. It is sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in Embodiment 1. FIG. It is a top view which shows the structure of the comparative example. It is sectional drawing which follows the XII-XII line of FIG. It is a figure which shows the Id-Vd waveform in each of Embodiment 1 and Comparative Example. It is a figure which shows the current density distribution in each of the comparative example (A) and the first embodiment (B). It is a figure which shows the potential distribution in each of the comparative example (A) and the first embodiment (B). It is a figure for demonstrating the effect in Embodiment 1. FIG. It is sectional drawing which shows the structure of the semiconductor device in Embodiment 2. It is sectional drawing which shows the 1st step of the manufacturing method of the semiconductor device in Embodiment 2. It is sectional drawing which shows the 2nd step of the manufacturing method of the semiconductor device in Embodiment 2. It is sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 2. It is a figure which shows the current density distribution in each of Embodiment 1 (A) and Embodiment 2 (B). It is a figure which shows the potential distribution in each of Embodiment 1 (A) and Embodiment 2 (B). FIG. 5 is a plan view showing an example of a configuration in which recesses cross a plurality of source regions arranged in the channel width direction. FIG. 3 is a cross-sectional view taken along the line XXIV-XXIV of FIG. FIG. 5 is a plan view showing another example of a configuration in which a recess traverses a plurality of source regions arranged in the channel width direction. FIG. 5 is a plan view showing still another example of a configuration in which recesses traverse a plurality of source regions arranged in the channel width direction. It is sectional drawing corresponding to the cross section along the line XXIV-XXIV of FIG. It is sectional drawing which shows the structure which the contact hole extends into a recess. It is a top view which shows the state which the recess is located only in the source area and does not reach the back gate area.

Hereinafter, the present embodiment will be described with reference to the drawings.
(Embodiment 1)
As shown in FIG. 1, the semiconductor device of this embodiment is, for example, in a chip state and has a semiconductor substrate. On the surface of the semiconductor substrate, formation regions such as a driver circuit DRC, a pre-driver circuit PDC, an analog circuit ANC, a power supply circuit PWC, a logic circuit LOC, and an input / output circuit IOC are arranged.

The semiconductor device of the present embodiment is not limited to the semiconductor chip, and may be in a wafer state or in a package state sealed with a sealing resin.

As shown in FIGS. 2 and 3, a plurality of elements having an insulated gate type field effect transistor portion are formed on the main surface MS of the semiconductor substrate SB. Each of the plurality of elements is, for example, a horizontal high withstand voltage transistor and is an n-channel MOS (Metal Oxide Semiconductor) transistor TR.

Each of the plurality of MOS transistors TR mainly includes a gate electrode layer GE, an n ⁺ drain region DR (first impurity region), an n ⁺ source region SR (second impurity region), and a p ⁺ back gate region BGR. Have in. In plan view, the gate electrode layer GE is arranged so as to surround the ^{n + drain region DR.} The gate electrode layer GE has a rectangular frame shape in a plan view. The frame shape of the gate electrode layer GE has a shape in which the dimension in the channel width direction is larger than the dimension in the channel length direction. The gate electrode layer GE is made of, for example, polycrystalline silicon (hereinafter, referred to as doped polysilicon) into which impurities have been introduced.

The gate electrode layer GE may have an acyclic shape that does not surround the ^{n + drain region DR in a plan view.} The gate electrode layer GE may consist of only a portion extending in a straight line, for example, in a plan view.

^{A plurality of n +} source region SRs are arranged in the channel width direction outside the frame of the gate electrode layer GE in a plan view. ^{Further, a plurality of p +} back gate region BGRs are arranged in the channel width direction outside the frame of the gate electrode layer GE in a plan view. The plurality of n ⁺ source region SRs and the plurality of p ⁺ backgate regions BGR are ^{arranged so that the n +} source region SRs and the p ⁺ backgate region BGRs are alternately arranged.

A plurality of frame-shaped gate electrode layers GE are provided. The plurality of gate electrode layers GE include, for example, three gate electrode layers GEA, GEB, and GEC. Further, a plurality of drain region DRs are provided. The plurality of drain regions DR include, for example, three drain regions DRA, DRB, and DRC.

The drain region DRA is surrounded by the gate electrode layer GEA in plan view. The drain region DRB is surrounded by the gate electrode layer GEB in plan view. The drain region DRC is surrounded by the gate electrode layer GEC in plan view.

The plurality of gate electrode layers GE may be two in addition to three, or may be four or more. Further, the plurality of drain region DRs may be two in addition to three, or may be four or more.

In the present specification, the plan view means a viewpoint viewed from a direction perpendicular to the main surface MS of the semiconductor substrate SB.

As shown in FIGS. 4 and 5, a substrate region SBR is arranged in the semiconductor substrate SB. An n-type embedded region BL is arranged on the main surface MS side of the substrate region SBR. On the main surface MS side of the n-type embedded region BL, the p-type epitaxial region EP is arranged so as to form a pn junction with the n-type embedded region BL.

A p-type well region WR1 is arranged inside the p-type epitaxial region EP. Inside the p-type epitaxial region EP, the p-type well region WR2 is arranged on the main surface MS side of the p-type well region WR1.

An n-type drift region WR3 is arranged on the main surface MS of the semiconductor substrate SB. The n-type drift region WR3 constitutes a pn junction with each of the p-type epitaxial region EP and the p-type well region WR2.

An STI (Shallow Trench Isolation) structure ST2 is arranged on the main surface in the n-type drift region WR3. The STI structure ST2 has a groove TR2 arranged on the main surface MS of the semiconductor substrate SB, and an embedded insulating layer BI2 that fills the inside of the groove TR2. This STI structure ST2 has a rectangular frame shape in a plan view as shown in FIGS. 2 and 3.

^{An n +} drain region DR is arranged on the main surface MS of the semiconductor substrate SB surrounded by the STI structure ST2. This n ⁺ drain region DR is arranged on the main surface MS in the n-type drift region WR3 and is in contact with the n-type drift region WR3. The n ⁺ drain region DR has an n-type impurity concentration higher than that of the n-type drift region WR3.

A p-type body region WR4 is arranged on the main surface MS of the semiconductor substrate SB. The p-type body region WR4 is located directly above the p-type well region WR2. The p-type body region WR4 is surrounded by the p-type epitaxial region EP and is in contact with the p-type epitaxial region EP.

^{As shown in FIG. 4, a p +} back gate region BGR is formed on the main surface MS of the semiconductor substrate SB so as to be surrounded by the p-type body region WR4. The p ⁺ backgate region BGR has a higher p-type impurity concentration than the p-type body region WR4.

In the cross section shown in FIG. 4, on the main surface MS of the semiconductor substrate SB, the n ⁺ drain region DRA (first portion) and the n ⁺ drain region DRB (second portion) are spaced apart from each other in the channel length direction of the MOS transistor TR. They are arranged side by side with a gap. Between the n ⁺ drain region DRA and the n ⁺ drain region DRB, each of the p ⁺ back gate region BGR and the p-type body region WR4 is sandwiched.

^{As shown in FIG. 5, an n +} source region SR is formed on the main surface MS of the semiconductor substrate SB so as to be surrounded by the p-type body region WR4. The n ⁺ source region SR constitutes a pn junction with the p-type body region WR4.

In the cross section shown in FIG. 5, each of the n ⁺ source region SR and the p-type body region WR4 is ^{sandwiched between the n +} drain region DRA and the n ⁺ drain region DRB. As shown in FIGS. 2 and 3, the ^{n + source region SR is adjacent to the p +} back gate region BGR in the channel width direction of the MOS transistor TR. The n ⁺ source region SR and the p ⁺ backgate region BGR form a pn junction.

As shown in FIG. 5, the n ⁺ source region SR has a first region SRA and a second region SRB. The second region SRB is located closer to the ^{n + drain region DRB than the first region SRA.} The first region SRA and the second region SRB have the same n-type impurity concentration distribution with each other.

The STI structure ST1 is arranged on the main surface MS of the semiconductor substrate SB between the first region SRA and the second region SRB. This STI structure ST1 has a recess TR1 and an embedded insulating layer BI1 (insulating layer).

The recess TR1 is formed on the main surface MS of the semiconductor substrate SB between the first region SRA and the second region SRB. The recess TR1 extends from the main surface MS to a position deeper than each of the first region SRA and the second region SRB. Therefore, the bottom of the recess TR1 extends deeper than the pn junction between each of the first region SRA and the second region SRB and the p-type body region WR4, and is located in the p-type body region WR4. .. The recess TR1 may have the same depth as the groove TR2 of the STI structure ST2. Further, the recess TR1 may extend to a position deeper than the p-type body region WR4.

The embedded insulating layer BI1 fills the entire inside of the recess TR1. Therefore, the embedded insulating layer BI1 extends from the main surface MS to a position deeper than each of the first region SRA and the second region SRB. The embedded insulating layer BI1 may have the same depth as the embedded insulating layer BI2 of the STI structure ST2. Further, the embedded insulating layer BI1 may extend to a position deeper than the p-type body region WR4. The upper surface of the embedded insulating layer BI1 may protrude above the main surface MS of the semiconductor substrate SB.

As shown in FIGS. 2 and 3, each of the recesses TR1 and the buried insulating layer BI1 is located in n ⁺ source region SR, reaches the n ⁺ source region SR to p ⁺ back gate region BGR .. Specifically, in each of the recess TR1 and the embedded insulating layer BI1, ^{the n-type impurity concentration in the n +} source region SR and the p-type impurity concentration in the p ⁺ backgate region BGR are the same in the main surface MS of the semiconductor substrate SB. Or extends to a position inside the ^{p +} backgate region BGR from that position.

Each of the recess TR1 and the embedded insulating layer BI1 has a rectangular shape in a plan view. One back gate region BGR is in contact with one of the pair of wall surfaces facing each other in the channel width direction among the wall surfaces constituting the recess TR1, and the other back gate region BGR is on the other of the pair of wall surfaces. Is in contact.

As shown in FIG. 5, ^{the first region SRA is in contact with the side wall of the recess TR1 on the n +} drain region DRA side (one of a pair of wall surfaces facing each other in the channel length direction). Further, the second region SRB is in contact with the side wall surface of the recess TR1 on the n ⁺ drain region DRB side (the other side of the pair of wall surfaces facing each other in the channel length direction).

As shown in FIGS. 4 and 5, a gate electrode layer GE (GEA, GEB, GEC: FIG. 2) is arranged on the main surface MS of the semiconductor substrate SB with the gate insulating layer GI interposed therebetween.

As shown in FIG. 5, the gate electrode layer GEA has a gate insulating layer GI interposed in each of the p-type body region WR4 and the p-type epitaxial region EP sandwiched between ^{the n + drain region DRA and the first region SRA.} They are facing each other. Further, as shown in FIG. 4, the gate electrode layer GEA has a gate insulating layer GI in each of the p-type body region WR4 and the p-type epitaxial region EP sandwiched between ^{the n +} drain region DRA and the p ^{+ back gate region BGR.} Are facing each other.

As shown in FIG. 5, the gate electrode layer GEB has a gate insulating layer GI interposed in each of the p-type body region WR4 and the p-type epitaxial region EP sandwiched between ^{the n + drain region DRB and the second region SRB.} They are facing each other. Further, as shown in FIG. 4, the gate electrode layer GEB has a gate insulating layer GI in each of the p-type body region WR4 and the p-type epitaxial region EP sandwiched between ^{the n +} drain region DRB and the p ^{+ back gate region BGR.} Are facing each other.

A side wall insulating layer SW is arranged on the side surface of the gate electrode layer GE. An interlayer insulating layer II is arranged on the main surface MS of the semiconductor substrate SB so as to cover the gate electrode layer GE. A plurality of contact holes CH1, CH2, and CH3 are arranged in the interlayer insulating layer II.

^{The contact hole CH1 (FIG. 5) reaches the n +} source region SR from the upper surface of the interlayer insulating layer II. ^{The contact hole CH2 (FIG. 4) reaches the p +} backgate region BGR from the upper surface of the interlayer insulating layer II. ^{The contact hole CH3 reaches the n +} drain region DR from the upper surface of the interlayer insulating layer II.

The insides of the plurality of contact holes CH1, CH2, and CH3 are embedded by the plug conductive layers PL1, PL2, and PL3, respectively.

Wiring layers IC1 and IC2 are arranged on the upper surface of the interlayer insulating layer II. The wiring layer IC1 is electrically connected to each of ^{the n +} source region SR and the p ⁺ backgate region BGR via each of the contact holes CH1 and CH2. The wiring layer IC2 is electrically connected to the ^{n + drain region DR via the contact hole CH3.}

Next, the method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 4 to 10.
As shown in FIG. 6, an n-type embedded region BL is formed on the substrate region SBR. A p-type epitaxial region EP is formed on the n-type embedded region BL. A p-type well region WR1, a p-type well region WR2, an n-type drift region WR3, and a p-type body region WR4 are formed inside the p-type epitaxial region EP.

As shown in FIG. 7, the STI structures ST1 and ST2 are formed on the main surface MS of the semiconductor substrate SB. Specifically, first, recesses TR1 and grooves TR2 are formed on the main surface of the semiconductor substrate SB by ordinary photoengraving techniques and etching techniques. Each of the recess TR1 and the groove TR2 may be formed by the same photoengraving technique and etching technique, or may be formed by different photoengraving techniques and etching techniques. After that, the embedded insulating layer BI2 is formed so as to embed each of the recess TR1 and the groove TR2.

As shown in FIG. 8, the main surface MS of the semiconductor substrate SB is, for example, thermally oxidized. As a result, the gate insulating layer GI is formed on the main surface MS of the semiconductor substrate SB. A conductive layer CL to be a gate electrode layer is formed on the gate insulating layer GI. The conductive layer CL is formed from, for example, doped polysilicon. After that, the conductive layer CL is patterned by ordinary photoengraving techniques and etching techniques.

As shown in FIG. 9, the gate electrode layer GE is formed from the conductive layer CL by the above patterning. The gate electrode layer GE is formed so as to partially ride on the STI structure ST2. After this, the side wall insulating layer SW is formed on the side wall of the gate electrode layer GE.

As shown in FIG. 10, an n-type impurity is ion-implanted into the main surface MS of the semiconductor substrate SB to form an n ⁺ drain region DR and an n ⁺ source region SR. ^{Further, a p +} backgate region BGR (not shown) is formed by ion-implanting a p-type impurity into the main surface MS of the semiconductor substrate SB. p ⁺ back gate region BGR may be formed after the formation of the n ⁺ drain region DR and the n ⁺ source region SR, or may be formed before the formation of the n ⁺ drain region DR and the n ⁺ source region SR.

As shown in FIGS. 4 and 5, the interlayer insulating layer II is formed on the main surface MS of the semiconductor substrate SB. After that, contact holes CH1, CH2, and CH3 are formed in the interlayer insulating layer II by ordinary photoengraving techniques and etching techniques. The plug conductive layers PL1, PL2, and PL3 are embedded in the contact holes CH1, CH2, and CH3, respectively.

After that, a conductive layer is formed on the upper surface of the interlayer insulating layer II, and the conductive layer is patterned by ordinary photoengraving techniques and etching techniques. As a result, the wiring layers IC1 and IC2 are formed from the conductive layer. The wiring layer IC1 is ^{electrically connected to the n +} source region SR via the plug conductive layer PL1 and is electrically connected to the p ⁺ backgate region BGR via the plug conductive layer PL2. It is formed. Further, the wiring layer IC2 is formed so as to be electrically connected to the ^{n + drain region DR via the plug conductive layer PL3.}

As described above, the semiconductor device of the present embodiment is manufactured.
Next, the effects of the semiconductor device of this embodiment will be described in comparison with the comparative examples shown in FIGS. 11 and 12.

As shown in FIGS. 11 and 12, the semiconductor device of the comparative example is different from the semiconductor device of the present embodiment in that it does not have a recess in the ^{n + source region SR.} Since the configurations of the comparative examples other than the above are substantially the same as the configurations of the present embodiment described above, the same elements are designated by the same reference numerals and the description thereof will not be repeated.

The present inventor investigated the Id-Vd waveform, the current density distribution, and the potential distribution with respect to the configuration of the present embodiment and the configuration of the comparative example. These were investigated by TCAD (Technology Computer-Aided Design) simulation. The results of the Id-Vd waveform obtained as described above are shown in FIG. 13, the result of the current density distribution is shown in FIG. 14, and the result of the potential distribution is shown in FIG.

As shown in FIG. 13, when the values of Vd are the same, it can be seen that the value of Id of the present embodiment shown by the solid line is lower than the value of Id of the comparative example shown by the broken line. ..

Further, FIG. 14 (A) shows the current density distribution of the comparative example, and FIG. 14 (B) shows the current density distribution of the present embodiment. As shown in FIGS. 14A and 14B, in the present embodiment, the STI structure ST1 is arranged in the source region SR, so that the current density is lower than that in the comparative example directly under the source region SR. You can see that it is.

Further, FIG. 15 (A) shows the potential distribution of the comparative example, and FIG. 15 (B) shows the potential distribution of the present embodiment. As shown in FIGS. 15A and 15B, in the present embodiment, by arranging the STI structure ST1 in the source region SR, the potential is lower than that in the comparative example directly under the source region SR. You can see that.

From the result of FIG. 14, in the present embodiment, since the ^{STI structure ST1 is arranged in the n +} source region SR, it is difficult for the hall current to flow in the vicinity of the STI structure ST1. As a result, as shown in FIG. 15, the rise of the potential of the p-type body region WR4 in the vicinity of the STI structure ST1 at the lower end of the ^{n + source region SR is suppressed.} Due to this effect of suppressing the potential increase, as shown in FIG. 15, the potential increase of the entire lower part ^{of the n + source region SR is also suppressed.} Due to this series of effects, as shown in FIG. 13, the on-voltage withstand voltage can be improved in the present embodiment as compared with the comparative example. The TCAD simulation was performed by setting the depth of the STI structure ST1 in the present embodiment to ^{twice the depth of the n +} drain region DR.

As described above, in the present embodiment, as shown in FIG. 16, the recess TR1 of the STI structure ST1 and the embedded insulating layer BI1 are located between the first region SRA and the second region SRB ^{of the n + source region SR.} Is provided. Therefore, for example, as shown by the broken line in the figure, ^{the Hall current that passes from the n +} drain region DRB to the lower side of the second region SRB and enters the first region SRA can be cut off by the STI structure ST1. .. By providing the STI structure ST1 in this way, it is possible to reduce the path through which the Hall current enters the source region SR. This makes it possible to improve the on-voltage BV _ON.

Further, in the present embodiment, as shown in FIGS. 2 and 3, each of the recess TR1 and the embedded insulating layer BI1 has ^{two p +} backgate regions BGR ^{that sandwich the n +} source region SR in the channel width direction. Each has been reached. As a result, the n ⁺ source region SR can be separated from each other into the first region SRA and the second region SRB. Therefore, the path of the Hall current to the first region SRA and the second region SRB can be further reduced by the STI structure ST1.

Further, in the present embodiment, as shown in FIGS. 4 and 5, the entire inside of the recess TR1 is embedded by the embedded insulating layer BI1. Therefore, the STI structure ST1 can be easily manufactured, and the size of the STI structure ST1 can be reduced.

Further, in the present embodiment, as shown in FIGS. 2 and 3, a plurality of p ⁺ back gate regions BGR and a plurality of n ⁺ source regions SR are arranged so as to be alternately arranged. This makes it possible to fix the potential of the p-type body region WR4 in a plurality of p ^{+ backgate region BGRs.}

(Embodiment 2)
As shown in FIG. 17, the configuration of the semiconductor device of the present embodiment is different from the configuration of the first embodiment in that a conductive layer having a source potential is inserted in the recess TR1 of the STI structure ST1. It's different.

In the present embodiment, the embedded insulating layer BI1 is arranged in the recess TR1 of the STI structure ST1. On the upper surface of the embedded insulating layer BI1, a hole TRE extending into the recess TR1 is arranged. The bottom of the hole TRE is located inside the embedded insulating layer BI1, and the embedded insulating layer BI1 remains between the bottom of the hole TRE and the bottom of the recess TR1.

The embedded conductive layer BC is arranged so as to embed the hole TRE. As a result, a part of the embedded conductive layer BC is arranged in the recess TR1. An embedded insulating layer BI1 is arranged between the embedded conductive layer BC and the wall surface of the recess TR1. The embedded conductive layer BC is made of, for example, doped polysilicon.

The embedded conductive layer BC projects upward from the upper surface of the embedded insulating layer BI1. The side wall insulating layer SW2 is arranged on the side wall of the portion of the embedded conductive layer BC that is above the upper surface of the embedded insulating layer BI1. In the interlayer insulating layer II, a contact hole CH4 that reaches the embedded conductive layer BC from the upper surface of the interlayer insulating layer II is arranged.

A plug conductive layer PL4 is embedded in the contact hole CH4. The wiring layer IC1 is electrically connected to the embedded conductive layer BC via the plug conductive layer PL4. As a result, the embedded conductive layer BC has the ^{same potential as the n +} source region SR and the p ⁺ back gate region BGR.

Since the configuration of the present embodiment other than the above is almost the same as the configuration of the first embodiment, the same elements as those of the first embodiment are designated by the same reference numerals in the second embodiment, and the description thereof will be described. Do not repeat.

Next, the method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 18 to 20.

The method for manufacturing the semiconductor device of the present embodiment first goes through the steps shown in FIGS. 6 and 7. After that, as shown in FIG. 18, a hole TRE is formed on the upper surface of the embedded insulating layer BI1 by ordinary photoengraving techniques and etching techniques. After that, the main surface MS of the semiconductor substrate SB is thermally oxidized, for example, to form a gate insulating layer GI on the main surface MS of the semiconductor substrate SB. A conductive layer CL to be a gate electrode layer is formed so as to embed the hole TRE and to be located on the gate insulating layer GI. The conductive layer CL is formed from, for example, doped polysilicon. After that, the conductive layer CL is patterned by ordinary photoengraving techniques and etching techniques.

As shown in FIG. 19, the gate electrode layer GE and the embedded conductive layer BC are formed from the conductive layer CL by the above patterning. The gate electrode layer GE is formed so as to partially ride on the STI structure ST2. The embedded conductive layer BC is formed so as to embed the hole TRE and to protrude upward from the hole TRE. After that, the side wall insulating layer SW is formed on the side wall of the gate electrode layer GE, and the side wall insulating layer SW2 is formed on the side wall of the embedded conductive layer BC.

As shown in FIG. 20, an n-type impurity is ion-implanted into the main surface MS of the semiconductor substrate SB to form an n ⁺ drain region DR and an n ⁺ source region SR. ^{Further, a p +} backgate region BGR (not shown) is formed by ion-implanting a p-type impurity into the main surface MS of the semiconductor substrate SB. p ⁺ back gate region BGR may be formed after the formation of the n ⁺ drain region DR and the n ⁺ source region SR, or may be formed before the formation of the n ⁺ drain region DR and the n ⁺ source region SR.

As shown in FIG. 17, the interlayer insulating layer II is formed on the main surface MS of the semiconductor substrate SB. After that, contact holes CH1, CH2, CH3, and CH4 are formed in the interlayer insulating layer II by ordinary photoengraving techniques and etching techniques. The plug conductive layers PL1, PL2, PL3, and PL4 are embedded in each of the contact holes CH1, CH2, CH3, and CH4.

After that, a conductive layer is formed on the upper surface of the interlayer insulating layer II, and the conductive layer is patterned by ordinary photoengraving techniques and etching techniques. As a result, the wiring layers IC1 and IC2 are formed from the conductive layer. The wiring layer IC1 is ^{electrically connected to the n +} source region SR via the plug conductive layer PL1 and is electrically connected to the p ⁺ backgate region BGR via the plug conductive layer PL2. Moreover, it is formed so as to be electrically connected to the embedded conductive layer BC via the plug conductive layer PL4. Further, the wiring layer IC2 is formed so as to be electrically connected to the ^{n + drain region DR via the plug conductive layer PL3.}

As described above, the semiconductor device of the present embodiment is manufactured.
Next, the effects of the semiconductor device of this embodiment will be described in comparison with the first embodiment shown in FIGS. 2 to 5.

The present inventor investigated the current density distribution and the potential distribution of the configuration of the present embodiment and the configuration of the first embodiment. The results of the current density distribution obtained as described above are shown in FIG. 21, and the results of the potential distribution are shown in FIG. 22.

FIG. 21 (A) shows the current density distribution of the first embodiment, and FIG. 21 (B) shows the current density distribution of the present embodiment. As shown in FIGS. 21 (A) and 21 (B), in the present embodiment, by arranging the embedded conductive layer BC in the recess TR1, the current is higher than that in the first embodiment directly under the source region SR. It can be seen that the density is low.

Further, FIG. 22 (A) shows the potential distribution of the first embodiment, and FIG. 22 (B) shows the potential distribution of the present embodiment. As shown in FIGS. 22 (A) and 22 (B), in the present embodiment, by arranging the embedded conductive layer BC in the recess TR1, the potential is higher than that of the first embodiment directly under the source region SR. Can be seen to be low.

From the results of FIG. 21, in the present embodiment, since the embedded conductive layer BC is arranged in the recess TR1, the hall current is more difficult to flow in the vicinity of the STI structure ST1. As a result, as shown in FIG. 22, the rise of the potential of the p-type body region WR4 in the vicinity of the STI structure ST1 at the lower end of the ^{n + source region SR is further suppressed.} Due to this effect of suppressing the potential increase, as shown in FIG. 22, the potential increase of the entire lower part ^{of the n + source region SR is also further suppressed.} Due to this series of effects, the on-voltage BV _ON can be improved in the present embodiment as compared with the first embodiment.

(Embodiment 3)
As shown in FIG. 23, in the configuration of the semiconductor device of the present embodiment, the STI structure ST1 (recess TR1, embedded insulating layer BI1) has a plurality of n ⁺ source regions SR as compared with the configuration of the first embodiment. And they differ in that they traverse multiple p ⁺ backgate regions BGR in the channel width direction.

The dimension of the STI structure ST1 (recess TR1, embedded insulating layer BI1) in the channel width direction ^{is smaller than, for example, the dimension of n +} drain region DR in the channel width direction. In this case, both ends of the STI structure ST1 (recess TR1, embedded insulating layer BI1) in the channel width direction are the outermost n ⁺ source region SRs (hereinafter, hereinafter, ^{among a plurality of n + source region SRs arranged in the channel width direction).} It may reach within the outermost source area SR). As a result, the STI structure ST1 (recess TR1) divides all of the ^{plurality of n + source regions SR arranged in the channel width direction.}

^{In this configuration, as shown in FIG. 5, the n +} source region SR is divided into two by the STI structure ST1 (recess TR1, embedded insulating layer BI1). ^{Further, as shown in FIG. 24, the p +} back gate region BGR is also divided into two by the STI structure ST1 (recess TR1, embedded insulating layer BI1).

Since the configuration of the present embodiment other than the above is almost the same as the configuration of the first embodiment, the same elements as those of the first embodiment are designated by the same reference numerals in the second embodiment, and the description thereof will be described. Do not repeat.

Further, as shown in FIG. 25, the dimensions of the STI structure ST1 (recess TR1, embedded insulating layer BI1) in the channel width direction ^{may be the same as the dimensions of the n +} drain region DR in the channel width direction. In this case, the end of the STI structure ST1 (recess TR1, embedded insulating layer BI1) in the channel width direction is p ⁺ back gate region BGR (hereinafter, the end back) located further outside the end source region SR. It may reach within the gate area).

Further, as shown in FIG. 26, the dimension of the STI structure ST1 (recess TR1, embedded insulating layer BI1) in the channel width direction ^{may be larger than the dimension of the n +} drain region DR in the channel width direction. In this case, the end portion of the STI structure ST1 (recess TR1, embedded insulating layer BI1) in the channel width direction may reach the outermost end in the channel width direction of the outermost end back gate region BGR.

According to the configurations shown in FIGS. 23, 25 and 26, it is not necessary to divide the STI structure ST1 (recessed TR1) into a plurality of pieces in the channel width direction, so that the layout and process are different from those of the first embodiment. It will be easy.

Further, by adopting the configuration of FIG. 23, the STI structure ST1 can be formed in all of the ^{plurality of n + source region SRs arranged in the channel width direction.} Thus, in all of the plurality of n ⁺ source regions SR arranged in the channel width direction, since the hole current as described with reference to FIG. 16, it is possible to reduce the route to enter the source region SR, improve the on-state breakdown voltage BV _ON It becomes possible.

Further, by adopting the configuration of FIG. 25, the STI structure ST1 can be arranged in the entire current path between the drain and the source.

Further, by adopting the configuration of FIG. 26, the influence of layout and process variations on the region where the current flows between the drain and the source is eliminated, so that the STI structure ST1 can be surely arranged in the hall current path. can.

From the configurations of FIGS. 23 to 26, the end portion of the STI structure ST1 (recess TR1) in the channel width direction is the outermost portion of the STI structure ST1 (recess TR1) in the channel width direction from the inside of the endmost source region SR. It suffices to be located in the area up to the edge.

Further, the cross section along the VV line of FIG. 23 may have the configuration shown in FIG. 17, and the cross section along the XXIV-XXIV line of FIG. 23 may have the configuration shown in FIG. 27.

As shown in FIGS. 17 and 27, the source potential embedded conductive layer BC is inserted into the recess TR1 of the STI structure ST1. The embedded conductive layer BC ^{traverses a plurality of n +} source region SRs and a plurality of p ⁺ backgate regions BGR in the channel width direction in FIG. 23.

Further, the contact hole CH4 (plug conductive layer PL4) that electrically connects the wiring layer IC1 and the embedded conductive layer BC shown in FIGS. 17 and 27 also has a plurality of n ⁺ source regions SR and a plurality of p ^{+ in FIG. 23.} It traverses the backgate region BGR in the channel width direction.

Since the configuration of FIG. 27 other than the above is almost the same as the configuration of FIG. 24, the same reference numerals are given to the same elements as those shown in FIG. 24 in FIG. 27, and the description thereof will not be repeated.

(Modification example)
As shown in FIG. 28, the contact hole CH5 may penetrate the interlayer insulating layer II and extend into the embedded insulating layer BI1, and the contact hole CH5 may be filled with the plug conductive layer PL5. As a result, the plug conductive layer PL5 extends into the recess TR1. ^{The plug conductive layer PL5 has the same potential as the n +} source region SR and the p ⁺ back gate region BGR by being electrically connected to the wiring layer IC1.

Since the configuration of FIG. 28 other than the above is almost the same as the configuration of FIG. 5, the same reference numerals are given to the same elements as those shown in FIG. 5 in FIG. 28, and the description thereof will not be repeated.

Further, the manufacturing method having the configuration of FIG. 28 goes through the same steps as those of the first embodiment shown in FIGS. 6 to 10. After that, as shown in FIG. 28, the interlayer insulating layer II is formed on the main surface MS of the semiconductor substrate SB. After that, contact holes CH1, CH2, CH3, and CH5 are simultaneously formed in the interlayer insulating layer II by ordinary photoengraving techniques and etching techniques.

The embedded insulating layer BI1 of the STI structure ST1 is etched by the overetching at the time of forming the contact hole CH5. As a result, the contact hole CH5 is formed so as to extend inside the recess TR1.

After that, the plug conductive layers PL1, PL2, PL3, and PL5 are embedded in the contact holes CH1, CH2, CH3, and CH5, respectively.

After that, a conductive layer is formed on the upper surface of the interlayer insulating layer II, and the conductive layer is patterned by ordinary photoengraving techniques and etching techniques. As a result, the wiring layers IC1 and IC2 are formed from the conductive layer. The wiring layer IC1 is ^{electrically connected to the n +} source region SR via the plug conductive layer PL1 and is electrically connected to the p ⁺ backgate region BGR via the plug conductive layer PL2. Moreover, it is formed so as to be electrically connected to the plug conductive layer PL5. Further, the wiring layer IC2 is formed so as to be electrically connected to the ^{n + drain region DR via the plug conductive layer PL3.}

As described above, the semiconductor device shown in FIG. 28 is manufactured.
According to the semiconductor device shown in FIG. 28, the source potential plug conductive layer PL5 can be formed in the recess TR1 by a simple manufacturing process.

The contact hole CH5 and the plug conductive layer PL5 may be provided separately for each of a ^{plurality of n + source regions SR arranged in the channel width direction.} Further, the contact hole CH5 and the plug conductive layer PL5 may be provided so as to cross a ^{plurality of n + source regions SR arranged in the channel width direction.}

Note that, in FIGS. 2 and 3, the ^{configuration in which the STI structure ST1 reaches the p +} backgate region BGR in a plan view has been described, but as shown in FIG. 29, the STI structure ST1 is located only in the ^{n + source region SR.} It is arranged and does not have to reach the ^{p + backgate region BGR in plan view.} In this case, in the main surface MS of the semiconductor substrate SB, the entire circumference of the STI structure ST1 ^{is surrounded by the n + source region SR, and the n +} source region SR is between the STI structure ST1 and the p ⁺ backgate region BGR. positioned.

Although the n-channel MOS transistor has been described in the above embodiment, the STI structure ST1 can be similarly applied to the p-channel MOS transistor. Specifically, ^{even if a structure similar to the STI structure ST1 is formed in the p +} source region, the same effect as that of the embodiment can be obtained.

Further, although the MOS transistor has been described in the above embodiment, the STI structure ST1 may be formed in the emitter region of the IGBT (Insulated Gate Bipolar Transistor). ^{Specifically, in the IGBT, the n +} drain region DR in FIGS. 4, 5, 17, 24, 27 and 28 is ^{replaced with the p +} collector region, and the n ⁺ source region SR is n ⁺ emitter. Replaced by an area.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the above embodiment and can be variously modified without departing from the gist thereof. Needless to say.

ANC analog circuit, BC embedded conductive layer, BGR backgate region, BI1, BI2 embedded insulating layer, BLn type embedded region, CH1, CH2, CH3, CH4, CH5 contact hole, CL conductive layer, DR, DRA, DRB, DRC n ⁺ drain region, DRC driver circuit, EP p-type epitaxial region, GE, GEA, GEB, GEC gate electrode layer, GI gate insulation layer, IC1, IC2 wiring layer, II interlayer insulation layer, IOC input / output circuit, LOC logic circuit , MS main surface, PC power supply circuit, PDC pre-driver circuit, PL1, PL2, PL3, PL4, PL5 plug conductive layer, PWC power supply circuit, SB semiconductor substrate, SBR substrate region, SR n ⁺ source region, SRA 1st region, SRB 2nd region, ST1, ST2 STI structure, SW, SW2 side wall insulation layer, TR MOS transistor, TR1 recess, TR2 groove, TRE hole, WR1, WR2 p-type well region, WR3 n-type drift region, WR4 p-type body region.

Claims (11)

A semiconductor substrate with a main surface and
An element having an insulated gate type field effect transistor section is provided.
The element is
A first impurity region on the main surface that has first and second portions aligned with each other in the channel length direction of the device and is either a drain or a collector.
At least one back gate region of the first conductive type arranged on the main surface so as to be sandwiched between the first portion and the second portion.
The main surface comprises at least one second impurity region of the second conductive type adjacent to the at least one backgate region in the channel width direction of the device and which is either a source or an emitter.
The at least one second impurity region has a first region arranged on the main surface and a second region arranged on the main surface and located closer to the second portion than the first region. Further, a semiconductor device comprising an insulating layer extending from the main surface between the first region and the second region to a position deeper than the first region and the second region. The insulating layer is arranged on the main surface so as to reach the at least one backgate region.
The semiconductor device according to claim 1, wherein the first region and the second region are separated from each other by the insulating layer. The semiconductor substrate has recesses arranged on the main surface between the first region and the second region.
The semiconductor device according to claim 1, wherein the insulating layer embeds the entire inside of the recess. The semiconductor substrate has recesses arranged on the main surface between the first region and the second region.
Further comprising an embedded conductive layer disposed inside the recess and electrically connected to the at least one second impurity region.
The semiconductor device according to claim 1, wherein the insulating layer is arranged between the wall surface of the recess and the embedded conductive layer. The semiconductor device according to claim 1, wherein the dimension of the insulating layer in the channel width direction is shorter than the dimension of the first impurity region in the channel width direction. The semiconductor device according to claim 1, wherein the dimension of the insulating layer in the channel width direction is the same as the dimension of the first impurity region in the channel width direction. The semiconductor device according to claim 1, wherein the dimension of the insulating layer in the channel width direction is longer than the dimension of the first impurity region in the channel width direction. The at least one backgate region has a plurality of backgate regions arranged in the channel width direction.
The at least one second impurity region has a plurality of second impurity regions arranged in the channel width direction.
The semiconductor device according to claim 1, wherein the plurality of back gate regions and the plurality of second impurity regions are arranged so that the back gate regions and the second impurity regions are arranged alternately. The semiconductor device according to claim 8, wherein the insulating layer crosses the plurality of second impurity regions arranged in the channel width direction. The process of forming recesses on the main surface of the semiconductor substrate and
The step of forming an insulating layer in the recess and
A step of forming an element having an insulated gate type field effect transistor portion on the main surface of the semiconductor substrate is provided.
The step of forming the element is
A step of forming a first impurity region having a first portion and a second portion aligned with each other in the channel length direction of the element on the main surface and being either a drain or a collector.
A step of forming at least one back gate region of the first conductive type arranged on the main surface so as to be sandwiched between the first portion and the second portion.
A step of forming at least one second impurity region of the second conductive type, which is adjacent to the at least one backgate region in the channel width direction of the element on the main surface and is either a source or an emitter. Including
The at least one second impurity region is formed so as to have a first region and a second region located closer to the second portion than the first region on the main surface.
A method for manufacturing a semiconductor device, wherein the first region and the second region are formed so as to sandwich the recess in which the insulating layer is embedded and to be shallower than the recess. A step of forming a conductive layer so as to be located on the main surface and in the recess.
By patterning the conductive layer, a gate electrode layer included in the element and an embedded conductive layer embedded in the recess and electrically connected to the at least one second impurity region are formed from the conductive layer. The method for manufacturing a semiconductor device according to claim 10, further comprising a step of performing.

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