CN102339857A - DMOS device and manufacturing methods thereof - Google Patents
DMOS device and manufacturing methods thereof Download PDFInfo
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- CN102339857A CN102339857A CN2010102270933A CN201010227093A CN102339857A CN 102339857 A CN102339857 A CN 102339857A CN 2010102270933 A CN2010102270933 A CN 2010102270933A CN 201010227093 A CN201010227093 A CN 201010227093A CN 102339857 A CN102339857 A CN 102339857A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000002347 injection Methods 0.000 claims abstract description 48
- 239000007924 injection Substances 0.000 claims abstract description 48
- 239000012535 impurity Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 230000003647 oxidation Effects 0.000 claims abstract description 13
- 230000000694 effects Effects 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 126
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 44
- 229910052760 oxygen Inorganic materials 0.000 claims description 44
- 239000001301 oxygen Substances 0.000 claims description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000002019 doping agent Substances 0.000 claims description 20
- 238000002513 implantation Methods 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 17
- 238000005516 engineering process Methods 0.000 claims description 15
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 229910052785 arsenic Inorganic materials 0.000 claims description 9
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 9
- 229910052698 phosphorus Inorganic materials 0.000 claims description 9
- 239000011574 phosphorus Substances 0.000 claims description 9
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- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 claims description 3
- 238000012163 sequencing technique Methods 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract 5
- 230000015556 catabolic process Effects 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 34
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000012010 growth Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention discloses a DMOS device. Lateral impurities in a drift region distribute nonuniformly and drift region impurity concentration of an active region is greater than the drift region impurity concentration under an isolated oxidation layer. The invention discloses a manufacturing method of the DMOS device. The method comprises the following steps: carrying out several times of ion implantation from high energy to low energy in an area of forming the drift region; carrying out silicon etching in the area of forming the isolated oxidation layer; forming the isolated oxidation layer and carrying out heat propulsion to the drift region. The invention discloses another manufacturing method of the DMOS device. The method comprises the following steps: carrying out first ion implantation so as to form a lightly doped drift region and the isolated oxidation layer, and then carrying out the heat propulsion to the lightly doped drift region; carrying out the second ion implantation, wherein injection energy of the second ion implantation is less than the injection energy of the first ion implantation; carrying out impurity heat propulsion. By using the device and the methods of the invention, on-resistance can be reduced; a high injection effect can be decreased; a conduction breakdown voltage can be increased; a cut-off breakdown voltage of the device can be maintained or raised.
Description
Technical field
The present invention relates to semiconductor integrated circuit and make the field, particularly relate to a kind of DMOS device, the invention still further relates to this DMOS device making method.
Background technology
High pressure DMOS is one of important devices in BCD (Bipolar-CMOS-DMOS) technology; The major criterion of its characteristic is puncture voltage (comprising off-state puncture voltage and conducting state puncture voltage) and conducting resistance, and the device optimization of DMOS mainly all is around improving puncture voltage and reducing on the conducting resistance.The raising of off-state puncture voltage and the reduction of thermoelectronic effect can be realized by the reduction of drift region doping content; The doping that raising of conducting state puncture voltage then will be through suitable increase drift region, reduce big injection effect and reach, the effective means that reduces conducting resistance is exactly the doping content that increases the drift region.Therefore on off-state puncture voltage, conducting state puncture voltage and the conducting resistance of DMOS are optimized, it is contradiction that the doping of drift region is required, and this also is the main restricting factor of conventional DMOS characteristic optimizing.
Summary of the invention
Technical problem to be solved by this invention provides a kind of DMOS device, can reduce conducting resistance, reduces big injection effect, increase the conducting puncture voltage, can also make remaining unchanged or improve by puncture voltage of device simultaneously.For this reason, the present invention also provides the manufacturing approach of DMOS device.
For solving the problems of the technologies described above, the horizontal Impurity Distribution of the drift region of DMOS device provided by the invention is inhomogeneous, and the impurity concentration of drift region that is in the DMOS device active region is greater than drift region impurity concentration under the isolating oxide layer.
More preferably select, DMOS device of the present invention comprises: the light dope drift region of one second conduction type is formed on the one first conduction type silicon substrate; The channel region of one first conduction type is formed on the said light dope drift region; The source region of one second conduction type forms on the said channel region; The drain region of one second conduction type, be formed on the said light dope drift region and with a said channel region distance at interval in the horizontal; One isolating oxide layer, be formed on the said light dope drift region and in the horizontal with said drain region adjacent and with the said channel region distance of being separated by; Be in the drift region impurity concentration of the drift region impurity concentration of said channel region and said isolation oxidation interlayer greater than said isolating oxide layer bottom; One grid is formed at said channel region top and extends laterally to said isolating oxide layer top, has covered said channel region and part drift region, and through a grid oxygen and said channel region and said part separated drift regions.
More preferably select, said isolating oxide layer is local field oxygen isolating oxide layer or shallow trench isolating oxide layer.
For solving the problems of the technologies described above, the manufacturing approach of first kind of DMOS device provided by the invention is to comprise the steps: when forming the drift region
Step 1, carry out repeatedly ion in the zone that forms said drift region and inject, the injection energy that said repeatedly ion injects reduces according to the sequencing that injects gradually.For N type DMOS, the implanted dopant that said repeatedly ion injects is phosphorus or arsenic, and the injection energy is 10KeV～1500KeV, and the implantation dosage scope is 1e11cm
-2～1e14cm
-2For P type DMOS, the implanted dopant that said repeatedly ion injects is a boron, and the injection energy is 5KeV～1000KeV, and the implantation dosage scope is 1e11cm
-2～1e14cm
-2
Step 2, carry out silicon etching in the zone that forms isolating oxide layer.Said isolating oxide layer is local field oxygen isolating oxide layer or shallow trench isolating oxide layer, and when said isolating oxide layer was local field oxygen isolating oxide layer, the thickness range of said silicon etching was 100 dusts～1000 dusts.When said isolating oxide layer was the shallow trench isolating oxide layer, said silicon etching adopted the shallow trench etching technics of shallow ditch groove separation process to form groove depth scope 1000 dusts～3000 dusts.
Step 3, form said isolating oxide layer, said drift region is picked into.When said isolating oxide layer is local field oxygen isolating oxide layer, adopts local field oxygen isolation technology promptly to adopt the method for high-temperature oxydation to form said isolating oxide layer, and can pick into said drift region simultaneously.When said isolating oxide layer is the shallow trench isolating oxide layer; The employing chemical vapor deposition method is inserted silica and is adopted CMP process to carry out forming said isolating oxide layer after the planarization in said shallow trench, more said drift region is picked into afterwards.The inventive method is passed through silicon etching; The impurity of the low-yield injection after repeatedly ion injects in said isolating oxide layer bottom silicon is removed along with silicon etching; Thereby make the impurity concentration of drift region of formation inhomogeneous in the horizontal, wherein the drift region impurity concentration of active area is greater than the drift region impurity concentration of said isolating oxide layer bottom.
For solving the problems of the technologies described above, the manufacturing approach of second kind of DMOS device provided by the invention is to comprise the steps: when forming the drift region
Step 1, carry out first time ion in the zone that forms said drift region and inject and form a light dope drift region, formation isolating oxide layer, said light dope drift region is picked into.When said isolating oxide layer is local field oxygen isolating oxide layer, adopt local field oxygen isolation technology to form said isolating oxide layer; When said isolating oxide layer is the shallow trench isolating oxide layer, adopt shallow ditch groove separation process to form said isolating oxide layer.For N type DMOS, the implanted dopant that the said first time, ion injected is phosphorus or arsenic, and the injection energy is 10KeV～1500KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2For P type DMOS, the implanted dopant that the said first time, ion injected is a boron, and the injection energy is 5KeV～1000KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2
Step 2, carry out second time ion in the zone that forms said drift region and inject, the injection energy that the said second time, ion injected is less than the injection energy of the ion injection first time; Ion injected and made the ion concentration on top, said light dope drift region of the active area that is in the DMOS device increase and form a doped drift region said second time, and the said light dope drift region that is in said isolating oxide layer below then can receive the barrier effect of said isolating oxide layer and keep concentration constant.For N type DMOS, the implanted dopant that the said second time, ion injected is phosphorus or arsenic, and the injection energy is 20KeV～200KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2For P type DMOS, the implanted dopant that the said second time, ion injected is a boron, and the injection energy is 5KeV～100KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2
Step 3, the impurity that said second time, ion injected is picked into, by said light dope drift region and said in doped drift region constitute said drift region together.Like this, the final said drift region that forms has horizontal heterogeneity, and the drift region that is in the DMOS device active region be said in the impurity concentration of doped drift region be the impurity concentration of said light dope drift region greater than drift region under the isolating oxide layer.
DMOS device of the present invention is that the light dope drift region realizes that the high-breakdown-voltage of DMOS can make remaining unchanged or improve by puncture voltage of DMOS device through drift region under the isolating oxide layer; Drift region through active area is the raising of the doping content of middle doped drift region between raceway groove and the isolating oxide layer again, can effectively improve the conducting puncture voltage of DMOS, can also reduce the conducting resistance of DMOS, the safety operation area of broadening DMOS.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1-Fig. 5 is a device architecture sketch map in each step of the embodiment of the invention one DMOS device making method;
Fig. 6-Figure 10 is a device architecture sketch map in each steps of the embodiment of the invention two DMOS device making methods.
Embodiment
As shown in Figure 5, the structural representation of embodiment of the invention DMOS device, embodiment of the invention DMOS device comprises:
The light dope drift region 102 of one second conduction type is formed on the one first conduction type silicon substrate 101.
The channel region 108 of one first conduction type is formed on the said light dope drift region 102.
The source region 109 of one second conduction type forms on the said channel region 108.
The drain region 110 of one second conduction type, be formed on the said light dope drift region 102 and with said channel region 108 distance at interval in the horizontal.
One isolating oxide layer 106, be formed on the said light dope drift region and in the horizontal with said drain region adjacent and with the said channel region distance of being separated by.Said isolating oxide layer 106 is a local field oxygen isolating oxide layer.
The impurity concentration of doped drift region 107 was the impurity concentration of light dope drift region 105 during the drift region 102 that is in 106 of said channel region 108 and said isolating oxide layers was greater than the drift region 102 of said isolating oxide layer bottom.Promptly make drift region 102 inhomogeneous in the horizontal.
One grid 111; Be formed at said channel region 108 tops and extend laterally to said isolating oxide layer 106 tops; Having covered said channel region 108 is doped drift region 107 or part light dope drift region 105 in the part with part drift region 102, and isolates through a grid oxygen 112 and said channel region 108 and said part drift region 102.
To shown in Figure 5, be device architecture sketch map in each step of the embodiment of the invention one DMOS device making method like Fig. 1.The embodiment of the invention one DMOS device making method comprises the steps:
Step 1, as shown in Figure 1; On the first conduction type silicon substrate 101, carrying out repeatedly second conductive type ion injects; The said second conduction type repeatedly injection energy of ion injection reduces according to the sequencing that injects gradually; Form light dope drift region 102 at last, wherein inject the upper position place that the low ion implanted impurity of energy is in said light dope drift region 102.For N type DMOS, the said second conduction type repeatedly implanted dopant of ion injection is phosphorus or arsenic, and the injection energy is 10KeV～1500KeV, and the implantation dosage scope is 1e11cm
-2～1e14cm
-2For P type DMOS, the said second conduction type repeatedly implanted dopant of ion injection is a boron, and the injection energy is 5KeV～1000KeV, and the implantation dosage scope is 1e11cm
-2～1e14cm
-2
Step 2, carry out silicon etching in the zone that forms isolating oxide layer.Said isolating oxide layer is a local field oxygen isolating oxide layer, and the thickness range of said silicon etching is 100 dusts～1000 dusts.Carry out silicon etching and comprise step: as shown in Figure 2, on said light dope drift region 102 from lower to upper successively the deposit hard mask layer be silica 103 and silicon nitride 104; Utilize photoetching and etching, carve the said hard mask layer that falls to form local field oxygen isolation oxidation layer region, form local field oxygen isolation oxidation layer region 105; As shown in Figure 3, utilize the protection of said hard mask layer, the silicon of etching local field oxygen isolation oxidation layer region 105 makes that injecting the low implanted dopant of energy in the said light dope drift region 102 of local field oxygen isolation oxidation layer region 105 bottoms is removed at this moment.
Step 3, form said isolating oxide layer, said light dope drift region 102 is picked into.As shown in Figure 4; Said isolating oxide layer is a local field oxygen isolating oxide layer 106; Adopt local field oxygen isolation technology promptly to adopt the method for high-temperature oxydation to form said local field oxygen isolating oxide layer 106; And can pick into said light dope drift region 102 simultaneously, this picks into and also can before or after high-temperature oxydation, carry out.After said light dope drift region 102 picks into; Active area at device has partly formed middle doped drift region 107; And what form in said local field oxygen isolating oxide layer 106 bottoms is light dope drift region 105; Finally make the impurity concentration of drift region of formation inhomogeneous in the horizontal, wherein the drift region of active area be said in the impurity concentration of doped drift region 107 be the impurity concentration of said light dope drift region 105 greater than the drift region of said local field oxygen isolating oxide layer 106 bottoms.
Step 4, as shown in Figure 5; Adopt existing conventional technology to form said DMOS device, comprise step: the ion of first conduction type injects and forms channel region 108,112 growths of grid oxygen, polysilicon gate 111 deposits and etching, source region 109 and drain region 110 injections.The said DMOS device that forms at last is a LDMOS device.
Also can to adopt be the shallow trench isolating oxide layer to isolating oxide layer in the manufacturing approach of the embodiment of the invention one; Need to adopt shallow ditch groove separation process replace corresponding local field oxygen isolation technology in the step 2, three: in the step 2 at the said hard mask layer that utilized photoetching and etching and after having formed the regional window of said shallow trench isolating oxide layer; Utilize the protection of said hard mask layer to carry out the shallow trench etching and form shallow trench, make that injecting the low implanted dopant of energy in the said light dope drift region 102 of bottom, shallow trench isolating oxide layer zone is removed at this moment; Adopt chemical vapor deposition method in said shallow trench, grow behind the pad silicon oxide film in the step 3, insert silica again and adopt CMP process to carry out the said shallow trench isolating oxide layer of formation after the planarization; Removing two-layer hard mask layer again is silica 103 and silicon nitride 104; And said light dope drift region 102 picked into; After said light dope drift region 102 picks into; Active area at device has partly formed middle doped drift region, and what form in said shallow trench isolating oxide layer bottom is light dope drift region 105.
To shown in Figure 10, be device architecture sketch map in each step of the embodiment of the invention two DMOS device making methods like Fig. 6.The embodiment of the invention two DMOS device making methods comprise the steps:
Step 1, as shown in Figure 6 is carried out the conductive type ion injection first time second and is formed a light dope drift region 202 on first conductivity type substrate 201; Form isolating oxide layer, said light dope drift region 202 is picked into.For N type DMOS, the implanted dopant that the said first time, ion injected is phosphorus or arsenic, and the injection energy is 10KeV～1500KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2For P type DMOS, the implanted dopant that the said first time, ion injected is a boron, and the injection energy is 5KeV～1000KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2Isolating oxide layer described in the present embodiment is a local field oxygen isolating oxide layer; Adopt local field oxygen isolation technology to form; Comprise step: as shown in Figure 7, on said light dope drift region 202 from lower to upper successively the deposit hard mask layer be silica 203 and silicon nitride 204; Utilize photoetching and etching, carve the said hard mask layer that falls to form local field oxygen isolation oxidation layer region, form local field oxygen isolation oxidation layer region 205; Local field oxygen isolation oxidation layer region 205 is carried out high-temperature oxydation form local field oxygen isolating oxide layer 206, as shown in Figure 8, and to remove said hard mask layer be silica 203 and silicon nitride 204.Said light dope drift region 202 is picked into and can carry out in the time of high-temperature oxydation, also can before or after high-temperature oxydation, adopt the boiler tube high-temperature annealing process to carry out separately, said light dope drift region 202 impurity are had vertically distribute uniformly.
Step 2, as shown in Figure 9 is carried out the conductive type ion injection second time second on first conductivity type substrate 201, the injection energy that the said second time, ion injected is less than the injection energy of the ion injection first time; Ion injected and made the ion concentration on 202 tops, said light dope drift region of the active area that is in the DMOS device increase and form a doped drift region 207 said second time, and 205 of said light dope drift regions that are in said local field oxygen isolating oxide layer 206 belows can receive the barrier effect of said local field oxygen isolating oxide layer 206 and keep concentration constant.For N type DMOS, the implanted dopant that the said second time, ion injected is phosphorus or arsenic, and the injection energy is 20KeV～200KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2For P type DMOS, the implanted dopant that the said second time, ion injected is a boron, and the injection energy is 5KeV～100KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2
Step 3, as shown in Figure 9 picks into the impurity that the said second time, ion injected, and constitutes the drift region together by said light dope drift region 202,205 and said middle doped drift region 207.Like this; The final said drift region that forms has horizontal heterogeneity, and the drift region that is in the DMOS device active region be said in the impurity concentration of doped drift region 207 be the impurity concentration of said light dope drift region 205 greater than the drift region under the said local field oxygen isolating oxide layer 206.
Step 4, shown in figure 10; Adopt existing conventional technology to form said DMOS device, comprise step: the ion of first conduction type injects and forms channel region 208,212 growths of grid oxygen, polysilicon gate 211 deposits and etching, source region 209 and drain region 210 injections.The said DMOS device that forms at last is a LDMOS device.
Also can to adopt be the shallow trench isolating oxide layer to isolating oxide layer in the manufacturing approach of the embodiment of the invention two; Need to adopt shallow ditch groove separation process replace corresponding local field oxygen isolation technology in the step 1: at the said hard mask layer that utilized photoetching and etching and after having formed the regional window of said shallow trench isolating oxide layer; Utilize the protection of said hard mask layer to carry out shallow trench etching formation shallow trench; Adopt chemical vapor deposition method in said shallow trench, grow behind the pad silicon oxide film, insert silica again and adopt CMP process to carry out forming said shallow trench isolating oxide layer after the planarization, removing two-layer hard mask layer again is silica 103 and silicon nitride 104.Said light dope drift region 202 is picked into and can adopt the boiler tube high-temperature annealing process to carry out separately before or after forming at said shallow trench isolating oxide layer, said light dope drift region 202 impurity are had after picking into and vertically distribute uniformly.
As shown in Figure 5, embodiment of the invention DMOS device is that said light dope drift region 105 realizes that the high-breakdown-voltage of DMOS devices can make remaining unchanged or improve by puncture voltage of DMOS device through 106 times drift regions of said local field oxygen isolating oxide layer; Drift region through active area is the raising of the doping content of said middle doped drift region 107 between said channel region 108 and the said local field oxygen isolating oxide layer 106 again; Can effectively improve the conducting puncture voltage of DMOS; Can also reduce the conducting resistance of DMOS, the safety operation area of broadening DMOS.Main rationale is: because the zone that the drift region mainly relies on below the isolating oxide layer is that dividing potential drop is carried out in said light dope drift region 105, therefore need to adopt light dope to guarantee drain terminal high-breakdown-voltage arranged.Drift region between channel region 108 and the local field oxygen isolating oxide layer 106 is that said middle doped drift region 107 is owing to there is polysilicon gate to cover; Get the field plate effect; This zone does not have the pressure of puncture basically, can adopt intermediate concentration to mix, and can reduce conducting resistance; And can reduce big injection effect, increase the conducting puncture voltage.Table one compares for the DMOS device key property of TCAD simulation; Embodiment of the invention 40V DMOS device and said conventional 40VDMOS device difference are; The doping content of drift region in embodiment of the invention 40V DMOS device zone between raceway groove and isolating oxide layer is 2 times of doping content of the following drift region of isolating oxide layer, and said conventional 40VDMOS device drift region concentration in the horizontal is identical.Can find out that the mode of the doping of embodiment of the invention device can keep threshold voltage and saturation current constant, the off-state puncture voltage is also constant basically, but the puncture voltage of conducting state improves 10V, and conducting resistance has also reduced 15%.
More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.
Table one
Claims (9)
1. DMOS device, it is characterized in that: the horizontal Impurity Distribution of DMOS device drift region is inhomogeneous, and the impurity concentration of drift region that is in the DMOS device active region is greater than drift region impurity concentration under the isolating oxide layer.
2. DMOS device as claimed in claim 1 is characterized in that, comprising:
The light dope drift region of one second conduction type is formed on the one first conduction type silicon substrate;
The channel region of one first conduction type is formed on the said light dope drift region;
The source region of one second conduction type forms on the said channel region;
The drain region of one second conduction type, be formed on the said light dope drift region and with a said channel region distance at interval in the horizontal;
One isolating oxide layer, be formed on the said light dope drift region and in the horizontal with said drain region adjacent and with the said channel region distance of being separated by;
Be in the drift region impurity concentration of the drift region impurity concentration of said channel region and said isolation oxidation interlayer greater than said isolating oxide layer bottom;
One grid is formed at said channel region top and extends laterally to said isolating oxide layer top, has covered said channel region and part drift region, and through a grid oxygen and said channel region and said part separated drift regions.
3. according to claim 1 or claim 2 DMOS device, it is characterized in that: said isolating oxide layer is local field oxygen isolating oxide layer or shallow trench isolating oxide layer.
4. the manufacturing approach of a DMOS device as claimed in claim 1 is characterized in that: comprise the steps: when forming the drift region
Step 1, carry out repeatedly ion in the zone that forms said drift region and inject, the injection energy that said repeatedly ion injects reduces according to the sequencing that injects gradually;
Step 2, carry out silicon etching in the zone that forms isolating oxide layer;
Step 3, form said isolating oxide layer, said drift region is picked into.
5. manufacturing approach as claimed in claim 4 is characterized in that: for N type DMOS, described in the step 1 repeatedly the implanted dopant that injects of ion be phosphorus or arsenic, the injection energy is 10KeV～1500KeV, the implantation dosage scope is 1e11cm
-2～1e14cm
-2For P type DMOS, described in the step 1 repeatedly the implanted dopant that injects of ion be boron, the injection energy is 5KeV～1000KeV, the implantation dosage scope is 1e11cm
-2～1e14cm
-2
6. manufacturing approach as claimed in claim 4; It is characterized in that: said isolating oxide layer is local field oxygen isolating oxide layer or shallow trench isolating oxide layer; When said isolating oxide layer is local field oxygen isolating oxide layer; The thickness range of silicon etching described in the step 2 is 100 dusts～1000 dusts, adopts local field oxygen isolation technology to form said isolating oxide layer in the step 3, and can pick into said drift region simultaneously; When said isolating oxide layer is the shallow trench isolating oxide layer; Silicon etching described in the step 2 adopts the shallow trench etching technics of shallow ditch groove separation process to form; The employing chemical vapor deposition method is inserted silica and is adopted CMP process to carry out forming said isolating oxide layer after the planarization in the step 3 in said shallow trench, more said drift region is picked into afterwards.
7. the manufacturing approach of a DMOS device as claimed in claim 1 is characterized in that: comprise the steps: when forming the drift region
Step 1, carry out first time ion in the zone that forms said drift region and inject and form a light dope drift region, formation isolating oxide layer, said light dope drift region is picked into;
Step 2, carry out second time ion in the zone that forms said drift region and inject, the injection energy that the said second time, ion injected is less than the injection energy of the ion injection first time; Ion injected and made the ion concentration on top, said light dope drift region of the active area that is in the DMOS device increase and form a doped drift region said second time, and the said light dope drift region that is in said isolating oxide layer below then can receive the barrier effect of said isolating oxide layer and keep concentration constant;
Step 3, the impurity that said second time, ion injected is picked into, by said light dope drift region and said in doped drift region constitute said drift region together.
8. manufacturing approach as claimed in claim 7 is characterized in that: for N type DMOS, the implanted dopant of ion injection for the first time is phosphorus or arsenic described in the step 1, and the injection energy is 10KeV～1500KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2, the implanted dopant of ion injection for the second time is phosphorus or arsenic described in the step 2, and the injection energy is 20KeV～200KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2For P type DMOS, the implanted dopant of ion injection for the first time is a boron described in the step 1, and the injection energy is 5KeV～1000KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2, the implanted dopant of ion injection for the second time is a boron described in the step 2, and the injection energy is 5KeV～100KeV, and the implantation dosage scope is 1e11cm
-2～1e13cm
-2
9. manufacturing approach as claimed in claim 7; It is characterized in that: isolating oxide layer described in the step 1 is local field oxygen isolating oxide layer or shallow trench isolating oxide layer; When said isolating oxide layer is local field oxygen isolating oxide layer, adopt local field oxygen isolation technology to form said isolating oxide layer; When said isolating oxide layer is the shallow trench isolating oxide layer, adopt shallow ditch groove separation process to form said isolating oxide layer.
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| CN105206658A (en) * | 2015-08-28 | 2015-12-30 | 电子科技大学 | Junction terminal structure of lateral high-voltage power device |
| CN113745161A (en) * | 2021-09-06 | 2021-12-03 | 武汉新芯集成电路制造有限公司 | High-voltage semiconductor device and manufacturing method thereof |
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