CN108054210A - Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof - Google Patents
Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof Download PDFInfo
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- CN108054210A CN108054210A CN201711397391.5A CN201711397391A CN108054210A CN 108054210 A CN108054210 A CN 108054210A CN 201711397391 A CN201711397391 A CN 201711397391A CN 108054210 A CN108054210 A CN 108054210A
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- 238000009792 diffusion process Methods 0.000 title claims abstract description 27
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 26
- 230000002146 bilateral effect Effects 0.000 title claims abstract description 25
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 25
- 238000002360 preparation method Methods 0.000 title description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 55
- 229920005591 polysilicon Polymers 0.000 claims abstract description 55
- 238000000407 epitaxy Methods 0.000 claims abstract description 29
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000010936 titanium Substances 0.000 claims description 50
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 238000002347 injection Methods 0.000 claims description 16
- 239000007924 injection Substances 0.000 claims description 16
- 230000012010 growth Effects 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 230000002035 prolonged effect Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 1
- 150000001875 compounds Chemical class 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000034655 secondary growth Effects 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of production method of trench vertical bilateral diffusion metal oxide transistor comprises the following steps：N-type substrate is provided, N-type epitaxy layer, PXing Ti areas, first groove and second groove are sequentially formed in the N-type substrate；Polysilicon is formed on gate oxide in first and second described groove and in the PXing Ti areas；The polysilicon is heat-treated, so that the N-type impurity in the polysilicon enters the PXing Ti areas adjacent to the surface of the polysilicon, so as to form N-type source region adjacent to the surface of the polysilicon in the PXing Ti areas, and the polysilicon on the outside of the groove is oxidized to the silica being located in the N-type source region；It forms the silica and N-type source region through first and second groove both sides and extends to the contact hole in the PXing Ti areas；Form front metal layer and back metal.
Description
【Technical field】
The present invention relates to semiconductor fabrication process technical fields, particularly, are related to a kind of trench vertical double diffused metal
Oxide transistor and preparation method thereof.
【Background technology】
It is widely used in field of switch power in groove-shaped VDMOS (vertical bilateral diffusion metallic oxide transistor).Groove
Type vertical DMOS transistor is (referred to as：Groove-shaped VDMOS) it is by source ion and body ion implanting
Longitudinal diffusion range difference is formed afterwards and forms raceway groove, and is widely used in Switching Power Supply and synchronous rectification field.Compared to plane
VDMOS, groove-shaped VDMOS are due to eliminating JFET areas, so its internal resistance is very small.
However, there is the problems such as the process is more complicated, cost is higher in existing groove-shaped VDMOS, it is necessary to improve.
【The content of the invention】
One of purpose of the present invention is to provide for the above-mentioned at least one technical problem of solution a kind of groove-shaped vertical
Straight bilateral diffusion metal oxide transistor and preparation method thereof.
A kind of production method of trench vertical bilateral diffusion metal oxide transistor comprises the following steps：
N-type substrate is provided, N-type epitaxy layer, initial oxide layer and silicon nitride layer are sequentially formed in the N-type substrate；
It carries out the injection in PXing Ti areas and drives in, thus in the N-type epitaxy layer adjacent to the one side shape of the initial oxide layer
Into PXing Ti areas；
It is formed through the silicon nitride layer, the initial oxide layer and the PXing Ti areas and extends to the N-type epitaxy layer
In first groove and second groove；
The first groove inner wall and the second groove inner wall shape in the PXing Ti areas and the N-type epitaxy layer
Into gate oxide；
Remove the silicon nitride layer and initial oxide layer；
Polysilicon is formed on gate oxide in first and second described groove and in the PXing Ti areas；
The polysilicon is heat-treated so that the N-type impurity in the polysilicon is into the PXing Ti areas adjacent to institute
The surface of polysilicon is stated, so as to form N-type source region, and the groove adjacent to the surface of the polysilicon in the PXing Ti areas
The polysilicon in outside is oxidized to the silica being located in the N-type source region；
The silica, the N-type source region and the PXing Ti areas are performed etching, so as to be formed through described first
With the silica and N-type source region of second groove both sides and extending to the contact hole in the PXing Ti areas；
Front metal layer is formed on the silica, the front metal connects the p-type by the contact hole
Body area；
Back metal is formed on surface of the N-type substrate away from the N-type epitaxy layer.
In one embodiment, the initial oxide layer is grown in the N-type epitaxy layer, the initial oxidation
Layer growth temperature is in the range of 900 degrees Celsius~1100 degrees Celsius, and thickness is in the range of 0.01um~0.10um.
In one embodiment, the silicon nitride layer is grown on the initial oxide layer, the silicon nitride layer
Growth temperature is in the range of 600 degrees Celsius~1100 degrees Celsius, and thickness is in the range of 0.02um~0.20um.
In one embodiment, the injection ion in the PXing Ti areas includes boron, and the dosage of the injection is at every square li
In the range of 13 powers to every square centimeter 1 14 powers of rice 1, the energy of the injection is in the scope of 100KEV to 400KEV
It is interior；To carrying out temperature the step of driving in PXing Ti areas in the range of 1100 degrees Celsius to 1200 degrees Celsius, the time is at 50 points
Clock is in the range of 200 minutes.
In one embodiment, the gate oxide is grown on first and second described trench wall, described
Growth of gate oxide layer temperature is in the range of 900 degrees Celsius~1200 degrees Celsius, and thickness is in the range of 0.01um~0.20um.
In one embodiment, the step of removing the silicon nitride layer and initial oxide layer includes：Using wet etching
Divest the silicon nitride layer and initial oxide layer.
In one embodiment, the polysilicon is n-type doping polysilicon, and the growth temperature of the polysilicon is 500
Degree Celsius~700 degrees Celsius in the range of, thickness is in the range of 0.1um~2um.
In one embodiment, the temperature of the heat treatment is described in the range of 900 degrees Celsius~1300 degrees Celsius
Polysilicon oxidation outside groove into silica thickness 0.1um~2um in the range of.
In one embodiment, the material of the front metal includes aluminium alloy, silicon alloy or copper alloy, the back of the body
Face metal includes titanium, nickel, the composite bed of silver.
A kind of trench vertical bilateral diffusion metal oxide transistor including N-type substrate, is formed at the N-type substrate
On N-type epitaxy layer, the N-type source that is formed at the PXing Ti areas on the N-type epitaxy layer surface, is formed at the p-type body surface
Area through the N-type source region and the PXing Ti areas and extends to the first groove and second groove, shape in the N-type epitaxy layer
The gate oxide of first groove described in Cheng Yu and second groove inner wall, on the gate oxide in first and second described groove
Polysilicon, be formed on the gate oxide and polysilicon of the N-type source region and first and second groove silica,
Through the silica, the N-type source region and extend to the contact hole in the PXing Ti areas, be arranged on the silica
And the front metal in the PXing Ti areas is connected by the contact hole and is arranged at the N-type substrate away from the N-type extension
The back metal on the surface of layer.
Compared to the prior art, trench vertical bilateral diffusion metal oxide transistor of the present invention and preparation method thereof includes
Advantages below：<1>The dry etch step of polysilicon is eliminated, reduces cost, is also avoided because etching polysilicon process
The many disadvantages brought；<2>As soon as using the polysilicon of secondary growth, polysilicon gate and N-type source region are formed simultaneously, greatly
Simplify technological process；<3>Using the heat treatment of polysilicon, silica is formd, before may be used as subsequent growth metal layer
Dielectric layer, eliminate the growth step of dielectric layer, saved cost, simplify technological process；<4>At the heat of polysilicon
Reason forms N-type source region, eliminates photoetching, the injection of N-type source region, and the cost of existing injection is very high, and operating efficiency
Also than relatively low, and the N-type impurity in polysilicon is diffused into formation N-type source region in PXing Ti areas by the present invention using heat treatment, this can
To carry out batch jobs in boiler tube, then cost is very low, and yield is big.
【Description of the drawings】
To describe the technical solutions in the embodiments of the present invention more clearly, used in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is the flow chart of the production method of trench vertical bilateral diffusion metal oxide transistor of the present invention.
Fig. 2-Figure 10 is each step of the production method of trench vertical bilateral diffusion metal oxide transistor shown in Fig. 1
Structure diagram.
【Specific embodiment】
The technical solution in the embodiment of the present invention will be clearly and completely described below, it is clear that described implementation
Example is only the part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is common
All other embodiment that technical staff is obtained without making creative work belongs to the model that the present invention protects
It encloses.
- Figure 10 is please referred to Fig.1, Fig. 1 is the production method of trench vertical bilateral diffusion metal oxide transistor of the present invention
Flow chart, Fig. 2-Figure 10 be trench vertical bilateral diffusion metal oxide transistor shown in Fig. 1 production method each step
Structure diagram.The production method of the trench vertical bilateral diffusion metal oxide transistor comprises the following steps.
Step S1 referring to Fig. 2, providing N-type substrate, sequentially forms N-type epitaxy layer, initial oxygen in the N-type substrate
Change layer and silicon nitride layer.Wherein, the initial oxide layer is grown in the N-type epitaxy layer, the initial oxide layer life
Long temperature is in the range of 900 degrees Celsius~1100 degrees Celsius, and thickness is in the range of 0.01um~0.10um.The silicon nitride
Layer is grown on the initial oxide layer, model of the silicon nitride layer growth temperature at 600 degrees Celsius~1100 degrees Celsius
In enclosing, thickness is in the range of 0.02um~0.20um.
Step S2, referring to Fig. 3, carrying out the injection in PXing Ti areas and driving in, so as to neighbouring described in the N-type epitaxy layer
The one side of initial oxide layer forms PXing Ti areas.Wherein, the injection ion in the PXing Ti areas includes boron, and the dosage of the injection exists
In the range of every square centimeter 1 13 powers to every square centimeter 1 14 powers, the energy of the injection in 100KEV extremely
In the range of 400KEV；To carrying out scope of temperature the step of driving in PXing Ti areas at 1100 degrees Celsius to 1200 degrees Celsius
Interior, the time is in the range of 50 minutes to 200 minutes.
Step S3, referring to Fig. 4, formed through the silicon nitride layer, the initial oxide layer and the PXing Ti areas and prolonged
Extend the first groove and second groove in the N-type epitaxy layer.Wherein, the step, which may be employed, carries out photoetching and etching
(such as dry etching) forms first and second described groove.
Step S4, referring to Fig. 5, the first groove inner wall and institute in the PXing Ti areas and the N-type epitaxy layer
It states second groove inner wall and forms gate oxide.Wherein, the gate oxide grown on first and second described trench wall and
Into the growth of gate oxide layer temperature is in the range of 900 degrees Celsius~1200 degrees Celsius, and thickness is 0.01um~0.20um's
In the range of.
Step S5, referring to Fig. 6, removing the silicon nitride layer and initial oxide layer.Specifically, wet etching may be employed
Divest the silicon nitride layer and initial oxide layer.
Step S6, referring to Fig. 7, shape on gate oxide in first and second described groove and in the PXing Ti areas
Into polysilicon.The polysilicon is n-type doping polysilicon, and the growth temperature of the polysilicon is at 500 degrees Celsius~700 degrees Celsius
In the range of, thickness is in the range of 0.1um~2um.
Step S7, referring to Fig. 8, being heat-treated to the polysilicon so that the N-type impurity in the polysilicon enters
The PXing Ti areas are adjacent to the surface of the polysilicon, so as to form N-type adjacent to the surface of the polysilicon in the PXing Ti areas
Source region, and the polysilicon on the outside of the groove is oxidized to the silica being located in the N-type source region.Wherein, the heat
The temperature of processing in the range of 900 degrees Celsius~1300 degrees Celsius, polysilicon oxidation outside the groove into silica
Thickness 0.1um~2um in the range of.
Step S8, referring to Fig. 9, the silica, the N-type source region and the PXing Ti areas are performed etching, so as to
It forms the silica and N-type source region through first and second groove both sides and extends to the contact in the PXing Ti areas
Hole.
Step S9, referring to Fig. 10, forming front metal layer on the silica, the front metal passes through described
Contact hole connects the PXing Ti areas.The material of the front metal includes aluminium alloy, silicon alloy or copper alloy.
Step S10, referring to Fig. 10, forming back metal on surface of the N-type substrate away from the N-type epitaxy layer.
The back metal includes titanium, nickel, the composite bed of silver.
Further, as shown in Figure 10, the trench vertical bilateral diffusion metal oxide crystal that the production method obtains
Pipe includes N-type substrate, the N-type epitaxy layer being formed in the N-type substrate, the p-type body for being formed at the N-type epitaxy layer surface
Area, the N-type source region for being formed at the p-type body surface through the N-type source region and the PXing Ti areas and extend to the N-type
First groove in epitaxial layer with second groove, be formed at the gate oxide of the first groove and second groove inner wall, be located at
The polysilicon on gate oxide in first and second described groove is formed at the N-type source region and first and second described ditch
Silica on the gate oxide and polysilicon of slot through the silica, the N-type source region and extends to the p-type
The contact hole in body area, be arranged on the silica and by the contact hole connect the PXing Ti areas front metal and
It is arranged at the back metal on surface of the N-type substrate away from the N-type epitaxy layer.
Compared to the prior art, trench vertical bilateral diffusion metal oxide transistor of the present invention and preparation method thereof includes
Advantages below：<1>The dry etch step of polysilicon is eliminated, reduces cost, is also avoided because etching polysilicon process
The many disadvantages brought；<2>As soon as using the polysilicon of secondary growth, polysilicon gate and N-type source region are formed simultaneously, greatly
Simplify technological process；<3>Using the heat treatment of polysilicon, silica is formd, before may be used as subsequent growth metal layer
Dielectric layer, eliminate the growth step of dielectric layer, saved cost, simplify technological process；<4>At the heat of polysilicon
Reason forms N-type source region, eliminates photoetching, the injection of N-type source region, and the cost of existing injection is very high, and operating efficiency
Also than relatively low, and the N-type impurity in polysilicon is diffused into formation N-type source region in PXing Ti areas by the present invention using heat treatment, this can
To carry out batch jobs in boiler tube, then cost is very low, and yield is big.
Above-described is only embodiments of the present invention, it should be noted here that for those of ordinary skill in the art
For, without departing from the concept of the premise of the invention, improvement can also be made, but these belong to the protection model of the present invention
It encloses.
Claims (10)
1. a kind of production method of trench vertical bilateral diffusion metal oxide transistor, it is characterised in that：The production method
Comprise the following steps：
N-type substrate is provided, N-type epitaxy layer, initial oxide layer and silicon nitride layer are sequentially formed in the N-type substrate；
It carries out the injection in PXing Ti areas and drives in, so as to form P adjacent to the one side of the initial oxide layer in the N-type epitaxy layer
Xing Ti areas；
It is formed through the silicon nitride layer, the initial oxide layer and the PXing Ti areas and extended in the N-type epitaxy layer
First groove and second groove；
The first groove inner wall and the second groove inner wall in the PXing Ti areas and the N-type epitaxy layer form grid
Oxide layer；
Remove the silicon nitride layer and initial oxide layer；
Polysilicon is formed on gate oxide in first and second described groove and in the PXing Ti areas；
The polysilicon is heat-treated so that the N-type impurity in the polysilicon is into the PXing Ti areas adjacent to described more
The surface of crystal silicon, so as to form N-type source region adjacent to the surface of the polysilicon in the PXing Ti areas, and on the outside of the groove
Polysilicon be oxidized to be located at the N-type source region on silica；
The silica, the N-type source region and the PXing Ti areas are performed etching, so as to be formed through described first and
The silica and N-type source region of two groove both sides simultaneously extend to the contact hole in the PXing Ti areas；
Front metal layer is formed on the silica, the front metal connects the PXing Ti areas by the contact hole；
Back metal is formed on surface of the N-type substrate away from the N-type epitaxy layer.
2. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The initial oxide layer is grown in the N-type epitaxy layer, the initial oxidation layer growth temperature 900 degrees Celsius~
In the range of 1100 degrees Celsius, thickness is in the range of 0.01um~0.10um.
3. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The silicon nitride layer is grown on the initial oxide layer, and the silicon nitride layer growth temperature is 600 degrees Celsius~1100
In the range of degree Celsius, thickness is in the range of 0.02um~0.20um.
4. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The injection ion in the PXing Ti areas includes boron, the dosage of the injection every square centimeter 1 13 powers to every square centimeter 1
14 powers in the range of, the energy of the injection is in the range of 100KEV to 400KEV；To carrying out driving in for PXing Ti areas
The temperature of step is in the range of 1100 degrees Celsius to 1200 degrees Celsius, and the time is in the range of 50 minutes to 200 minutes.
5. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The gate oxide is grown on first and second described trench wall, and the growth of gate oxide layer temperature is Celsius 900
In the range of~1200 degrees Celsius of degree, thickness is in the range of 0.01um~0.20um.
6. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The step of removing the silicon nitride layer and initial oxide layer includes：The silicon nitride layer and initial oxidation are divested using wet etching
Layer.
7. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The polysilicon be n-type doping polysilicon, the growth temperature of the polysilicon in the range of 500 degrees Celsius~700 degrees Celsius,
Thickness is in the range of 0.1um~2um.
8. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The temperature of the heat treatment in the range of 900 degrees Celsius~1300 degrees Celsius, polysilicon oxidation outside the groove into two
In the range of thickness 0.1um~2um of silica.
9. the production method of trench vertical bilateral diffusion metal oxide transistor as described in claim 1, it is characterised in that：
The material of the front metal include aluminium alloy, silicon alloy or copper alloy, the back metal include titanium, nickel, silver it is compound
Layer.
10. a kind of trench vertical bilateral diffusion metal oxide transistor, it is characterised in that：The trench vertical double diffusion gold
Belonging to oxide transistor includes N-type substrate, the N-type epitaxy layer being formed in the N-type substrate, is formed at the N-type epitaxy layer
The PXing Ti areas on surface, the N-type source region for being formed at the p-type body surface through the N-type source region and the PXing Ti areas and are prolonged
It extends the first groove in the N-type epitaxy layer and second groove, be formed at the first groove and the grid of second groove inner wall
Oxide layer, the polysilicon on the gate oxide in first and second described groove are formed at the N-type source region and described
One and second groove gate oxide and polysilicon on silica, through the silica, the N-type source region and extend
Contact hole to the PXing Ti areas is arranged on the silica and is connecting the PXing Ti areas just by the contact hole
Face metal and the back metal for being arranged at surface of the N-type substrate away from the N-type epitaxy layer.
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