CN104835739A - Manufacturing method of power transistor and power transistor - Google Patents
Manufacturing method of power transistor and power transistor Download PDFInfo
- Publication number
- CN104835739A CN104835739A CN201410047137.2A CN201410047137A CN104835739A CN 104835739 A CN104835739 A CN 104835739A CN 201410047137 A CN201410047137 A CN 201410047137A CN 104835739 A CN104835739 A CN 104835739A
- Authority
- CN
- China
- Prior art keywords
- layer
- power transistor
- silicon nitride
- predeterminable area
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims description 39
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 32
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- -1 boron ion Chemical class 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 abstract 7
- 238000007254 oxidation reaction Methods 0.000 abstract 7
- 230000010354 integration Effects 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UIFOTCALDQIDTI-UHFFFAOYSA-N arsanylidynenickel Chemical compound [As]#[Ni] UIFOTCALDQIDTI-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention provides a manufacturing method of a power transistor and the power transistor. The manufacturing method of the power transistor comprises: growing a first oxidation layer on an upper surface of a substrate, on which an epitaxial layer is formed; injecting first doping ions to the top of the epitaxial layer to form a body layer; injecting second doping ions to the top of the body layer to form an N+ layer and to obtain a substrate structure; etching a plurality of first pre-set areas of the substrate structure to form a plurality of grooves; etching the left oxidation layer, and growing a gate oxidation layer on the substrate provided with grooves; growing a polycrystalline silicon layer on the surface of the gate oxidation layer, and growing a second oxidation layer on the surface of the polycrystalline silicon layer; removing the second oxidation layer and the polycrystalline silicon layer, beyond the plurality of second pre-set areas, away through etching on the second oxidation layer and the polycrystalline silicon layer to form a plurality of projections; and etching side walls between every two adjacent projections to form a contact hole. Through the technical scheme in the invention, the integration degree of the power transistor is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method and a kind of power transistor of power transistor.
Background technology
At present, in the manufacture process of trench VDMOS device, need to make contact hole between adjacent groove, as shown in fig. 1, the position of contact hole is between groove 1 and groove 2.In the related, the manufacture method of contact hole generally adopts photoetching, etching has been come, but there is deviation owing to aiming at during photoetching, the skew of contact hole position can be caused (as shown in Figure 2, contact hole is displaced to the position at groove 1 place), even if therefore need reserved larger distance to guarantee that contact hole offsets between two grooves, also can in normal deviation range.But larger preset space is unfavorable for the integrated level of device.
Therefore, how when guaranteeing that contact hole meets the demands, the distance between reduction groove becomes technical problem urgently to be resolved hurrily.
Summary of the invention
The present invention is just based on the problems referred to above, propose a kind of fabrication scheme of new power transistor, make when etching contact hole, only need etch along the sidewall between adjacent two projections, avoid when to contact hole photoetching, the skew of the contact hole position that the distance limit between groove causes, improves the integrated level of power transistor.
In view of this, the present invention proposes a kind of manufacture method of power transistor, comprising: grow the first oxide layer at the upper surface of the substrate being formed with epitaxial loayer, described first oxide layer is positioned at the top of described epitaxial loayer; The first Doped ions is injected at top to described epitaxial loayer, organizator region layer; The second Doped ions is injected at top to described tagma, forms N+ region layer, obtains substrat structure; Multiple first predeterminable areas on described substrat structure etch, all form a groove after etching to make each described first predeterminable area, other first predeterminable areas in described each first predeterminable area and described multiple first predeterminable area are all non-intersect; Etch away remaining described first oxide layer, and be formed with the Grown gate oxide of described groove; At the superficial growth polysilicon layer of described gate oxide, described pair of groove is filled by described polysilicon layer, and in superficial growth second oxide layer of described polysilicon layer; Described second oxide layer and described polysilicon layer etch away the second oxide layer outside multiple second predeterminable area and polysilicon layer, to form multiple projection including polysilicon layer and the second oxide layer, wherein, described first predeterminable area be in corresponding described second predeterminable area at described first predeterminable area in projection on the whole; Etch along the sidewall between two adjacent protrusion every in multiple described projection, be in over the substrate in the structure between described every two adjacent protrusion and form contact hole.
In this technical scheme, by etching away the second oxide layer outside multiple second predeterminable area and polysilicon layer in the second oxide layer and polysilicon layer, form multiple projection including polysilicon layer and the second oxide layer, make when etching contact hole, only need etch along the sidewall between every two adjacent projections, avoid when to contact hole photoetching, the skew of the contact hole position that the distance limit between groove causes, improves the integrated level of power transistor.
According to a further aspect in the invention, also proposed a kind of power transistor, described power transistor is made by the manufacture method of the power transistor described in technique scheme.
When manufacturing power transistor, by etching away the second oxide layer outside multiple second predeterminable area and polysilicon layer in the second oxide layer and polysilicon layer, form multiple projection including polysilicon layer and the second oxide layer, make when etching contact hole, only need etch along the sidewall between every two adjacent projections, avoid when to contact hole photoetching, the skew of the contact hole position that the distance limit between groove causes, improves the integrated level of power transistor.
By above technical scheme, making when etching contact hole, only need etch along the sidewall between every two adjacent projections, avoiding when to contact hole photoetching, the skew of the contact hole position that the distance limit between groove causes, improves the integrated level of power transistor.
Accompanying drawing explanation
Fig. 1 shows the normal position schematic diagram of contact hole in power transistor;
Fig. 2 shows the deviation post schematic diagram of contact hole in power transistor;
Fig. 3 shows the schematic flow diagram of the manufacture method of power transistor according to an embodiment of the invention;
Fig. 4 A to Fig. 4 M shows the manufacturing process schematic diagram of power transistor according to an embodiment of the invention.
Embodiment
In order to more clearly understand above-mentioned purpose of the present invention, feature and advantage, below in conjunction with the drawings and specific embodiments, the present invention is further described in detail.It should be noted that, when not conflicting, the feature in the embodiment of the application and embodiment can combine mutually.
Set forth a lot of detail in the following description so that fully understand the present invention; but; the present invention can also adopt other to be different from other modes described here and implement, and therefore, protection scope of the present invention is not by the restriction of following public specific embodiment.
Fig. 3 shows the schematic flow diagram of the manufacture method of power transistor according to an embodiment of the invention.As shown in Figure 3, the manufacture method of power transistor, comprising: step 302 according to an embodiment of the invention, grows the first oxide layer at the upper surface of the substrate being formed with epitaxial loayer, and described first oxide layer is positioned at the top of described epitaxial loayer; Step 304, the first Doped ions is injected at the top to described epitaxial loayer, organizator region layer; Step 306, the second Doped ions is injected at the top to described tagma, forms N+ region layer, obtains substrat structure; Step 308, multiple first predeterminable areas on described substrat structure etch, all form a groove after etching to make each described first predeterminable area, other first predeterminable areas in described each first predeterminable area and described multiple first predeterminable area are all non-intersect; Step 310, etches away remaining described first oxide layer, and is being formed with the Grown gate oxide of described groove; Step 312, at the superficial growth polysilicon layer of described gate oxide, described pair of groove is filled by described polysilicon layer, and in superficial growth second oxide layer of described polysilicon layer; Step 314, described second oxide layer and described polysilicon layer etch away the second oxide layer outside multiple second predeterminable area and polysilicon layer, to form multiple projection including polysilicon layer and the second oxide layer, wherein, described first predeterminable area be in corresponding described second predeterminable area at described first predeterminable area in projection on the whole; Step 316, etches along the sidewall between two adjacent protrusion every in multiple described projection, is in over the substrate in the structure between described every two adjacent protrusion and forms contact hole.
In this technical scheme, by etching away the second oxide layer outside multiple second predeterminable area and polysilicon layer in the second oxide layer and polysilicon layer, form multiple projection including polysilicon layer and the second oxide layer, make when etching contact hole, only need etch along the sidewall between every two adjacent projections, avoid when to contact hole photoetching, the skew of the contact hole position that the distance limit between groove causes, improves the integrated level of power transistor.
In technique scheme, preferably, each described groove is all through described tagma layer and described N+ region layer, and the bottom of described each groove is positioned at described epitaxial loayer.
In technique scheme, preferably, before the structure described substrate is between described every two adjacent protrusion is etched, also comprise: be formed with the types of flexure of described projection, grown silicon nitride layer, described silicon nitride layer is step-like, and described silicon nitride layer comprises upper table surface silicon nitride layer, sidewall silicon nitride layer and following table silicon nitride layer; Etch away described upper table surface silicon nitride layer and described following table silicon nitride layer, retain described sidewall silicon nitride layer.
In this technical scheme, by being formed with protruding types of flexure, grown silicon nitride layer, making, when etching contact hole, to etch along the position of sidewall silicon nitride layer, projection can also protected surprisingly not etched away simultaneously.
In technique scheme, preferably, the growth temperature of described silicon nitride layer is 600 degrees Celsius ~ 900 degrees Celsius, and thickness is 0.1 micron ~ 0.3 micron.
In technique scheme, preferably, when etching along the sidewall between described every two adjacent protrusion, etch described N+ region layer and described tagma layer one by one, wherein, the bottom of described contact hole is positioned at described tagma layer.
In technique scheme, preferably, described first Doped ions is boron ion, and described second Doped ions is phosphonium ion.
In this technical scheme, the boron ion dose of injection can be 1.0E14/centimetre ~ 1.0E15/centimetre, and energy can be 100KEV ~ 150KEV, and driving in temperature can be 1100 DEG C ~ 1200 DEG C, and injection length can be 50 minutes ~ 200 minutes.The phosphonium ion dosage injected can be 1.0E15/centimetre ~ 1.0E16/centimetre, and energy can be 100KEV ~ 150KEV.
In technique scheme, preferably, the step etching away the second oxide layer outside described multiple second predeterminable area and polysilicon layer described in specifically comprises: be formed with the substrate surface coating photoresist of described silicon dioxide layer; On described silicon dioxide layer, remove the photoresist outside described multiple second predeterminable area, to form photoresist window in described second oxide layer; Etch described second oxide layer of described photoresist window area and described polysilicon layer, retain described second oxide layer at described multiple second predeterminable area place and described polysilicon layer, each described second predeterminable area corresponding described projection respectively.
In technique scheme, preferably, on the lower surface of described substrate, growing metal layer, forms the drain electrode of described power transistor, at the described upper surface growing metal layer being formed with the substrate of described contact hole, forms the source electrode of described power transistor.
In this technical scheme, can be titanium, nickeline composite bed at the metal level of substrate lower surface growth, the metal level grown at the upper surface of substrate can be aluminium lamination.
In technique scheme, preferably, described etching is dry etching.
In this technical scheme, dry etching has higher selectivity, it is hereby ensured the accuracy of etching.
According to a further aspect in the invention, also proposed a kind of power transistor, described power transistor is made by the manufacture method of the power transistor described in technique scheme.
When manufacturing power transistor, by etching away the second oxide layer outside multiple second predeterminable area and polysilicon layer in the second oxide layer and polysilicon layer, form multiple projection including polysilicon layer and the second oxide layer, make when etching contact hole, only need etch along the sidewall between every two adjacent projections, avoid when to contact hole photoetching, the skew of the contact hole position that the distance limit between groove causes, improves the integrated level of power transistor.
The manufacturing process of power transistor is according to an embodiment of the invention described in detail below in conjunction with Fig. 4 A to Fig. 4 M.
Fig. 4 A to Fig. 4 M shows the manufacturing process schematic diagram of power transistor according to an embodiment of the invention.
In the present embodiment, set forth the production technology of power transistor by two grooves, it should be appreciated by those skilled in the art, for the transistor comprising multiple groove, the technical scheme of the present embodiment also can be adopted to produce.
As shown in Figure 4 A, on N-type substrate 402, grow N-type epitaxy layer 404, and grow silicon dioxide layer 406 on N-type epitaxy layer 404, the thickness of silicon dioxide layer 406 can be 0.05 micron ~ 0.15 micron, and growth temperature can be 1000 DEG C ~ 1150 DEG C.
As shown in Figure 4 B, boron ion is injected at the top of N-type epitaxy layer, to form P type tagma 408.Implantation dosage can be 1.0E14/centimetre ~ 1.0E15/centimetre, and energy can be 100KEV ~ 150KEV, and driving in temperature can be 1100 DEG C ~ 1200 DEG C, and injection length can be 50 minutes ~ 200 minutes.
As shown in Figure 4 C, inject phosphonium ion, form N+ district 410 at the top in P type tagma 408, the phosphonium ion dosage of injection can be 1.0E15/centimetre ~ 1.0E16/centimetre, and energy can be 100KEV ~ 150KEV.
As shown in Figure 4 D, photoetching, etching form groove 412 and groove 414, and groove width can be 0.1 micron ~ 0.4 micron, and the degree of depth can be 0.5 micron ~ 3.0 microns.
As shown in Figure 4 E, silicon dioxide layer 406 is etched away.
As illustrated in figure 4f, on N+ district 410 and groove 412 and groove 414, grow canopy oxide layer 416, growth temperature can be 800 DEG C ~ 1150 DEG C, and thickness can be 0.03 micron ~ 0.20 micron.
As shown in Figure 4 G, growing polycrystalline silicon layer 418 on canopy oxide layer 416, growth temperature can be 500 DEG C ~ 700 DEG C, and thickness can be 0.5 micron ~ 2.0 microns.
As shown at figure 4h, on polysilicon layer 418, grow silicon dioxide layer 420, growth temperature can be 1000 DEG C ~ 1150 DEG C, and thickness can be 0.1 micron ~ 0.5 micron.
As shown in fig. 41, silicon dioxide layer 420 and polysilicon layer 418 are etched, after etching completes, form the projection that two include polysilicon layer 418 and silicon dioxide layer 420.
As shown in fig. 4j, be formed with the types of flexure of described projection, grown silicon nitride layer 422, growth temperature can be 600 DEG C ~ 900 DEG C, thickness can be 0.1 micron ~ 0.3 micron, wherein, silicon nitride layer 422, in step-like, comprises upper table surface silicon nitride layer, sidewall silicon nitride layer 4220 and following table silicon nitride layer.
As shown in Figure 4 K, etch away upper table surface silicon nitride layer and following table silicon nitride layer, retain sidewall silicon nitride layer 4220.
As illustrated in fig. 4l, etching along sidewall silicon nitride layer 4220, form contact hole 432, when etching, need to etch away N+ district 410 and P type tagma 408 one by one, and the bottom of contact hole 432 is in P type tagma 408.
When etching contact hole 432, not needing to carry out photoetching between two grooves (412 and 414), only need etch along sidewall silicon nitride layer 4220, thus guaranteeing that contact hole 432 can not be displaced to the position of groove 412 or groove 414.
As described in Fig. 4 M, growing metal layer 424 on the lower surface of N-type substrate 402, forms the drain electrode 430 of power transistor, being formed with the upper surface growing metal layer 426 of N-type substrate 402 of contact hole 432, forms the source electrode 428 of power transistor.Wherein, can be titanium, nickeline composite bed at metal level 424, metal level 426 can be aluminium lamination.
More than be described with reference to the accompanying drawings technical scheme of the present invention, consider in the related, when manufacturing power transistor, even if need reserved larger distance to guarantee that contact hole offsets between two grooves, also can in normal deviation range, but larger preset space is unfavorable for the integrated level of device.Therefore, the present invention proposes a kind of fabrication scheme of new power transistor, make when etching contact hole, only need etch along the sidewall between two projections, avoid when to contact hole photoetching, the skew of the contact hole position that the distance limit between groove causes, improves the integrated level of power transistor.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a manufacture method for power transistor, is characterized in that, comprising:
Grow the first oxide layer at the upper surface of the substrate being formed with epitaxial loayer, described first oxide layer is positioned at the top of described epitaxial loayer;
The first Doped ions is injected at top to described epitaxial loayer, organizator region layer;
The second Doped ions is injected at top to described tagma, forms N+ region layer, obtains substrat structure;
Multiple first predeterminable areas on described substrat structure etch, all form a groove after etching to make each described first predeterminable area, other first predeterminable areas in described each first predeterminable area and described multiple first predeterminable area are all non-intersect;
Etch away remaining described first oxide layer, and be formed with the Grown gate oxide of described groove;
At the superficial growth polysilicon layer of described gate oxide, described pair of groove is filled by described polysilicon layer, and in superficial growth second oxide layer of described polysilicon layer;
Described second oxide layer and described polysilicon layer etch away the second oxide layer outside multiple second predeterminable area and polysilicon layer, to form multiple projection including polysilicon layer and the second oxide layer, wherein, described first predeterminable area be in corresponding described second predeterminable area at described first predeterminable area in projection on the whole;
Etch along the sidewall between two adjacent protrusion every in multiple described projection, be in over the substrate in the structure between described every two adjacent protrusion and form contact hole.
2. the manufacture method of power transistor according to claim 1, is characterized in that, each described groove is all through described tagma layer and described N+ region layer, and the bottom of described each groove is positioned at described epitaxial loayer.
3. the manufacture method of power transistor according to claim 1, is characterized in that, before etching the structure described substrate is between described every two adjacent protrusion, also comprises:
Be formed with the types of flexure of described projection, grown silicon nitride layer, described silicon nitride layer is step-like, and described silicon nitride layer comprises upper table surface silicon nitride layer, sidewall silicon nitride layer and following table silicon nitride layer;
Etch away described upper table surface silicon nitride layer and described following table silicon nitride layer, retain described sidewall silicon nitride layer.
4. the manufacture method of power transistor according to claim 3, is characterized in that, the growth temperature of described silicon nitride layer is 600 degrees Celsius ~ 900 degrees Celsius, and thickness is 0.1 micron ~ 0.3 micron.
5. the manufacture method of power transistor according to claim 1, is characterized in that,
When etching along the sidewall between described every two adjacent protrusion, etch described N+ region layer and described tagma layer one by one, wherein, the bottom of described contact hole is positioned at described tagma layer.
6. the manufacture method of power transistor according to claim 1, is characterized in that, described first Doped ions is boron ion, and described second Doped ions is phosphonium ion.
7. the manufacture method of power transistor according to claim 1, is characterized in that, described in etch away the second oxide layer outside described multiple second predeterminable area and polysilicon layer step specifically comprise:
Be formed with the substrate surface coating photoresist of described silicon dioxide layer;
On described silicon dioxide layer, remove the photoresist outside described multiple second predeterminable area, to form photoresist window in described second oxide layer;
Etch described second oxide layer of described photoresist window area and described polysilicon layer, retain described second oxide layer at described multiple second predeterminable area place and described polysilicon layer, the corresponding described projection of each described second predeterminable area.
8. the manufacture method of power transistor according to claim 1, it is characterized in that, growing metal layer on the lower surface of described substrate, form the drain electrode of described power transistor, at the described upper surface growing metal layer being formed with the substrate of described contact hole, form the source electrode of described power transistor.
9. the manufacture method of power transistor according to any one of claim 1 to 8, is characterized in that, described etching is dry etching.
10. a power transistor, is characterized in that, described power transistor is made by the manufacture method of power transistor as claimed in any one of claims 1-9 wherein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410047137.2A CN104835739B (en) | 2014-02-10 | 2014-02-10 | The manufacturing method and power transistor of power transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410047137.2A CN104835739B (en) | 2014-02-10 | 2014-02-10 | The manufacturing method and power transistor of power transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104835739A true CN104835739A (en) | 2015-08-12 |
| CN104835739B CN104835739B (en) | 2018-06-05 |
Family
ID=53813543
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410047137.2A Active CN104835739B (en) | 2014-02-10 | 2014-02-10 | The manufacturing method and power transistor of power transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104835739B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106340537A (en) * | 2016-11-04 | 2017-01-18 | 无锡新洁能股份有限公司 | Low-voltage trench DMOS device of high integrated level and manufacture method of device |
| CN108039372A (en) * | 2017-12-21 | 2018-05-15 | 深圳迈辽技术转移中心有限公司 | Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof |
| CN108054210A (en) * | 2017-12-21 | 2018-05-18 | 深圳市晶特智造科技有限公司 | Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof |
| CN108133894A (en) * | 2017-12-21 | 2018-06-08 | 深圳市晶特智造科技有限公司 | Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080042222A1 (en) * | 2006-08-16 | 2008-02-21 | Force Mos Technology Co., Ltd. | Trench mosfet with copper metal connections |
| CN101794734A (en) * | 2009-01-23 | 2010-08-04 | 半导体元件工业有限责任公司 | Semiconductor component and method of manufacture |
| CN102088035A (en) * | 2010-09-21 | 2011-06-08 | 上海韦尔半导体股份有限公司 | Trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and manufacturing method thereof |
| CN102983164A (en) * | 2011-09-07 | 2013-03-20 | 株式会社东芝 | Semiconductor device and method for manufacturing same |
-
2014
- 2014-02-10 CN CN201410047137.2A patent/CN104835739B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080042222A1 (en) * | 2006-08-16 | 2008-02-21 | Force Mos Technology Co., Ltd. | Trench mosfet with copper metal connections |
| CN101794734A (en) * | 2009-01-23 | 2010-08-04 | 半导体元件工业有限责任公司 | Semiconductor component and method of manufacture |
| CN102088035A (en) * | 2010-09-21 | 2011-06-08 | 上海韦尔半导体股份有限公司 | Trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and manufacturing method thereof |
| CN102983164A (en) * | 2011-09-07 | 2013-03-20 | 株式会社东芝 | Semiconductor device and method for manufacturing same |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106340537A (en) * | 2016-11-04 | 2017-01-18 | 无锡新洁能股份有限公司 | Low-voltage trench DMOS device of high integrated level and manufacture method of device |
| CN108039372A (en) * | 2017-12-21 | 2018-05-15 | 深圳迈辽技术转移中心有限公司 | Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof |
| CN108054210A (en) * | 2017-12-21 | 2018-05-18 | 深圳市晶特智造科技有限公司 | Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof |
| CN108133894A (en) * | 2017-12-21 | 2018-06-08 | 深圳市晶特智造科技有限公司 | Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof |
| CN108133894B (en) * | 2017-12-21 | 2021-02-26 | 自贡国晶科技有限公司 | Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof |
| CN108054210B (en) * | 2017-12-21 | 2021-10-26 | 深圳市晶特智造科技有限公司 | Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof |
| CN108039372B (en) * | 2017-12-21 | 2021-12-07 | 上海领矽半导体有限公司 | Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104835739B (en) | 2018-06-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5217257B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR102008744B1 (en) | Semiconductor devices and methods of manufacturing the same | |
| JP6492068B2 (en) | Vertical trench MOSFET devices in integrated power technology | |
| JP2009531850A (en) | Trench gate semiconductor device and manufacturing method thereof | |
| US8981462B2 (en) | Semiconductor device | |
| JPWO2014061367A1 (en) | Silicon carbide semiconductor device and manufacturing method thereof | |
| CN105428237A (en) | Negative metal oxide transistor (NMOS) transistor and forming method thereof | |
| JP2009200300A (en) | Semiconductor device, and method of manufacturing the same | |
| JP2011204808A (en) | Semiconductor device and method of manufacturing the same | |
| TWI544632B (en) | U-shape resurf mosfet devices and associated methods of manufacturing | |
| CN104835739A (en) | Manufacturing method of power transistor and power transistor | |
| TWI534910B (en) | Method of manufacturing semiconductor device | |
| CN111755525A (en) | Trench MOS power device and preparation method | |
| US20150187911A1 (en) | Semiconductor device and fabrication method thereof | |
| CN105575781A (en) | Manufacturing method for trench type super junction | |
| TW201826529A (en) | Semiconductor device and method of manufacturing the semiconductor device | |
| CN103000533B (en) | The manufacture method of autoregistration super junction power transistor | |
| KR100902585B1 (en) | Trench gate mosfet and method for fabricating of the same | |
| CN105448722B (en) | A kind of production method and semiconductor device of superjunction semiconductor field | |
| TWI460823B (en) | Methods for fabricating trench metal oxide semiconductor field effect transistors | |
| CN110504161A (en) | Trench-gate metal-oxide half field effect transistor and its manufacturing method | |
| KR100549579B1 (en) | Method for manufacturing cell transistor | |
| CN104838501A (en) | Semiconductor device having vertical MOSFET of super junction structure, and method for production of same | |
| CN105190897A (en) | Semiconductor device, and manufacturing method for same | |
| KR20170080510A (en) | Transistor device with field electrode |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| EXSB | Decision made by sipo to initiate substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220721 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
|
| TR01 | Transfer of patent right |