CN104900526B - The manufacturing method and VDMOS of VDMOS - Google Patents
The manufacturing method and VDMOS of VDMOS Download PDFInfo
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- CN104900526B CN104900526B CN201410083225.8A CN201410083225A CN104900526B CN 104900526 B CN104900526 B CN 104900526B CN 201410083225 A CN201410083225 A CN 201410083225A CN 104900526 B CN104900526 B CN 104900526B
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Abstract
The present invention provides a kind of manufacturing method and VDMOS of VDMOS, and method includes：Gate oxide, polysilicon layer, P bodies area are sequentially generated in N-type epitaxy layer；In P bodies area, injection N-type impurity forms N-type source region, and the N-type source region includes N source regions and N+ source regions；The N+ source regions are between the gate oxide and N source regions；Oxide layer, the areas P+, dielectric layer, contact hole and metal layer are sequentially formed on the polysilicon layer and the gate oxide, so that the metal layer is connected with every layer of side in the N source regions, N+ source regions, gate oxide, oxide layer, dielectric layer and the areas P+ respectively.The embodiment of the present invention efficiently solves in the prior art, the non-clamp perception switch of VDMOS（UIS）The low technical problem of ability.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of vertical DMOS transistors
（Vertical Double-diffused MOSFET；Referred to as：VDMOS）Manufacturing method and VDMOS.
Background technology
Fig. 1 is the structure principle chart of prior art planar-type VDMOS, as shown in Figure 1, being opened to improve non-clamp perception
It closes（UIS）Ability, that is, the triode ON for preventing source region, body area and N-type epitaxy layer three from being formed, the method that the prior art uses
For source region and body area are got up by metal short circuit.
But know from Fig. 1, the perceptual switch UIS abilities of its non-clamp of existing VDMOS are low, and there are still improve space.
Such as：Usual existing VDMOS, source region doping concentration is higher, and source region is contacted with the areas P+ and contacted for N+P, which can increase
Above-mentioned triode ON ability；Said circumstances result in the non-clamp perception switch of VDMOS（UIS）Ability declines.
Invention content
The present invention provides a kind of manufacturing method and VDMOS of VDMOS, for reducing with source region, body area and N-type epitaxy layer three
The ducting capacity for the triode ON that person is formed, and then improve UIS abilities.
On the one hand, the embodiment of the present invention provides a kind of manufacturing method of VDMOS, including：
Gate oxide, polysilicon layer, P- bodies area are sequentially generated in N-type epitaxy layer；
In P- bodies area, injection N-type impurity forms N-type source region, and the N-type source region includes N- source regions and N+ source regions；It is described
N+ source regions are between the gate oxide and N- source regions；
Oxide layer, the areas P+, dielectric layer, contact hole and metal are sequentially formed on the polysilicon layer and the gate oxide
Layer, so that the metal layer side with every layer in the N- source regions, N+ source regions, gate oxide, oxide layer, dielectric layer respectively
And the areas P+ are connected.
On the other hand, the embodiment of the present invention provides a kind of VDMOS, including：N-type substrate, in N-type substrate upper surface shape
At N-type epitaxy layer, the N-type epitaxy layer upper surface formed gate oxide, the gate oxide upper surface formed
Polysilicon layer, the P- bodies area formed in the N-type substrate, the N-type source region by being formed in P- bodies area injection N-type impurity,
The N-type source region includes N- source regions and N+ source regions；The N+ source regions are between the gate oxide and N- source regions；In the P-
The P+ bodies area formed in body area, the contact hole formed above P+ bodies area, and in the upper surface of the dielectric layer, described
The metal layer that in the contact hole and lower surface of the N-type substrate is formed；
Wherein, the metal layer respectively with the N- source regions, the N+ source regions, the gate oxide, the oxide layer and
Every layer of side and the areas P+ are connected in the dielectric layer.
N-type source region is divided into two parts by the manufacturing method and VDMOS of VDMOS provided by the invention；I.e. in N-type source region
N+ source regions are formed in the subregion of the first oxide layer, the shape in the subregion far from the first oxide layer in N-type source region
At N- source regions.This N-type source structure makes N-type source region and body area under the premise of ensureing impurity concentration needed for its normal work
Contact surface is that low-doped N- source regions are contacted with the areas PXing Ti, effectively reduces the parasitism three constituted with source-body-epitaxial layer
The emitter injection efficiency of pole pipe enhances the UIS abilities of VDMOS to reduce the possibility of parasitic triode conducting.
Description of the drawings
Fig. 1 is the cross-sectional view of VDMOS in the prior art；
Fig. 2 is the flow chart of manufacturing method one embodiment of VDMOS provided in an embodiment of the present invention；
Fig. 3 a are the schematic diagram of the forming method of gate oxide and polysilicon layer in the embodiment of the present invention；
Fig. 3 b are the schematic diagram of the forming method in the areas ZhongP-Ti of the embodiment of the present invention
Fig. 3 c are the schematic diagram of the forming method of N-type source region in the embodiment of the present invention；
Fig. 3 d are the schematic diagram of oxide layer and the forming method in P+ bodies area in the embodiment of the present invention；
Fig. 3 e are the schematic diagram of the generation type of dielectric layer of the embodiment of the present invention and contact hole；
Fig. 3 f are the schematic diagram of the generation type of metal layer in the embodiment of the present invention；
Fig. 3 g are the schematic diagram of contact hole inner convex platform structure forming manner in the embodiment of the present invention；
Fig. 3 h are the schematic diagram of the first P+ type area generation type in the embodiment of the present invention
Fig. 3 i are the simultaneous formation schematic diagram of contact hole and the first P+ type area in the embodiment of the present invention.
Specific implementation mode
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described.For convenience of explanation, amplification or
The size of different layer and region is reduced, so size as shown in the figure and ratio might not represent actual size, is not also reflected
The proportionate relationship of size.
Fig. 2 is the flow chart of manufacturing method one embodiment of VDMOS provided in an embodiment of the present invention, as shown in Fig. 2, should
Method specifically includes：
S201 sequentially generates gate oxide, polysilicon layer, P- bodies area in N-type epitaxy layer；
In the present embodiment, Fig. 3 a are the signal of the forming method of gate oxide and polysilicon layer in the embodiment of the present invention
The gate oxide, as shown in Figure 3a, is formed in the upper surface of N-type epitaxy layer, and formed in the upper surface of the gate oxide by figure
Polysilicon layer.Wherein, N-type epitaxy layer is formed in the upper surface of N-type substrate.The growth of gate oxide layer temperature is greater than or equal to 900
DEG C, and it is less than or equal to 1100 DEG C；Its thickness is greater than or equal to 0.05um, and is less than or equal to 0.20um.The polysilicon layer is given birth to
Long temperature is greater than or equal to 500 DEG C, and is less than or equal to 700 DEG C；Its thickness is greater than or equal to 0.3um, and is less than or equal to
0.8um。
In addition, Fig. 3 b are the schematic diagram of the forming method in the areas ZhongP-Ti of the embodiment of the present invention, as shown in Figure 3b, P- bodies area
Generation type is specially：Inject boron ion to form P- bodies area, wherein the dosage of boron ion be greater than or equal to 1.0E13/
cm2, and less than or equal to 1.0E15/cm2；Its energy is greater than or equal to 100KEV, and is less than or equal to 150KEV.Then it adopts
It is driven in temperature with default and default driven in the time P- bodies area is driven in, wherein this is default to drive in temperature and be greater than or equal to
1100 DEG C, and it is less than or equal to 1200 DEG C；It is default to drive in the time more than or equal to 50 minutes, and be less than or equal to 200 minutes.
S202, in P- bodies area, injection N-type impurity forms N-type source region, which includes N- source regions and N+ source regions；The N+
Source region is between gate oxide and N- source regions；
Fig. 3 c are the schematic diagram of the forming method of N-type source region in the embodiment of the present invention, as shown in Figure 3c, the shape of N-type source region
It is specially at mode：In P- bodies area, injection N-type impurity forms N-type source region, which includes N- source regions and N+ source regions；Wherein,
N+ source regions are between gate oxide and N- source regions.
A kind of specific implementation of injection N-type impurity is shown in particular in the present embodiment：Injection process is divided into twice
Injection injects phosphonium ion to form the N- region portions of N-type source region in P- bodies area first, and the dosage of the phosphonium ion is greater than or equal to
1.0E13 a/cm2, and less than or equal to 1.0E14/cm2；Its energy is and to be less than or equal to more than or equal to 100KEV
150KEV；Secondly, it re-injects arsenic ion in P- bodies area and forms N+ region portions, the dosage of the arsenic ion is greater than or equal to
1.0E15 a/cm2, and less than or equal to 1.0E16/cm2；Its energy is and to be less than or equal to more than or equal to 100KEV
150KEV.Before injecting arsenic ion, if the thickness of above-mentioned gate oxide is more than 0.05um, need to carry out gate oxide
Otherwise etching can influence the injection of arsenic ion so that the thickness of gate oxide is less than or equal to 0.05um.
S203 sequentially formed on the polysilicon layer and the gate oxide oxide layer, the areas P+, dielectric layer, contact hole and
Metal layer so that metal layer respectively with every layer of side in N- source regions, N+ source regions, gate oxide, oxide layer, dielectric layer and
The areas P+ are connected；
In the present embodiment, Fig. 3 d are the schematic diagram of oxide layer and the forming method in P+ bodies area in the embodiment of the present invention, such as
Shown in Fig. 3 d, the generation type in the oxide layer and P+ bodies area is specially：In the upper surface of polysilicon layer and gate oxide using low
The method for pressing chemical vapor deposition forms oxide layer, wherein the growth temperature of the oxide layer is greater than or equal to 600 DEG C, and is less than
Or it is equal to 800 DEG C；Its thickness is greater than or equal to 0.1um, and is less than or equal to 0.3um.It is then injected into boron ion（That is institute in Fig. 3 d
The p-type ion shown）To form the P+ bodies area, wherein the boron ion dosage is greater than or equal to 1.0E15/cm2, and be less than or wait
In 1.0E16/cm2；Its energy be more than or equal to 100KEV, and be less than or equal to 150KEV.
In addition, Fig. 3 e are the schematic diagram of the generation type of dielectric layer of the embodiment of the present invention and contact hole, as shown in Figure 3 e,
Dielectric layer is by undoping silica and phosphorosilicate glass is made, wherein the thickness of the silica to undope is 0.2um；Phosphorus silicon
The thickness of glass is 0.8um.
Fig. 3 f are the schematic diagram of the generation type of metal layer in the embodiment of the present invention, as illustrated in figure 3f, in dielectric layer side
Metal layer can be referred to as front metal layer.Metal layer in N-type substrate side is referred to as metal layer on back（Or titanium nickeline is compound
Layer）.By Fig. 3 f it is found that front metal layer respectively with N- source regions, N+ source regions, gate oxide, oxide layer, dielectric layer side and
The areas P+ are connected.
The manufacturing method of VDMOS provided by the invention sequentially generates gate oxide, polysilicon layer, P- in N-type epitaxy layer
Body area；In P- bodies area, injection N-type impurity forms N-type source region, which includes N- source regions and N+ source regions；The N+ source regions are located at
Between the gate oxide and N- source regions；Oxide layer, the areas P+, dielectric layer, contact hole and metal layer are sequentially formed again, so that golden
Belong to floor to be respectively connected with N- source regions, N+ source regions, gate oxide, oxide layer, the side of dielectric layer and the areas P+.The program
N-type source region is divided into two parts；N+ source regions are formed in the subregion of the first oxide layer i.e. in N-type source region, in N-type source
N- source regions are formed in area in subregion far from the first oxide layer.This N-type source structure is ensureing needed for its normal work
Under the premise of impurity concentration, so that N-type source region is contacted with the areas PXing Ti for low-doped N- source regions with body area contact surface, effectively reduce
The emitter injection efficiency of the parasitic triode constituted with source-body-epitaxial layer, to reduce parasitic triode conducting
May, enhance the UIS abilities of VDMOS.
Further, on the basis of above-mentioned embodiment illustrated in fig. 2, the one kind for forming contact hole in step 203 is specific
Realization method is：
The original contact hole structure of contact hole is formed using preset technological process；The original contact hole structure is such as Fig. 3 e
Shown in contact hole structure.The side wall of its contact hole is a smooth surface.
Wet etching, the part grid oxygen of removal N+ area surfaces covering are carried out to the side wall of original contact hole using hydrofluoric acid
Change layer, oxide layer and dielectric layer, with the N+ source regions position formation boss structure on the side wall of contact hole.Fig. 3 g are the present invention
The schematic diagram of contact hole inner convex platform structure forming manner in embodiment.Finally by the original contact hole structure comprising the boss structure
As the structure of contact hole final in embodiment illustrated in fig. 2, the filling for carrying out metal layer is may thereafter continue to, by source region and P- bodies
Area's short circuit gets up.This boss structure makes the contact area of metal layer and source region increase, and short circuit effect improves, can be further
Reduce the possibility of the parasitic triode conducting constituted with source-body-epitaxial layer.To further improve VDMOS device
UIS abilities.
Further, on the basis of above-mentioned embodiment illustrated in fig. 2, after forming contact hole, and metal layer is formed
Before, further include：
Implanting p-type impurity in the contact hole, to form the first P+ type area in P- bodies area.Fig. 3 h are in the embodiment of the present invention
The schematic diagram of first P+ type area generation type.As illustrated in figure 3h, the implanting p-type impurity such as boron ion into contact hole, to form
One P+ type area, wherein the dosage for injecting boron ion is greater than or equal to 1.0E15/cm2, and less than or equal to 1.0E16/cm2；
Its energy be more than or equal to 100KEV, and be less than or equal to 150KEV.The first P+ type area can further decrease P- bodies area
Interior resistance increases the short circuit effect of source region and P- bodies area, to further improve the UIS abilities of VDMOS device.
It further, can also be by the boss knot of the formation of above-mentioned contact hole on the basis of above-mentioned embodiment illustrated in fig. 2
Structure is combined with the first P+ type plot structure, that is, the simultaneous formation of contact hole and the first P+ type area formed as shown in figure 3i is shown
It is intended to.
In the present embodiment, by contact hole area surface form above-mentioned boss structure and increase connecing for source region and metal layer
Contacting surface is accumulated；And the first P+ type area is formed in P- bodies area to reduce the overall electrical resistance in P- bodies area, increase source region and P- bodies area
Short circuit effect, to further improve the UIS abilities of VDMOS device.
The present invention also provides a kind of VDMOS, including：N-type substrate, N-type substrate upper surface formed N-type epitaxy layer,
In the gate oxide that N-type epitaxy layer upper surface is formed, in the polysilicon layer that gate oxide upper surface is formed, the shape in N-type substrate
At P- bodies area, by the N-type source region that is formed of P- bodies area injection N-type impurity, the N-type source region includes N- source regions and N+ source regions；
The N+ source regions are between gate oxide and N- source regions；The P+ bodies area formed in P- bodies area, what is formed above P+ bodies area connects
Contact hole, and in the upper surface of dielectric layer, the contact hole and the lower surface of N-type substrate formed metal layer；
Wherein, metal layer respectively with every layer of side in N- source regions, N+ source regions, gate oxide, oxide layer, dielectric layer and
The areas P+ are connected.
Further, further include：The portion being in contact with the side wall of gate oxide, oxide layer and dielectric layer in above-mentioned metal layer
Subregion, it is horizontally extending to N+ area surfaces, so that the surface that metal layer is in contact with N+ source regions forms boss knot
Structure.
Further, further include：The the first P+ type area formed in P- bodies area, the first P+ type area are contacted with the areas P+.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (5)
1. a kind of manufacturing method of VDMOS, which is characterized in that including：
Gate oxide, polysilicon layer, P- bodies area are sequentially generated in N-type epitaxy layer；
In P- bodies area, injection N-type impurity forms N-type source region, and the N-type source region includes N- source regions and N+ source regions；The sources N+
Area is between the gate oxide and N- source regions；
Oxide layer, the areas P+, dielectric layer, contact hole and metal layer are sequentially formed on the polysilicon layer and the gate oxide,
So that the metal layer respectively with every layer in the N- source regions, N+ source regions, gate oxide, oxide layer, dielectric layer of side with
And the areas P+ are connected；
Wherein, the process of the contact hole is formed, including：
The original contact hole structure of the contact hole is formed using preset technological process；
Wet etching is carried out to the side wall of the original contact hole using hydrofluoric acid, removes the part of the N+ area surfaces covering
The gate oxide, the oxide layer and the dielectric layer, with the N+ source regions position on the side wall of the contact hole
Form boss structure；
Using the original contact hole structure comprising the boss structure as the final contact hole.
2. according to the method described in claim 1, it is characterized in that, described form the sources N- in P- bodies area injection N-type impurity
Area and N+ source regions, including：
In P- bodies area, injection phosphonium ion forms N- source regions；
Arsenic ion is injected in P- bodies area forms N+ source regions.
3. according to the method described in claim 2, it is characterized in that, described form the sources N- in P- bodies area injection N-type impurity
The N-type impurity of Qu Shi, injection are phosphonium ion, and implantation dosage is 1.0E13~1.0E14/cm2, Implantation Energy be 100kEV~
150KEV。
4. according to the method described in claim 2, it is characterized in that, described re-inject N-type impurity shape in the N- source regions
When at N+ source regions, the N-type impurity of injection is arsenic ion, and implantation dosage is 1.0E15~1.0E16/cm2, Implantation Energy is
100kEV~150KEV.
5. according to claim 1-4 any one of them methods, which is characterized in that after forming the contact hole, and formed
Before the metal layer, further include：
Implanting p-type impurity in the contact hole, to form the first P+ type area in P- bodies area.
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| CN107342224B (en) * | 2016-05-03 | 2020-10-16 | 北大方正集团有限公司 | Manufacturing method of VDMOS device |
| CN105931970A (en) * | 2016-06-30 | 2016-09-07 | 杭州士兰集成电路有限公司 | Planar gate power device structure and formation method therefor |
| CN107331621A (en) * | 2017-07-14 | 2017-11-07 | 欧阳慧琳 | A kind of vertical bilateral diffusion field-effect tranisistor and preparation method thereof |
| CN110942992B (en) * | 2018-09-21 | 2021-08-17 | 无锡华润上华科技有限公司 | Vertical double-diffused semiconductor component and manufacturing method thereof |
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| CN1937176A (en) * | 2005-09-23 | 2007-03-28 | 半导体元件工业有限责任公司 | Method of forming a low resistance semiconductor contact and structure therefor |
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| US8008719B2 (en) * | 2008-10-09 | 2011-08-30 | Hvvi Semiconductors, Inc. | Transistor structure having dual shield layers |
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| CN1937176A (en) * | 2005-09-23 | 2007-03-28 | 半导体元件工业有限责任公司 | Method of forming a low resistance semiconductor contact and structure therefor |
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