CN103996622A - Method for manufacturing VDMOS - Google Patents
Method for manufacturing VDMOS Download PDFInfo
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- CN103996622A CN103996622A CN201310056245.1A CN201310056245A CN103996622A CN 103996622 A CN103996622 A CN 103996622A CN 201310056245 A CN201310056245 A CN 201310056245A CN 103996622 A CN103996622 A CN 103996622A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 150000002500 ions Chemical class 0.000 claims abstract description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- -1 phosphonium ion Chemical class 0.000 claims description 32
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 229910052796 boron Inorganic materials 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 238000002347 injection Methods 0.000 abstract description 7
- 239000007924 injection Substances 0.000 abstract description 7
- 238000005530 etching Methods 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract 5
- 238000007254 oxidation reaction Methods 0.000 abstract 5
- 238000000151 deposition Methods 0.000 abstract 1
- 238000003384 imaging method Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000004411 aluminium Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 5
- 238000003475 lamination Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The embodiment of the invention provides a method for manufacturing a VDMOS. The method comprises the following steps: providing an N type substrate and forming an N type epitaxial layer at a first surface of the substrate; growing field oxide at the N type epitaxial layer to form a field oxidation layer; etching an active zone at the field oxidation layer and injecting N type ions and carrying out driving; etching at least one ring zone at the field oxidation layer and injecting P type ions into the ring zone; growing gate oxide at the active zone and the ring zone to form a gate oxidation layer; forming a threshold injection layer below the upper surface of the N type epitaxial layer; depositing polycrystalline silicon at the gate oxidation layer to form a polycrystalline layer used as a grid electrode of a VDMOS; injecting P type ions into the active zone and the two sides of the polycrystalline silicon layer and carrying out driving; forming a source electrode of the VDMOS at the zone with driven P type ions; carrying out reduction on a second surface of the substrate and growing a metal layer at the reduced second surface to form a drain electrode of the VDMOS. With the method, the voltage can be adjusted at any time; and the method can be implemented conveniently.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technical field, relate in particular to a kind of manufacture method of VDMOS device.
Background technology
At present, the technique of the vertical double diffusion Metal-Oxide Semiconductor of existing making field-effect transistor (VDMOS), generally includes following making flow process:
Step 1, as shown in Figure 1A, provides a N-type substrate 101, forms N-type epitaxial loayer 102 on the first surface of substrate.
Step 2, as shown in Figure 1B, in N-type epitaxial loayer 102 growth of oxygen of entering the court, forms field oxide 103.
In this step 2, preferably can in the scopes of 1100～1200 degree, carry out an oxide growth, and form the thickness of this field oxide 103 can be between 0.8～1.4 micron, why form this layer, be mainly to use in order to do isolation;
Step 3 as shown in Figure 1 C, etches active area 104 on field oxide 103, and injects N-type ion in active area 104 and drive in (as shown in Fig. 1 D).
In this step 3, specifically can etch active area 104 by following flow process: first on field oxide 103, be coated with photoresistance; Then a selected region on the field oxide after coating, and the mode by exposure imaging is got rid of the photoresistance on this region on this piece region; After the method that re-uses wet etching etches away the field oxide on this region, it is the above-mentioned active area etching 104.Active area 104 is mainly that for example, the making of subsequent device can be all on this region as the working region that makes device (VDMOS); The N-type ion injecting in step 3 can be phosphonium ion, the concentration of injecting can be 12 power levels, and the energy of phosphonium ion can be controlled between 80KeV～120KeV, while driving in phosphonium ion, temperature can be controlled to 1100～1200 degree, the time of driving in can be controlled at 2-4 hour; And why this step injects phosphonium ion, be mainly in order to prevent that adjacent active area from ganging up making when device.
Step 4 as shown in Fig. 1 E, etches at least one ring district 105 (be generally more than 4, Yi Gehuan district is only shown in figure) on field oxide 103, injects P type ion (as shown in Fig. 1 F) in each ring district 105.
In this step 4, the idiographic flow that etches ring district is identical with the flow process that etches active area, does not repeat them here.In addition, the P type ion of injection can be boron ion, and the concentration of injection can be 15 power levels, and the energy of boron ion can be controlled at 60KeV～90KeV.
Step 5, as shown in Figure 1 G, the grid oxygen of growing in 104He Huan district, active area 105, forms gate oxide 106.
In this step 5, the thickness of growth grid oxygen generally, between 500A～1500A, is determined with the operating voltage of device conventionally.
Step 6, as shown in Fig. 1 H, deposit spathic silicon on gate oxide 106, forms polysilicon layer 107 (only shown with in source region), sets it as the grid of VDMOS.
In this step 6, specifically can form polysilicon layer by following flow process: first on gate oxide 106, deposit the polysilicon of one deck resistance lowering, thickness can be controlled between 0.8 micron ~ 1.2 microns; Then on this layer of polysilicon, be coated with photoresistance, and remove in advance as the photoresistance on other regions beyond grid by the mode of exposure imaging, finally, by dry etching method, the gate oxide on other regions is etched away, only retain the polysilicon layer as grid.
Step 7, as shown in Figure 1 I, injects P type ion and drives in active area 104 and in the both sides of polysilicon layer 107.
In this step 7, the energy of the boron ion injecting can be controlled between 60KeV～100KeV, implantation concentration can be 13 power levels, driving in boron ion is to shift the boron ion of injection onto the needed degree of depth, conventionally technological temperature is controlled between 1000～1200 degree, and the time driving in is controlled at 2-3 hour.
Step 8 as shown in Fig. 1 J, forms the source electrode 108 of VDMOS on the region that drives in P type ion.
In this step 8, specifically can form by following flow process the source electrode 108 of VDMOS: first on the region of injecting P type ion, be coated with photoresistance; Then remove the photoresistance as source electrode region in advance by the mode of exposure imaging; Last toward injecting arsenic ion or phosphonium ion as source electrode region place in advance, form the source electrode 108 of VDMOS.Here, the concentration of injecting arsenic ion or phosphonium ion can be 15 power levels, and energy is controlled at 60KeV～130KeV.
Step 9, carries out attenuate to the second surface of substrate 101, and growing metal layer on second surface after attenuate, forms the drain electrode of VDMOS.
In this step 9, can the second surface of substrate 101 be ground off by physics mode, until wafer thickness is also left 100 ~ 300 microns; Can also inject phosphonium ion at second surface, implantation concentration can be 15 power levels, and the energy that injects phosphonium ion is 40 ~ 70kev.In addition, the metal level of growth can be titanium, nickel or silver, and their corresponding thickness can be respectively 0.1um, 0.2um or 1um.
Conventionally in the time making VDMOS, before above-mentioned steps nine, also need to make contact hole, aluminium lamination and the sheath etc. of VDMOS, particularly, the technological process of making the contact hole of VDMOS is: on N-type epitaxial loayer, deposit the oxide layer of one deck doped with boron and phosphorus, and then high temperature reflux, temperature can be at 800 ~ 1000 degree, return time can be 30 ~ 120 minutes, can pass into nitrogen or a small amount of oxygen in this process; Then in this oxide layer, be coated with photoresistance, remove the photoresistance as contact hole region in advance by the mode of exposure imaging, then by the method for wet etching or dry etching, this is etched away as the oxide layer in contact hole region in advance, formed the contact hole of VDMOS, in this case, just expose silicon and polysilicon below.
Particularly, the technological process of the aluminium lamination of making VDMOS is: on N-type epitaxial loayer, deposit one deck aluminium, thickness can be at 3 ~ 4 microns; Then at this layer coating photoresistance, by the mode of exposure imaging, the photoresistance in non-wiring region is got rid of; Finally, by the method for dry etching or wet etching, the aluminium that removes photoresistance region is etched away, so just only retained and need to do the aluminium lamination connecting up.
Particularly, the technological process of the sheath of making VDMOS is: on epitaxial loayer, deposit layer of oxide layer or silicon nitride or oxide layer and silicon nitride; On this layer, be coated with photoresistance, remove as the photoresistance on grid welding spot and source electrode solder joint pre-by the mode of exposure imaging; Finally by dry etching using pre-on grid welding spot and source electrode solder joint oxide layer or silicon nitride or oxide layer and and silicon nitride etch fall.
In the VDMOS producing through above-mentioned steps one to step 9; conventionally 5 important static parameters be can relate to, BVdss (source drain breakdown voltage), Rdson (conducting resistance), Vth (cut-in voltage), Idss (electric leakage is leaked in source) and Igss (source grid leak electricity) are specially.Generally, these five parameters need to reach user's demand simultaneously, and VDMOS could normally work, and different users may be to the demand difference of parameter, and these parameters can be subject to the impact (specifically affecting relation shown in Figure 2) of more aforementioned steps.
In the process debugging of making VDMOS, tend to occur such problem, in the time only needing to regulate BVdss and Rdson, for example Vth of other parameters also can change thereupon, in this case, for Vth is recalled to, will change concentration, the energy of N-type ion or P type ion or drive in (drive-in) time, but, when changing these conditions, can have influence on again these two parameters of BVdss and Rdson, this has just formed a kind of vicious circle, cannot make all the time each parameter all be transferred to position.For example BVdss and Rdson have been transferred to position, and Vth has drifted about; Or Vth has been transferred to position, and BVdss and Rdson have drifted about.
Occur that the main cause of the problems referred to above is that the processing step that affects BVdss, Rdson and Vth is all identical, that is to say, a processing step can affect multiple parameters (except step 4), like this, changing wherein arbitrary processing step in the situation that, all can have influence on other parameters simultaneously.In view of this, the VDMOS that the method for existing making VDMOS is produced, user uses very inconvenient.
Summary of the invention
The embodiment of the present invention provides the method for VDMOS of making a kind of, uses inconvenient problem in order to solve the VDMOS that existing making VDMOS method produces.
Based on the problems referred to above, the method for a kind of VDMOS of making that the embodiment of the present invention provides, comprising:
One N-type substrate is provided, on the first surface of described substrate, forms N-type epitaxial loayer;
On described N-type epitaxial loayer, raw long field oxide, forms field oxide;
On described field oxide, etch active area, and inject N-type ion and drive in described active area;
On described field oxide, etch at least one ring district, and inject P type ion in each ring district;
The grid oxygen of growing in described active area and described ring district, forms gate oxide;
Below the upper surface of described N-type epitaxial loayer, form threshold value implanted layer;
Deposit spathic silicon on described gate oxide, forms polysilicon layer, as the grid of VDMOS;
Inject P type ion and drive in described active area and in the both sides of described polysilicon layer;
On the region that drives in P type ion, etch the source electrode of VDMOS;
The second surface of described substrate is carried out to attenuate, and growing metal layer on second surface after attenuate, the drain electrode of VDMOS formed.
The beneficial effect of the embodiment of the present invention comprises: the method for the making VDMOS that the embodiment of the present invention provides, in the method, the grid oxygen of growing in He Huan district, source region, after forming gate oxide, on gate oxide before deposit spathic silicon, the below that is also included in the upper surface of N-type epitaxial loayer forms this step of threshold value implanted layer, this step can regulate according to user's actual demand the threshold voltage of VDMOS, that is to say, only need to change this step, just can complete the adjusting of threshold voltage, can not have influence on other parameters (without changing other processing steps), for example, while needing to heighten threshold voltage, inject P type ion, when threshold voltage need to be turned down, inject N-type ion.So, user uses VDMOS that aforementioned this method produces more for convenience.
Brief description of the drawings
Figure 1A to Fig. 1 J is the method flow diagram of existing making VDMOS;
Fig. 2 is that affecting between the technique of existing making VDMOS and static parameter is related to schematic diagram;
The method flow diagram of the making VDMOS that Fig. 3 A to Fig. 3 K provides for the embodiment of the present invention.
Embodiment
Below in conjunction with Figure of description, the embodiment of the method for a kind of VDMOS of making that the embodiment of the present invention is provided describes.
The method of a kind of VDMOS of making that the embodiment of the present invention provides, in the method for existing making VDMOS, the grid oxygen of growing in He Huan district, active area, after forming gate oxide, and on gate oxide before deposit spathic silicon, increase the step that forms threshold value implanted layer below the upper surface of N-type epitaxial loayer.
Below in conjunction with Fig. 3 A to Fig. 3 K, the flow process of the making VDMOS that the embodiment of the present invention is provided describes, and specifically can realize by following step:
Step 1, as shown in Figure 3A, provides a N-type substrate 301, forms N-type epitaxial loayer 302 on the first surface of substrate.
Step 2, as shown in Figure 3 B, in N-type epitaxial loayer 302 growth of oxygen of entering the court, forms field oxide 303.
In this step 2, preferably can in the scopes of 1100～1200 degree, carry out an oxide growth, and form the thickness of this field oxide 303 can be between 0.8～1.4 micron, why form this layer, be mainly to use in order to do isolation.
Step 3 as shown in Figure 3 C, etches active area 304 on field oxide 303, and injects N-type ion in active area 304 and drive in (as shown in Figure 3 D).
In this step 3, specifically can etch active area 104 by following flow process: first on field oxide 103, be coated with photoresistance; Then a selected region on the field oxide after coating, and the mode by exposure imaging is got rid of the photoresistance on this region on this piece region; After the method that re-uses wet etching etches away the field oxide on this region, it is the above-mentioned active area etching 104.Active area 304 is mainly that for example, the making of subsequent device can be all on this region as the working region that makes device (VDMOS); The N-type ion injecting in step 3 can be phosphonium ion, the concentration of injecting can be 12 power levels, and the energy of phosphonium ion can be controlled between 80KeV～120KeV, while driving in phosphonium ion, temperature can be controlled to 1100～1200 degree, the time of driving in can be controlled at 2-4 hour; And why this step injects phosphonium ion, be mainly in order to prevent that adjacent active area from ganging up making when device.
Step 4 as shown in Fig. 3 E, etches at least one ring district 305 (be generally more than 4, Yi Gehuan district is only shown in figure) on field oxide 303, injects P type ion (as shown in Fig. 3 F) in each ring district 105.
In this step 4, the idiographic flow that etches ring district is identical with the flow process that etches active area, does not repeat them here.In addition, the P type ion of injection can be boron ion, and the concentration of injection can be 15 power levels, and the energy of boron ion can be controlled at 60KeV～90KeV.
Step 5, as shown in Fig. 3 G, the grid oxygen of growing in 304He Huan district, active area 305, forms gate oxide 306.
In this step 5, the thickness of growth grid oxygen generally, between 500A～1500A, is determined with the operating voltage of device conventionally.
Step 6 as shown in Fig. 3 H, forms threshold value implanted layer 307 below the upper surface of N-type epitaxial loayer 302.
In this step 6, preferably, the degree of depth of threshold value implanted layer 307 is 0.01～0.04 micron; When user needs (while needing to heighten threshold voltage) when high-tension VDMOS, can on threshold value implanted layer 307, inject the degree of depth and be the boron ion of 0.11～0.13 micron, the energy of boron ion can be 35KeV～40KeV; In the time that user needs the VDMOS of low-voltage (while needing to turn down threshold voltage), can on threshold value implanted layer 307, inject the degree of depth and be the phosphonium ion of 0.11～0.14 micron, the energy of phosphonium ion can be 9KeV～110KeV.
Step 7, as shown in Fig. 3 I, deposit spathic silicon on gate oxide 306, forms polysilicon layer 308 (only shown with in source region), sets it as the grid of VDMOS.
In this step 7, specifically can form polysilicon layer by following flow process: first on gate oxide 106, deposit the polysilicon of one deck resistance lowering, thickness can be controlled between 0.8 micron ~ 1.2 microns; Then on this layer of polysilicon, be coated with photoresistance, and remove in advance as the photoresistance on other regions beyond grid by the mode of exposure imaging, finally, by dry etching method, the gate oxide on other regions is etched away, only retain the polysilicon layer as grid.
Step 8, as shown in Fig. 3 J, injects P type ion and drives in active area 304 and in the both sides of polysilicon layer 308.
In this step 8, the energy of the P type ion (for example boron ion) injecting can be controlled between 60KeV～100KeV, implantation concentration can be 13 power levels, driving in boron ion is to shift the boron ion of injection onto the needed degree of depth, conventionally technological temperature is controlled between 1000～1200 degree, and the time driving in is controlled at 2-3 hour.
Step 9 as shown in Fig. 3 K, forms the source electrode 309 of VDMOS on the region that drives in P type ion.
In this step 9, specifically can form by following flow process the source electrode 108 of VDMOS: first on the region of injecting P type ion, be coated with photoresistance; Then remove the photoresistance as source electrode region in advance by the mode of exposure imaging; Last toward injecting arsenic ion or phosphonium ion as source electrode region place in advance, form the source electrode 108 of VDMOS.Here, the concentration of injecting arsenic ion or phosphonium ion can be 15 power levels, and energy is controlled at 60KeV～130KeV.
Step 10, carries out attenuate to the second surface of substrate 301, and growing metal layer on second surface after attenuate, forms the drain electrode of VDMOS.
In this step 10, can the second surface of substrate 101 be ground off by physics mode, until wafer thickness is also left 100 ~ 300 microns; Can also inject phosphonium ion at second surface, implantation concentration can be 15 power levels, and the energy that injects phosphonium ion is 40 ~ 70kev.In addition, the metal level of growth can be titanium, nickel or silver, and their corresponding thickness can be respectively 0.1um, 0.2um or 1um.
Conventionally in the time making VDMOS, before step 10, also need to make contact hole, aluminium lamination and the sheath etc. of VDMOS, making contact hole, the aluminium lamination of VDMOS and the technological process of protecting is existing procedure, does not repeat them here.
In the process debugging of above-mentioned making VDMOS, owing to having increased this step of formation threshold value implanted layer in said method, so, in the time that user need to heighten or turn down threshold voltage, can inject corresponding ion and realize adjusting, because the degree of depth of this threshold value implanted layer is 0.01 ~ 0.04 micron, injecting like this ion just concentrates on from the position of 0.01 ~ 0.04 micron of the silicon face of N-type epitaxial loayer, even if drive in through P type ion, the concentration of injecting ion is also concentrated between 0.03 ~ 0.1 micron, the shallow like this ion degree of depth, can ensure can not have influence on other parameter of VDMOS, and just to threshold value implanted layer generation effect, use more convenient.
The method of the making VDMOS that the embodiment of the present invention provides, in the method, the grid oxygen of growing in He Huan district, source region, after forming gate oxide, on gate oxide before deposit spathic silicon, the below that is also included in the upper surface of N-type epitaxial loayer forms this step of threshold value implanted layer, this step can regulate according to user's actual demand the threshold voltage of VDMOS, that is to say, only need to change this step, just can complete the adjusting of threshold voltage, can not have influence on other parameters (without changing other processing steps), for example, while needing to heighten threshold voltage, inject P type ion, when threshold voltage need to be turned down, inject N-type ion.So, user uses VDMOS that aforementioned this method produces more for convenience.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (5)
1. a method of making vertical double diffusion Metal-Oxide Semiconductor field-effect transistor VDMOS, is characterized in that, comprising:
One N-type substrate is provided, on the first surface of described substrate, forms N-type epitaxial loayer;
On described N-type epitaxial loayer, raw long field oxide, forms field oxide;
On described field oxide, etch active area, and inject N-type ion and drive in described active area;
On described field oxide, etch at least one ring district, and inject P type ion in each ring district;
The grid oxygen of growing in described active area and described ring district respectively, forms gate oxide;
Below the upper surface of described N-type epitaxial loayer, form threshold value implanted layer;
Deposit spathic silicon on described gate oxide, forms polysilicon layer, sets it as the grid of VDMOS;
Inject P type ion and drive in described active area and in the both sides of described polysilicon layer;
On the region that drives in P type ion, form the source electrode of VDMOS;
The second surface of described substrate is carried out to attenuate, and growing metal layer on second surface after attenuate, the drain electrode of VDMOS formed.
2. the method for claim 1, is characterized in that, described N-type ion is phosphonium ion, and described P type ion is boron ion.
3. method as claimed in claim 1 or 2, is characterized in that, the degree of depth of described threshold value implanted layer is 0.01～0.04 micron.
4. method as claimed in claim 3, is characterized in that, also comprises:
On described threshold value implanted layer, inject the degree of depth and be the N-type ion of 0.11～0.14 micron, the energy of described N-type ion is 9KeV～110KeV.
5. method as claimed in claim 3, is characterized in that, also comprises:
On described threshold value implanted layer, inject the degree of depth and be the P type ion of 0.11～0.13 micron, the energy of described P type ion is 35KeV～40KeV.
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| CN111540727A (en) * | 2020-03-28 | 2020-08-14 | 电子科技大学 | Metal wiring method for reducing gate resistance of small-size control gate structure |
| CN113363156A (en) * | 2021-05-31 | 2021-09-07 | 电子科技大学 | Method for optimizing VDMOS processing technology |
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| US4845047A (en) * | 1987-06-25 | 1989-07-04 | Texas Instruments Incorporated | Threshold adjustment method for an IGFET |
| US5248627A (en) * | 1992-03-20 | 1993-09-28 | Siliconix Incorporated | Threshold adjustment in fabricating vertical dmos devices |
| CN101431057B (en) * | 2008-12-11 | 2010-11-17 | 电子科技大学 | High-capacity BCD technique for twice etching single/poly-silicon |
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| CN111540727A (en) * | 2020-03-28 | 2020-08-14 | 电子科技大学 | Metal wiring method for reducing gate resistance of small-size control gate structure |
| CN113363156A (en) * | 2021-05-31 | 2021-09-07 | 电子科技大学 | Method for optimizing VDMOS processing technology |
| CN113363156B (en) * | 2021-05-31 | 2022-05-24 | 电子科技大学 | Method for optimizing VDMOS processing technology |
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