CN111341827A - N-type super junction device and manufacturing method thereof - Google Patents
N-type super junction device and manufacturing method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention discloses an N-type super junction device.A P-type column consists of a P-type epitaxial layer filled in a super junction groove; the super junction structure is arranged according to the improvement of the process consistency of the device, and the consistency improvement is realized by improving the size distribution and the doping concentration distribution uniformity of the P-type columns of the super junction units; under the condition that the stepping of the super junction unit is guaranteed to be unchanged or reduced, the consistency is improved by increasing the top width of the P-type column and setting the top width of the P-type column to be larger than the top width of the N-type column; under the condition that the width of the top of the N-type column is reduced, the on-resistance of the N-type column is ensured or reduced by increasing the doping concentration of the N-type column. The invention also discloses a manufacturing method of the N-type super junction device. The invention can improve the consistency of the device, simultaneously keeps or reduces the on-resistance of the device, and is beneficial to the high-temperature application of the device.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an N-type super junction (junction) device; the invention also relates to a manufacturing method of the N-type super junction device.
Background
The super junction structure is a structure of alternately arranged N-type columns and P-type columns. If a super-junction structure is used for replacing an N-type drift region in a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device, a conduction path is provided in a conduction state, for the N-type device, only an N-type column provides a path, and a P-type column does not provide a path; when the super-junction Metal-Oxide Semiconductor Field effect transistor (MOSFET) is subjected to reverse bias voltage in an off state, the P-type column and the N-type column are mutually transversely depleted and are commonly subjected to the reverse bias voltage, and a super-junction Metal-Oxide Semiconductor Field effect transistor (MOSFET) is formed. The super-junction MOSFET can greatly reduce the on-resistance of the device by using an epitaxial layer with low resistivity under the condition that the reverse breakdown voltage is consistent with that of a traditional VDMOS device.
The method for manufacturing the super junction is a manufacturing method of the super junction which can be produced in batch and is characterized in that a groove, namely a super junction groove, is formed in an N-type epitaxial layer, and P-type epitaxial layers are filled in the groove to form PN-type columns which are arranged alternately.
In the prior art, in order to obtain a lower specific on-resistance, the width of the N-type column of the PN-type column is generally designed to be greater than or equal to the width of the P-type column, so as to ensure that the area of the N-type region is increased and the specific on-resistance (Rsp) of the device is reduced, for example, the width of the P-type column and the width of the N-type column are 5 micrometers (P-type column)/12 micrometers (N-type column), 5 micrometers/8 micrometers, 5 micrometers/6 micrometers, 4 micrometers/5 micrometers, and 2 micrometers/3 micrometers in the existing practical use. That is, in the prior art, in order to reduce Rsp of the device, the width of the N-type column needs to be widened, but under the condition that the steps of the super junction unit, i.e., one P-type column and one N-type column, remain unchanged, the width of the P-type column will be reduced after the N-type column is widened; in the same super junction unit, in order to realize larger withstand voltage, charge balance between the P-type column and the N-type column is required, so that mutual transverse depletion of the P-type column and the N-type column can be realized in reverse bias; after the width of the P-type column is reduced, the total doping amount of the P-type column needs to be balanced with that of the N-type column, so that the doping concentration of the P-type column needs to be increased. In the existing method, the P-type column is usually realized by filling a P-type epitaxial layer in a super junction trench, and after the doping concentration of the P-type column is increased, the forming process of the P-type epitaxial layer is difficult to control. Generally, the process control of the doping concentration of the super junction trench P-type epitaxial layer is generally controlled by the offset percentage of a center line, for example, the resistivity changes within plus or minus 3%, the center line corresponds to an optimal balance position and is generally arranged at the center position in the depth direction of the super junction structure, so that after the absolute value of the doping concentration of a P-type column is increased, the process change with the same percentage increases the change of the total amount of impurities, the degree of charge imbalance is serious, the deviation of device performance, including the deviation of breakdown voltage, is large, and the consistency of the device is affected.
Disclosure of Invention
The invention aims to provide an N-type super junction device, which can improve the consistency of the device and simultaneously keep or reduce the on-resistance of the device. Therefore, the invention also provides a manufacturing method of the N-type super junction device.
In order to solve the technical problem, the N-type super junction device provided by the invention comprises a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns; each of the N-type columns and the P-type column adjacent thereto constitute one super junction cell.
The P-type column is composed of P-type epitaxial layers filled in the super-junction grooves, the N-type column is composed of N-type epitaxial layers located between the super-junction grooves, and the N-type epitaxial layers are formed on the surface of the semiconductor substrate.
The super junction structure is arranged according to the process consistency of the device, and the consistency improvement is realized by improving the size distribution and the doping concentration distribution uniformity of the P-type column of each super junction unit; under the condition that the super junction unit is guaranteed to be unchanged or reduced in stepping, the top width of the P-type column is increased and is set to be larger than that of the N-type column, so that consistency is improved; the larger the difference between the width of the top of the P-type column and the width of the top of the N-type column is, the lower the doping concentration of the P-type column is under the condition of ensuring the charge balance of the super junction units, and the lower the doping concentration of the P-type column is, the more the consistency is improved; under the condition that the width of the top of the N-type column is reduced, the on-resistance of the N-type column is ensured or reduced by improving the doping concentration of the N-type column, and the higher the doping concentration of the N-type column is, the lower the temperature sensitivity of the on-resistance is, so that the temperature application range of the device is favorably increased.
In a further improvement, an optimal balance position between the P-type column and the N-type column of each super junction unit is arranged at a center position in a depth direction of the super junction unit in the area, at the optimal balance position, the doping concentration multiplied by the width of the P-type column is equal to the doping concentration multiplied by the width of the N-type column, and the arrangement of the optimal balance position ensures that the breakdown position of the N-type super junction device tends to the center area of the super junction structure.
In a further improvement, the doping concentration of the P-type column varies within plus or minus 5% of the doping concentration at the optimal equilibrium position in the depth direction.
In a further improvement, the side surface of the super junction trench is inclined so as to facilitate the filling of the P-type epitaxial layer of the P-type column.
In a further improvement, the inclination angle of the side surface of the super junction groove is greater than or equal to 88.6 degrees and smaller than 90 degrees.
In a further improvement, the sides of the super junction trench are vertical to facilitate an increase in breakdown voltage.
In a further improvement, the N-type super junction device is an N-type super junction MOSFET, and further includes: the semiconductor device comprises a grid structure, a P-type well, a source region and a drain region.
The P-type well is formed on the top of the P-type column and extends to the top of the N-type column, and the surface of the P-type well covered by the gate structure is used for forming a channel.
The source region is formed in the P-type well.
The drain region is formed on the back of the super junction structure.
The further improvement is that the gate structure is a planar gate structure and comprises a gate dielectric layer and a polysilicon gate which are sequentially formed on the surface of the P-type trap, and the polysilicon gate covers the P-type trap from the top of the P-type trap.
The further improvement is that the P-type wells at the tops of two adjacent P-type columns have a spacing at the top of the same N-type column, the P-type wells are defined by a photoetching process, and JFET injection regions are formed in the spacing between the two adjacent P-type wells.
The gate structure is a trench gate structure and comprises a gate dielectric layer and a polysilicon gate which are sequentially formed in a gate trench, wherein the polysilicon gate covers the P-type well from the side surface.
In a further improvement, the P-well is formed by blanket implantation, and the polysilicon gate longitudinally passes through the P-well.
In order to solve the technical problem, the invention provides a method for manufacturing an N-type super junction device, wherein the N-type super junction device comprises a super junction structure formed by a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; the super junction structure is formed by the following steps:
step one, providing a semiconductor substrate, and forming an N-type epitaxial layer on the surface of the semiconductor substrate.
And secondly, forming a hard mask layer formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer on the surface of the N-type epitaxial layer.
And step three, defining a forming area of the super junction groove by photoetching, and etching the hard mask layer and the N-type epitaxial layer in sequence to form the super junction groove.
And step four, removing the third oxide layer and the second nitride layer and reserving the first oxide layer with the whole or partial thickness.
And fifthly, filling a P-type epitaxial layer in the super junction groove by adopting an epitaxial growth process, wherein the P-type epitaxial layer also extends out of the super junction groove.
And sixthly, removing the P-type epitaxial layer outside the super junction groove by adopting a chemical mechanical polishing process, and then removing the first oxidation layer.
The P-type column is formed by P-type epitaxial layers filled in the super junction grooves, and the N-type column is formed by N-type epitaxial layers positioned between the super junction grooves.
The super junction structure is arranged according to the process consistency of the device, and the consistency improvement is realized by improving the size distribution and the doping concentration distribution uniformity of the P-type column of each super junction unit; under the condition that the super junction unit is guaranteed to be unchanged or reduced in stepping, the top width of the P-type column is increased and is set to be larger than that of the N-type column, so that consistency is improved; the larger the difference between the width of the top of the P-type column and the width of the top of the N-type column is, the lower the doping concentration of the P-type column is under the condition of ensuring the charge balance of the super junction units, and the lower the doping concentration of the P-type column is, the more the consistency is improved; under the condition that the width of the top of the N-type column is reduced, the on-resistance of the N-type column is ensured or reduced by improving the doping concentration of the N-type column, and the higher the doping concentration of the N-type column is, the lower the temperature sensitivity of the on-resistance is, so that the temperature application range of the device is favorably increased.
In a further improvement, an optimal balance position between the P-type column and the N-type column of each super junction unit is arranged at a center position in a depth direction of the super junction unit in the area, at the optimal balance position, the doping concentration multiplied by the width of the P-type column is equal to the doping concentration multiplied by the width of the N-type column, and the arrangement of the optimal balance position ensures that the breakdown position of the N-type super junction device tends to the center area of the super junction structure.
In a further improvement, the doping concentration of the P-type column varies within plus or minus 5% of the doping concentration at the optimal equilibrium position in the depth direction.
In a further improvement, the side surface of the super junction trench is inclined so as to facilitate the filling of the P-type epitaxial layer of the P-type column.
Or the side surface of the super junction groove is vertical, so that the breakdown voltage is conveniently improved.
The P-type column of the super-junction structure is composed of a P-type epitaxial layer filled in a super-junction groove, the super-junction structure is arranged according to the process consistency of a device, the consistency improvement is realized by improving the size distribution and the doping concentration distribution uniformity of the P-type column of each super-junction unit, and in the invention, under the condition of ensuring that the stepping of the super-junction unit is unchanged or reduced, the consistency is improved by increasing the top width of the P-type column and setting the top width of the P-type column to be larger than the top width of the N-type column; the principle of improving the process consistency by increasing the top width of the P-type is as follows: the larger the difference between the top width of the P-type column and the top width of the N-type column is, the lower the doping concentration of the P-type column is under the condition of ensuring the charge balance of each super-junction unit, and the lower the doping concentration of the P-type column is, because the process deviations are generally controlled according to percentages, under the same process deviation, such as under the condition that the process deviates by 3%, the lower the doping concentration is, the smaller the actual variation of the doping concentration is, and the consistency of the super-junction structure is determined according to the actual doping concentration deviations of the P-type column and the N-type column, so the lower the doping concentration of the P-type column is more favorable for improving the consistency.
In addition, under the condition that the width of the top of the N-type column is reduced, the doping concentration of the N-type column is increased to ensure or reduce the on-resistance of the N-type column, and the higher the doping concentration of the N-type column is, the lower the temperature sensitivity of the on-resistance is, so that the temperature application range of the device is increased, the characteristics of the device at high temperature are improved, the on-resistance at high temperature can be reduced, the loss is reduced, the junction temperature is reduced, and the service life of the device is prolonged. To this end, the following is explained: in the design of a common device, the on-resistance at 25 ℃ is taken as a design target, but in the actual use of the device, because of the existence of switching loss and conduction loss, the actual working temperature of the device, namely the junction temperature, can generally reach 50-120 ℃, the junction temperature of the device can generally be guaranteed to be operable at-55 ℃ to +150 ℃, because the device is usually in a high-temperature state in the working process, the on-resistance of the device at high temperature is very important in practice, and by reducing the on-resistance at high temperature, the loss can be reduced, the junction temperature of the device can be reduced, and the service life of the device can be prolonged.
In addition, after the width of the P-type column is increased, the width of the super junction groove is also increased, so that the depth-to-width ratio of the super junction groove can be reduced, and the difficulty of etching and filling the groove can be reduced.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a structural diagram of a conventional N-type super junction device;
fig. 2 is a structural diagram of an N-type superjunction device according to a first embodiment of the present invention;
FIG. 3 is a graph of the on-resistance versus temperature for a first embodiment device of the present invention and a prior art device;
FIG. 4A is a graph of specific on-resistance (Rsp) and Breakdown Voltage (BV) of the prior art device shown in FIG. 1 as a function of doping concentration of the N-type epitaxial layer;
FIG. 4B is a plot of specific on-resistance and breakdown voltage as a function of doping concentration for the N-type epitaxial layer for the device of the first embodiment of the present invention shown in FIG. 2;
fig. 5 is a structural diagram of an N-type superjunction device according to a second embodiment of the present invention;
fig. 6A to 6B are device structure diagrams in respective steps of the method for manufacturing an N-type superjunction device according to the first embodiment of the present invention.
Detailed Description
The first embodiment of the invention is an N-type super junction device:
as shown in fig. 2, which is a structural diagram of an N-type super junction device according to a first embodiment of the present invention, the N-type super junction device according to the embodiment of the present invention includes a super junction structure composed of a plurality of alternately arranged N-type columns 22 and P-type columns 32; each of the N-type pillars 22 and its adjacent P-type pillars 32 constitute one superjunction cell.
The P-type column 32 is composed of a P-type epitaxial layer filled in a super junction trench, the N-type column 22 is composed of an N-type epitaxial layer 2 located between the super junction trenches, and the N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1.
The super junction structure is arranged according to the process consistency of the device, and the consistency improvement is realized by improving the size distribution and the doping concentration distribution uniformity of the P-type column 32 of each super junction unit; under the condition that the super junction unit is ensured to be unchanged or reduced in stepping, the consistency is improved by increasing the top width of the P-type column 32 and setting the top width of the P-type column 32 to be larger than the top width of the N-type column 22; the larger the difference between the top width of the P-type column 32 and the top width of the N-type column 22 is, the lower the doping concentration of the P-type column 32 is under the condition of ensuring the charge balance of the super junction units, and the lower the doping concentration of the P-type column 32 is, which is more beneficial to the improvement of consistency; under the condition that the width of the top of the N-type column 22 is reduced, the on-resistance of the N-type column 22 is ensured or reduced by increasing the doping concentration of the N-type column 22, and the higher the doping concentration of the N-type column 22 is, the lower the temperature sensitivity of the on-resistance is, which is beneficial to increasing the temperature application range of the device. As shown in fig. 3, it is a graph of the on-resistance of the device according to the first embodiment of the present invention and the conventional device as a function of temperature; curve 101 is the curve of the on-resistance of the device according to the first embodiment of the present invention changing with temperature, and curve 102 is the curve of the on-resistance of the conventional device changing with temperature, and it can be seen that the rate of the increase of the on-resistance of the device according to the first embodiment of the present invention with temperature is smaller than that of the conventional device, so the on-resistance of the device according to the first embodiment of the present invention is lower at high temperature.
The optimal balance position between the P-type column 32 and the N-type column 22 of each super junction unit is arranged at the center position in the depth direction of the super junction unit, the doping concentration multiplied by the width of the P-type column 32 is equal to the doping concentration multiplied by the width of the N-type column 22 at the optimal balance position, and the arrangement of the optimal balance position ensures that the breakdown position of the N-type super junction device tends to the center area of the super junction structure.
In the depth direction, the doping concentration of the P-type column 32 varies within plus or minus 5% of the doping concentration at the optimum equilibrium position.
In the first embodiment of the present invention, the sides of the super junction trench are inclined to facilitate filling of the P-type epitaxial layer of the P-type column 32. For example: the side inclination angle of the super junction groove is larger than or equal to 88.6 degrees and smaller than 90 degrees.
In the first embodiment of the present invention, the P-type column 32 is filled in the super junction trench, and the inclination angle of the side surface of the super junction trench is the included angle between the side surface and the bottom surface of the corresponding adjacent N-type column 22, that is, the included angle between the side surface and the bottom surface of the N-type column 22; as can be seen from fig. 2, the side slope angle when the sides of the superjunction trench and the bottom surface of N-type pillar 22 are perpendicular is 90 degrees; when the inclination angle of the side surface of the super junction groove is smaller than 90 degrees, two bottom angles of the N-type column 22 are acute angles, two bottom angles of the P-type column 32 are obtuse angles, the top opening of the super junction groove is larger than the bottom opening, the smaller the inclination angle of the side surface is, and the larger the width difference between the top opening and the bottom opening of the super junction groove is. In the first embodiment of the present invention, the side surface inclination angle of the super junction trench is set to 88.6 degrees or more and less than 90 degrees, the side surface inclination angle of the super junction trench cannot be too small, if the side surface inclination angle is too small, the overall balance may be deteriorated, and the Breakdown Voltage (BV) may be lowered.
The N type super junction device is an N type super junction MOSFET, and further comprises: a gate structure, a P-type well 6, a source region 10, and a drain region 1. In the first embodiment of the invention, the semiconductor substrate 1 is a silicon substrate and is heavily doped in an N type, and the drain region 1 is directly formed after the back surface of the semiconductor substrate 1 is thinned; in other embodiments, the drain region 1 can also be formed by thinning the semiconductor substrate 1 and then performing backside ion implantation.
The P-type well 6 is formed on top of the P-type column 32 and extends to the top of the N-type column 22, and the surface of the P-type well 6 covered by the gate structure is used for forming a channel.
The source region 10 is formed in the P-well 6.
The drain region 1 is formed on the back surface of the super junction structure.
The source region 10 and the drain region 1 are both N + doped.
The grid structure is a planar grid structure and comprises a grid dielectric layer 8 and a polysilicon grid 9 which are sequentially formed on the surface of the P-type trap 6, and the polysilicon grid 9 covers the P-type trap 6 from the top of the P-type trap 6.
The P-type trap 6 at the top of the two adjacent P-type columns 32 is arranged at the same top of the N-type column 22, the P-type trap 6 is defined through a photoetching process, a JFET (junction field effect transistor) injection region 7 is formed in the distance between the two adjacent P-type traps 6, and the JFET injection region 7 is doped in an N type mode.
In addition, the front structure of the N-type super junction structure further comprises an interlayer film 11, a contact hole 12 and a front metal layer 14, wherein the front metal layer 14 is patterned to form a source electrode and a gate electrode. The source electrode is connected with the source region 10 and the P-type well 6 through a contact hole 12 corresponding to the bottom of the source region 10, and a P + doped well contact region 13 is formed at the bottom of the contact hole 12 at the top of the source region 10 and used for achieving good contact between the P-type well 6 and the contact hole 12.
A drain electrode composed of a back metal layer 15 is formed on the back surface of the drain region 1.
In other embodiments can also be: the grid structure is a trench grid structure and comprises a grid dielectric layer 8 and a polysilicon grid 9 which are sequentially formed in the grid trench, and the polysilicon grid 9 covers the P-type trap 6 from the side surface. The P-type well 6 is formed by full implantation, and the polysilicon gate 9 penetrates through the P-type well 6 in the longitudinal direction.
In order to more clearly illustrate the device of the first embodiment of the present invention, the structure of the device of the first embodiment of the present invention will be described with specific parameters:
the semiconductor substrate 1 has a resistivity of 0.001-0.003 ohm cm and a thickness of about 725 μm.
The angle of inclination of the super junction trench is 88.6 degrees, the depth is 40 micrometers, the top width is 5 micrometers, the pitch of the super junction trench, that is, the top width of the N-type column 22 is 4 micrometers, the width of the super junction cell is stepped to 9 micrometers, and the N-type impurity concentration is 3.75e15cm-3(ii) a The depth of the P-type well 6 is 2 micrometers, the center line of the super junction structure, i.e., the center position of the depth, is the middle position of the top surface of the super junction trench reduced by 2 micrometers, i.e., the depth of the P-type well 6, the center line is the optimal charge balance position, and the concentration of the P-type column at the center line can be calculated to be 4.75E15cm-3。
By way of comparison, the prior art device shown in fig. 1 takes the following parameters: the semiconductor substrate 1 has a resistivity of 0.001-0.003 ohm cm and a thickness of about 725 μm. The angle of inclination of the super junction trench is 88.6 degrees, the depth is 40 micrometers, the top width is 4 micrometers, the pitch of the super junction trench, that is, the top width of the N-type column 22 is 5 micrometers, the step of the super junction cell is 9 micrometers, the N-type impurity concentration is 3.15e15cm-3(ii) a The depth of the P-type well 6 is 2 microns, and the center line of the super junction structure, namely the center position of the depth is the super junction structureThe center line of the top surface of the junction trench is a position of optimum charge balance after the top surface is lowered by 2 μm, i.e., the depth of the P-type well 6, and the concentration of the P-type column 31 at the center line can be calculated to be 6.09E15cm-3。
Corresponding to the device of the first embodiment of the present invention and the existing device, after the P-type pillar is formed, a thermal annealing process is performed at 1100 ℃ for 60min, and Rsp simulation is performed respectively, so as to obtain:
as shown in fig. 4A, it is a curve of specific on-resistance (Rsp) and Breakdown Voltage (BV) of the conventional device shown in fig. 1 according to the doping concentration of the N-type epitaxial layer; curve 103 is a simulated curve of breakdown voltage and curve 104 is a simulated curve of Rsp. It can be seen that the doping concentration in the N-type epitaxial layer is 3e15cm-3When Rsp is 1.43ohm mm2BV is 763.49V.
As shown in fig. 4B, it is a curve of the specific on-resistance and breakdown voltage of the device of the first embodiment of the present invention shown in fig. 2 as a function of the doping concentration of the N-type epitaxial layer; curve 105 is a simulated curve of breakdown voltage and curve 106 is a simulated curve of Rsp. It can be seen that the doping concentration in the N-type epitaxial layer is 3.75e15cm-3When Rsp is 1.36ohm mm2BV is 769.17V.
As can be seen from a comparison between fig. 4A and fig. 4B, under the condition that the step of the superjunction unit is kept unchanged, the first embodiment of the present invention can achieve better retention and even reduction of Rsp while improving uniformity.
It can also be seen that while keeping Rsp the same, e.g. 1.2ohm mm2The breakdown voltage in the curve 103 is 712.64V, and the breakdown voltage in the curve 105 is 732.33V, so that the breakdown voltage of the first embodiment of the present invention can be improved.
In the invention, under the condition of ensuring that the steps of the super junction units are unchanged or reduced, the consistency is improved by increasing the width of the top of the P-type column 32 and setting the width of the top of the P-type column 32 to be larger than the width of the top of the N-type column 22; the principle of improving the process consistency by increasing the top width of the P-type is as follows: the larger the difference between the top width of P-type column 32 and the top width of N-type column 22 is, the lower the doping concentration of P-type column 32 is under the condition of ensuring the charge balance of each super junction unit, and the lower the doping concentration of P-type column 32 is, because the process deviations are generally managed in percentage, under the same process deviation, such as under the condition that the process deviates from 3%, the lower the doping concentration is, the smaller the actual variation of the doping concentration is, and the consistency of the super junction structure is determined according to the actual doping concentration deviations of P-type column 32 and N-type column 22, the lower the doping concentration of P-type column 32 is more favorable for consistency improvement.
In addition, in the first embodiment of the present invention, under the condition that the width of the top of the N-type column 22 is reduced, the on-resistance of the N-type column 22 is ensured or reduced by increasing the doping concentration of the N-type column 22, and the higher the doping concentration of the N-type column 22 is, the lower the temperature sensitivity of the on-resistance is, which is beneficial to increasing the temperature application range of the device, mainly beneficial to improving the characteristics of the device at high temperature, capable of reducing the on-resistance at high temperature, reducing loss, reducing junction temperature, and prolonging the service life of the device. To this end, the following is explained: in the design of a common device, the on-resistance at 25 ℃ is taken as a design target, but in the actual use of the device, because of the existence of switching loss and conduction loss, the actual working temperature of the device, namely the junction temperature, can generally reach 50-120 ℃, the junction temperature of the device can generally be guaranteed to be operable at-55 ℃ to +150 ℃, because the device is usually in a high-temperature state in the working process, the on-resistance of the device at high temperature is very important in practice, and by reducing the on-resistance at high temperature, the loss can be reduced, the junction temperature of the device can be reduced, and the service life of the device can be prolonged.
In addition, after the width of the P-type column is increased, the width of the super junction groove is also increased, so that the depth-to-width ratio of the super junction groove can be reduced, and the difficulty of etching and filling the groove can be reduced.
The second embodiment of the invention is an N-type super junction device:
as shown in fig. 5, it is a structural diagram of an N-type superjunction device according to a second embodiment of the present invention; the difference between the second embodiment N-type super junction device of the present invention and the first embodiment N-type super junction device of the present invention is that in the second embodiment of the present invention:
the N-type column of the super junction structure is represented by the mark 23 alone, the P-type column is represented by the mark 33 alone, and the side face of the super junction trench corresponding to the P-type column 33 is of a vertical structure, so that the breakdown voltage is conveniently improved.
The manufacturing method of the first embodiment of the invention for the N-type super junction device comprises the following steps:
as shown in fig. 6A to 6B, which are device structure diagrams in the steps of the method for manufacturing an N-type superjunction device according to the first embodiment of the present invention, in the method for manufacturing an N-type superjunction device according to the first embodiment of the present invention, the N-type superjunction device includes a superjunction structure formed of a plurality of alternately arranged N-type columns 22 and P-type columns 32; each of the N-type pillars 22 and its adjacent P-type pillars 32 constitute a super junction cell; the super junction structure is formed by the following steps:
step one, as shown in fig. 6A, a semiconductor substrate 1 is provided, and an N-type epitaxial layer 2 is formed on the surface of the semiconductor substrate 1.
Step two, as shown in fig. 6A, a hard mask layer 201 formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer is formed on the surface of the N-type epitaxial layer 2.
Step three, as shown in fig. 6A, defining a super junction trench forming region by lithography, and sequentially etching the hard mask layer 201 and the N-type epitaxial layer 2 to form the super junction trench. In the method according to the first embodiment of the present invention, the bottom of the super junction trench is located in the N-type epitaxial layer 2, and is spaced apart from the surface of the semiconductor substrate 1. And step four, as shown in fig. 6B, removing the third oxide layer and the second nitride layer and retaining the first oxide layer with the whole or partial thickness.
The sides of the super junction trench are sloped so that the filling of the P-type epitaxial layer of P-type column 32 in the super junction trench can be facilitated. In other embodiments, this can also be: the sides of the superjunction trench are vertical, which ultimately results in the second embodiment device of the present invention shown in fig. 5.
Step five, as shown in fig. 6B, filling a P-type epitaxial layer in the super junction trench by using an epitaxial growth process, wherein the P-type epitaxial layer also extends out of the super junction trench.
And sixthly, as shown in fig. 6B, removing the P-type epitaxial layer outside the super junction trench by adopting a chemical mechanical polishing process, and then removing the first oxide layer.
The P-type column 32 is composed of P-type epitaxial layers filled in super junction trenches, and the N-type column 22 is composed of N-type epitaxial layers 2 located between the super junction trenches. In fig. 6B, the position indicated by line AA is the bottom position of the super junction structure, and the position indicated by line BB is the top position of the super junction structure.
The super junction structure is arranged according to the process consistency of the device, and the consistency improvement is realized by improving the size distribution and the doping concentration distribution uniformity of the P-type column 32 of each super junction unit; under the condition that the super junction unit is ensured to be unchanged or reduced in stepping, the consistency is improved by increasing the top width of the P-type column 32 and setting the top width of the P-type column 32 to be larger than the top width of the N-type column 22; the larger the difference between the top width of the P-type column 32 and the top width of the N-type column 22 is, the lower the doping concentration of the P-type column 32 is under the condition of ensuring the charge balance of the super junction units, and the lower the doping concentration of the P-type column 32 is, which is more beneficial to the improvement of consistency; under the condition that the width of the top of the N-type column 22 is reduced, the on-resistance of the N-type column 22 is ensured or reduced by increasing the doping concentration of the N-type column 22, and the higher the doping concentration of the N-type column 22 is, the lower the temperature sensitivity of the on-resistance is, which is beneficial to increasing the temperature application range of the device.
The optimal balance position between the P-type column 32 and the N-type column 22 of each super junction unit is arranged at the center position in the depth direction of the super junction unit, the doping concentration multiplied by the width of the P-type column 32 is equal to the doping concentration multiplied by the width of the N-type column 22 at the optimal balance position, and the arrangement of the optimal balance position ensures that the breakdown position of the N-type super junction device tends to the center area of the super junction structure. In the first embodiment of the present invention, the optimum balance position needs to be subtracted below line BB after the subsequently formed P-well 6, i.e. the middle position between the top surface of P-well 6 and line AA.
In the depth direction, the doping concentration of the P-type column 32 varies within plus or minus 5% of the doping concentration at the optimum equilibrium position.
Then, as shown in fig. 2, the following front structure is formed, including:
forming a P-type well 6, forming a grid structure, a source region 10, an interlayer film 11, a contact hole 12 and a front metal layer 14, and patterning the front metal layer 14 to form a source electrode and a grid electrode.
The source electrode is connected with the source region 10 and the P-type well 6 through a contact hole 12 corresponding to the bottom of the source region 10, and a P + doped well contact region 13 is formed at the bottom of the contact hole 12 at the top of the source region 10 and used for achieving good contact between the P-type well 6 and the contact hole 12.
The P-type well 6 is formed on top of the P-type column 32 and extends to the top of the N-type column 22, and the surface of the P-type well 6 covered by the gate structure is used for forming a channel.
The source region 10 is formed in the P-well 6.
The grid structure is a planar grid structure and comprises a grid dielectric layer 8 and a polysilicon grid 9 which are sequentially formed on the surface of the P-type trap 6, and the polysilicon grid 9 covers the P-type trap 6 from the top of the P-type trap 6.
The P-type wells 6 on the tops of two adjacent P-type columns 32 have a distance at the top of the same N-type column 22, and the P-type wells 6 are defined through a photolithography process. The method further comprises the step of forming a JFET injection region 7 in the space between two adjacent P-type wells 6, wherein the JFET injection region 7 is doped in an N type mode.
The method also comprises the following back process:
and thinning the semiconductor substrate 1 and forming the drain region 1. The semiconductor substrate 1 is a silicon substrate and is N-type heavily doped, and the drain region 1 is directly formed after the back surface of the semiconductor substrate 1 is thinned; in other embodiments, the drain region 1 can also be formed by thinning the semiconductor substrate 1 and then performing backside ion implantation. The source region 10 and the drain region 1 are both N + doped.
A drain electrode composed of a back metal layer 15 is formed on the back surface of the drain region 1.
In other embodiments can also be: the grid structure is a trench grid structure and comprises a grid dielectric layer 8 and a polysilicon grid 9 which are sequentially formed in the grid trench, and the polysilicon grid 9 covers the P-type trap 6 from the side surface. The P-type well 6 is formed by full implantation, and the polysilicon gate 9 penetrates through the P-type well 6 in the longitudinal direction.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. An N type super junction device, characterized in that: the super junction structure comprises a super junction structure consisting of a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit;
the P-type column is composed of P-type epitaxial layers filled in the super-junction grooves, the N-type column is composed of N-type epitaxial layers located between the super-junction grooves, and the N-type epitaxial layers are formed on the surface of the semiconductor substrate;
the super junction structure is arranged according to the process consistency of the device, and the consistency improvement is realized by improving the size distribution and the doping concentration distribution uniformity of the P-type column of each super junction unit; under the condition that the super junction unit is guaranteed to be unchanged or reduced in stepping, the top width of the P-type column is increased and is set to be larger than that of the N-type column, so that consistency is improved; the larger the difference between the width of the top of the P-type column and the width of the top of the N-type column is, the lower the doping concentration of the P-type column is under the condition of ensuring the charge balance of the super junction units, and the lower the doping concentration of the P-type column is, the more the consistency is improved; under the condition that the width of the top of the N-type column is reduced, the on-resistance of the N-type column is ensured or reduced by improving the doping concentration of the N-type column, and the higher the doping concentration of the N-type column is, the lower the temperature sensitivity of the on-resistance is, so that the temperature application range of the device is favorably increased.
2. The N-type superjunction device of claim 1, wherein: the optimal balance position between the P-type column and the N-type column of each super junction unit is arranged at the center position of the super junction unit in the depth direction, the doping concentration multiplied by the width of the P-type column is equal to the doping concentration multiplied by the width of the N-type column at the optimal balance position, and the arrangement of the optimal balance position ensures that the breakdown position of the N-type super junction device approaches to the center area of the super junction structure.
3. The N-type superjunction device of claim 2, wherein: in the depth direction, the doping concentration of the P-type column is within plus or minus 5% of the doping concentration at the optimal equilibrium position.
4. The N-type superjunction device of claim 1, wherein: the side face of the super junction groove is inclined so as to facilitate filling of the P-type epitaxial layer of the P-type column.
5. The N-type superjunction device of claim 4, wherein: the side inclination angle of the super junction groove is larger than or equal to 88.6 degrees and smaller than 90 degrees.
6. The N-type superjunction device of claim 1, wherein: the side surface of the super junction groove is vertical, so that the breakdown voltage is conveniently improved.
7. The N-type superjunction device of claim 1, wherein the N-type superjunction device is an N-type superjunction MOSFET, further comprising: the transistor comprises a grid structure, a P-type well, a source region and a drain region;
the P-type well is formed at the top of the P-type column and extends to the top of the N-type column, and the surface of the P-type well covered by the gate structure is used for forming a channel;
the source region is formed in the P-type well;
the drain region is formed on the back of the super junction structure.
8. The N-type superjunction device of claim 7, wherein: the grid structure is a planar grid structure and comprises a grid dielectric layer and a polysilicon grid which are sequentially formed on the surface of the P-type trap, and the polysilicon grid covers the P-type trap from the top of the P-type trap.
9. The N-type superjunction device of claim 8, wherein: the P-type trap at the top of two adjacent P-type columns has a distance at the top of the same N-type column, the P-type trap is defined through a photoetching process, and JFET injection regions are formed in the distance between the two adjacent P-type traps.
10. The N-type superjunction device of claim 7, wherein: the grid structure is a groove grid structure and comprises a grid dielectric layer and a polysilicon grid which are sequentially formed in the grid groove, and the polysilicon grid covers the P-type trap from the side surface.
11. The N-type superjunction device of claim 10, wherein: the P-type well is formed by full implantation, and the polysilicon gate penetrates through the P-type well in the longitudinal direction.
12. The manufacturing method of the N-type super junction device is characterized in that the N-type super junction device comprises a super junction structure formed by a plurality of alternately arranged N-type columns and P-type columns; each N-type column and the adjacent P-type column form a super junction unit; the super junction structure is formed by the following steps:
providing a semiconductor substrate, and forming an N-type epitaxial layer on the surface of the semiconductor substrate;
secondly, forming a hard mask layer formed by overlapping a first oxide layer, a second nitride layer and a third oxide layer on the surface of the N-type epitaxial layer;
step three, defining a forming area of a super junction groove by photoetching, and etching the hard mask layer and the N-type epitaxial layer in sequence to form the super junction groove;
step four, removing the third oxide layer and the second nitride layer and retaining the first oxide layer with the whole or partial thickness;
filling a P-type epitaxial layer in the super junction groove by adopting an epitaxial growth process, wherein the P-type epitaxial layer also extends out of the super junction groove;
removing the P-type epitaxial layer outside the super junction groove by adopting a chemical mechanical polishing process, and then removing the first oxidation layer;
the P-type column is formed by P-type epitaxial layers filled in the super junction grooves, and the N-type column is formed by N-type epitaxial layers positioned between the super junction grooves;
the super junction structure is arranged according to the process consistency of the device, and the consistency improvement is realized by improving the size distribution and the doping concentration distribution uniformity of the P-type column of each super junction unit; under the condition that the super junction unit is guaranteed to be unchanged or reduced in stepping, the top width of the P-type column is increased and is set to be larger than that of the N-type column, so that consistency is improved; the larger the difference between the width of the top of the P-type column and the width of the top of the N-type column is, the lower the doping concentration of the P-type column is under the condition of ensuring the charge balance of the super junction units, and the lower the doping concentration of the P-type column is, the more the consistency is improved; under the condition that the width of the top of the N-type column is reduced, the on-resistance of the N-type column is ensured or reduced by improving the doping concentration of the N-type column, and the higher the doping concentration of the N-type column is, the lower the temperature sensitivity of the on-resistance is, so that the temperature application range of the device is favorably increased.
13. The method of manufacturing an N-type superjunction device of claim 12, wherein: the optimal balance position between the P-type column and the N-type column of each super junction unit is arranged at the center position of the super junction unit in the depth direction, the doping concentration multiplied by the width of the P-type column is equal to the doping concentration multiplied by the width of the N-type column at the optimal balance position, and the arrangement of the optimal balance position ensures that the breakdown position of the N-type super junction device approaches to the center area of the super junction structure.
14. The method of manufacturing an N-type superjunction device of claim 13, wherein: in the depth direction, the doping concentration of the P-type column is within plus or minus 5% of the doping concentration at the optimal equilibrium position.
15. The method of manufacturing an N-type superjunction device of claim 12, wherein: the side face of the super junction groove is inclined so as to facilitate the filling of the P-type epitaxial layer of the P-type column;
or the side surface of the super junction groove is vertical, so that the breakdown voltage is conveniently improved.
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| JP2004072068A (en) * | 2002-06-14 | 2004-03-04 | Fuji Electric Holdings Co Ltd | Semiconductor device |
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