CN112768522A - Super junction device and manufacturing method thereof - Google Patents

Super junction device and manufacturing method thereof Download PDF

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Publication number
CN112768522A
CN112768522A CN201911058984.8A CN201911058984A CN112768522A CN 112768522 A CN112768522 A CN 112768522A CN 201911058984 A CN201911058984 A CN 201911058984A CN 112768522 A CN112768522 A CN 112768522A
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type
super junction
epitaxial layer
type column
column
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肖胜安
曾大杰
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Nantong Shangyangtong Integrated Circuit Co ltd
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Nantong Shangyangtong Integrated Circuit Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

The invention discloses a super junction device, wherein a super junction structure is formed above the surface of a first N-type epitaxial layer, the width of a P-type column on the top position of a super junction unit is smaller than that of an N-type column, and the step is constant; the N-type column consists of second N-type epitaxial layers filled in the grooves, the P-type column consists of first P-type epitaxial layers between the grooves, and the first P-type epitaxial layers are formed on the first N-type epitaxial layers; the groove penetrates through the first P-type epitaxial layer, and the bottom of the groove is in contact with the first N-type epitaxial layer; the total amount of P-type impurities of a P-type column in the super junction unit is matched with the total amount of N-type impurities of an N-type column, and the doping concentration of the P-type column is higher than that of the N-type column. The invention also discloses a manufacturing method of the super junction device. The invention can reduce the difficulty of process control and improve the consistency of devices; when the groove is inclined, the high-temperature on-resistance of the device can be reduced, the PN impurity difference between the top and the bottom of the super junction unit is reduced, and the breakdown voltage of the device is improved.

Description

Super junction device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction (junction) device; the invention also relates to a manufacturing method of the super junction device.
Background
A super junction (super junction) structure is a structure of N-type columns and P-type columns, i.e., PN columns, which are alternately arranged. If a super-junction structure is used to replace an N-type drift region in a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device, a conduction path is provided in a conduction state (only an N-type column provides a path, and a P-type column does not provide), and a reverse bias voltage is borne in an off state (P N columns bear together), so that a super-junction Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) is formed. The super-junction MOSFET can greatly reduce the on-resistance of the device by using an epitaxial layer with low resistivity under the condition that the reverse breakdown voltage is consistent with that of a traditional VDMOS device.
The method for manufacturing the super junction is capable of being produced in batch and comprises the steps of forming a groove in an N-type epitaxial layer, filling a P-type epitaxial layer in the groove, and forming PN columns which are arranged alternately.
In the prior art, in order to obtain a lower specific on-resistance, the width of the N-type pillar of the PN pillar is generally designed to be greater than or equal to the width of the P-type pillar, so as to ensure that the area of the N-type region is increased and the specific on-resistance of the device is reduced, for example, in the current practical use, the width of the P-type pillar and the width of the N-type pillar are 5 micrometers/12 micrometers, 5 micrometers/8 micrometers, 5 micrometers/6 micrometers, 4 micrometers/5 micrometers, and 2 micrometers/3 micrometers, where the number before "/" indicates the width of the P-type pillar and the number after "/" indicates the width of the N-type pillar. However, in this way, in the manufacturing process, especially in the trench process, since the width of the P-pillar is small, the difficulty of process control is increased, and the concentration of the filling impurity is increased, and because the absolute value of the concentration is increased, the total amount of the impurity is changed greatly due to the process change of the same percentage, the degree of charge imbalance is serious, and the deviation of the device performance, including the deviation of the breakdown voltage, is large, which affects the uniformity of the device.
Disclosure of Invention
The invention aims to provide a super junction device, which can reduce the process control difficulty and improve the consistency of the device. Therefore, the invention also provides a manufacturing method of the super junction device.
In order to solve the technical problem, the super junction device provided by the invention comprises a super junction structure formed by alternately arranging P-type columns and N-type columns; the super junction device is an N-type device and is formed on the super junction structure; one P-type column and one adjacent N-type column form a super junction unit.
The super junction structure is formed above the surface of a first N-type epitaxial layer, the first N-type epitaxial layer is formed on an N-type high-concentration doped semiconductor substrate, and the first N-type epitaxial layer is used as a buffer layer at the bottom of the super junction structure.
The width of the P-type column at the top position of the super junction unit is smaller than that of the N-type column, and the widths of the P-type column and the N-type column and the step (pitch) of the super junction unit are not changed, so that the volume of the N-type column is increased, and the specific on-resistance of the super junction device is reduced.
The N-type column with the larger top width of the super junction unit is composed of a second N-type epitaxial layer filled in the grooves, the P-type column with the smaller top width of the super junction unit is composed of a first P-type epitaxial layer between the grooves, and the first P-type epitaxial layer is formed on the first N-type epitaxial layer; the trench penetrates through the first P-type epitaxial layer and the bottom of the trench is in contact with the first N-type epitaxial layer.
The total amount of P-type impurities of the P-type column in the super junction unit is matched with the total amount of N-type impurities of the N-type column, and the doping concentration of the P-type column is higher than that of the N-type column.
The top opening of the groove is arranged according to the top width of the N-type column with the larger top width of the super junction unit and is defined through photoetching so as to reduce the height-to-width ratio of the groove; the doping concentration of the second N-type epitaxial layer filling the groove is set according to the doping concentration of the N-type column with the lower doping concentration of the super junction unit so as to reduce the change of the impurity amount of the epitaxial filling process of the groove.
In a further improvement, the super junction device comprises a plurality of super junction device units, and each super junction device unit is formed on the corresponding super junction unit.
The superjunction device unit comprises a P-type body region formed at the top of the P-type column and extending into the N-type column.
The further improvement is that the thickness of the first N-type epitaxial layer is 5-20 microns, and the body diode characteristic of the device is adjusted through the thickness of the first N-type epitaxial layer, so that the thicker the thickness of the first N-type epitaxial layer is, the better the body diode characteristic of the device is.
In a further improvement, the side surface of the groove is in a vertical structure; the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.
The further improvement is that the side of the groove is in an inclined structure, the width of the top of the N-type column is larger than that of the bottom of the N-type column, and the width of the top of the P-type column is smaller than that of the bottom of the P-type column.
The structure that the width of the N-type column is gradually reduced from the top to the bottom enables the volume of the N-type column to be reduced and the doping concentration of the N-type column to be improved under the condition that the step of the super junction unit is not changed and the total amount of N-type doping is not changed, so that the high-temperature on-resistance of the super junction device is reduced.
The further improvement is that the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped;
the doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer enable the P-type impurity amount of the P-type column and the N-type impurity amount of the N-type column at the middle position of the super junction unit at the bottom of the P-type well in depth to form optimal matching;
the P-type impurity amount of the P-type column at each position above the middle position of the super junction unit in depth is less than the N-type impurity amount of the N-type column;
the P-type impurity amount of the P-type column at each position above the middle position of the super junction unit in depth is larger than the N-type impurity amount of the N-type column.
In a further improvement, the first N-type epitaxial layer simultaneously forms a compensation structure for depleting P-type impurities of the P-type column from the bottom so as to compensate the influence of the fact that the P-type impurity amount of the P-type column at the bottom of the super junction unit is larger than the N-type impurity amount of the N-type column on breakdown voltage reduction.
And the P-type body region simultaneously forms a compensation structure for depleting N-type impurities of the N-type column from the top so as to compensate the influence of the fact that the P-type impurity amount of the P-type column at the top of the super junction unit is smaller than the N-type impurity amount of the N-type column on the reduction of breakdown voltage.
In order to solve the technical problem, the invention provides a manufacturing method of a super junction device, wherein the super junction device is an N-type device and is formed on a super junction structure; the super junction structure is formed by alternately arranging P-type columns and N-type columns, and one P-type column and one adjacent N-type column form a super junction unit; the width of the P-type column at the top position of the super junction unit is smaller than that of the N-type column, and the width of the P-type column and the width of the N-type column are not changed, so that the volume of the N-type column is increased, and the specific on-resistance of the super junction device is reduced; manufacturing the super junction structure by adopting the following steps:
providing an N-type high-concentration doped semiconductor substrate, and forming a first N-type epitaxial layer on the semiconductor substrate; the first N-type epitaxial layer is used as a buffer layer at the bottom of the super junction structure.
And secondly, forming a first P-type epitaxial layer on the surface of the first N-type epitaxial layer.
And thirdly, forming a groove in the first P-type epitaxial layer by adopting a photoetching definition and etching process, wherein the groove penetrates through the first P-type epitaxial layer, and the bottom of the groove is in contact with the first N-type epitaxial layer.
And the top opening of the groove is arranged according to the width of the top of the N-type column with the larger width of the top of the super junction unit, so that the aspect ratio of the groove can be reduced.
And fourthly, filling a second N-type epitaxial layer in the groove, wherein the N-type column is composed of the second N-type epitaxial layer filled in the groove, and the P-type column is composed of the first P-type epitaxial layer between the grooves.
The total amount of P-type impurities of the P-type column in the super junction unit is matched with the total amount of N-type impurities of the N-type column, and the doping concentration of the P-type column is lower than that of the N-type column; the doping concentration of the second N-type epitaxial layer filling the groove is set according to the doping concentration of the N-type column with the lower doping concentration of the super junction unit so as to reduce the change of the impurity amount of the epitaxial filling process of the groove.
The further improvement is that in the third step, before the photoetching definition, a step of forming a hard mask layer on the surface of the first P-type epitaxial layer is also included, the hard mask layer is etched firstly in the etching process, then the first P-type epitaxial layer is etched, and the hard mask layer with partial thickness is removed after the etching of the third step is finished; in the fourth step, an epitaxial growth process of the second N-type epitaxial layer is performed first, and the second N-type epitaxial layer after the growth is completed further extends to the outer surface of the trench; and then removing the second N-type epitaxial layer on the outer surface of the groove by adopting a chemical mechanical polishing process, and then removing the residual hard mask layer.
In a further improvement, the super junction device comprises a plurality of super junction device units, and each super junction device unit is formed on the corresponding super junction unit; after the super junction structure is formed, the method further comprises the following steps:
forming a P-type body region formed at the top of the P-type pillar and extending into the N-type pillar;
forming a grid structure, a source region, an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a grid and a source;
and thinning the back of the semiconductor substrate, forming a drain region on the back of the semiconductor substrate, and forming a back metal layer on the back of the drain region.
The further improvement is that the thickness of the first N-type epitaxial layer is 5-20 microns, and the body diode characteristic of the device is adjusted through the thickness of the first N-type epitaxial layer, so that the thicker the thickness of the first N-type epitaxial layer is, the better the body diode characteristic of the device is.
In a further improvement, the side surface of the groove is in a vertical structure; the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.
The further improvement is that the side of the groove is in an inclined structure, the width of the top of the N-type column is larger than that of the bottom of the N-type column, and the width of the top of the P-type column is smaller than that of the bottom of the P-type column.
The structure that the width of the N-type column is gradually reduced from the top to the bottom enables the volume of the N-type column to be reduced and the doping concentration of the N-type column to be improved under the condition that the super-junction unit is not stepped and the total amount of N-type doping is not changed, so that the high-temperature on-resistance of the super-junction device is reduced.
The further improvement is that the first P-type epitaxial layer is uniformly doped and the second N-type epitaxial layer is uniformly doped.
The doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer enable the P-type impurity amount of the P-type column and the N-type impurity amount of the N-type column at the middle position of the super junction unit located at the bottom of the P-type trap in the depth to form the best matching.
The P-type impurity amount of the P-type column at each position above the middle position of the super junction unit in depth is less than the N-type impurity amount of the N-type column.
The P-type impurity amount of the P-type column at each position above the middle position of the super junction unit in depth is larger than the N-type impurity amount of the N-type column.
In a further improvement, the first N-type epitaxial layer simultaneously forms a compensation structure for depleting P-type impurities of the P-type column from the bottom so as to compensate the influence of the fact that the P-type impurity amount of the P-type column at the bottom of the super junction unit is larger than the N-type impurity amount of the N-type column on breakdown voltage reduction.
And the P-type body region simultaneously forms a compensation structure for depleting N-type impurities of the N-type column from the top so as to compensate the influence of the fact that the P-type impurity amount of the P-type column at the top of the super junction unit is smaller than the N-type impurity amount of the N-type column on the reduction of breakdown voltage.
The super-junction structure is specially set from the overall structure of the super-junction device, and the volume of the N-type column is increased under the condition that the stepping of the super-junction unit, namely the width of the P-type column and the width of the N-type column are unchanged according to the requirement of the N-type device, so that the specific on-resistance of the super-junction device is reduced; on the basis, the invention selects the top width of the N-type column with larger width as the top opening width of the groove, and sets the N-type column to be composed of the N-type epitaxial layer filled in the groove, namely the second N-type epitaxial layer, and the epitaxial layer formed by the groove is the P-type epitaxial layer, namely the first P-type epitaxial layer.
Because the width of the P-type column on the top position of the super junction unit is smaller than the width of the N-type column, and the volume of the N-type column is larger than the volume of the P-type column, the invention also utilizes the characteristic that the doping concentration of the N-type column is lower than the doping concentration of the P-type column when the super junction unit is in charge matching and the volume of the N-type column is larger than the volume of the P-type column, and adopts the process of filling the groove with the second N-type epitaxial layer to realize the N-type column, compared with the technical scheme of filling the groove with the P-type epitaxial layer to form the P-type column in the prior art, the invention can reduce the doping concentration of the epitaxial layer filling the groove, and because the deviation of the doping concentration of the epitaxial layer in the groove filling process is changed according to the deviation of percentage, the invention can reduce the doping concentration of the groove filling the epitaxial layer and further reduce the deviation of the, therefore, the charge imbalance of the super junction unit can be reduced, the performance of the device such as the deviation of breakdown voltage can be reduced, and finally the consistency of the device can be improved.
In addition, the groove usually has a certain inclination angle, namely the side surface of the groove is in an inclined structure, so that the etching, cleaning and filling of the groove are facilitated; meanwhile, when the groove with the side surface inclined structure is applied to the N-type column, the width of the top of the N-type column, namely the width of the top opening of the groove, is directly defined by photoetching, and the width of the N-type column from the top to the bottom is gradually reduced, so that compared with the N-type column formed by an N-type epitaxial layer between the grooves in the prior art, the N-type column has the advantages that the volume of the N-type column is reduced under the condition that the widths of the tops of the N-type column and the N-type column are the same, and the doping concentration of the N-type column is higher under the condition that the total doping amount of the N-type column and the N-type column is consistent, so that compared with the N-type column in the prior art, the N-type column with; in actual use, due to the switching loss and the conduction loss, the actual working temperature of the device is not room temperature but can reach 50-120 ℃, and the invention can reduce the loss of the device, reduce the junction temperature of the device and prolong the service life of the device after reducing the on-resistance of the device at high temperature.
In addition, when the trench is inclined, compared with the conventional super junction structure in which the P-type column is formed by trench filling under the condition that the widths of the tops of the N-type column and the P-type column are kept unchanged, the N-type column of the invention has a smaller volume and a gradually smaller width from the top to the bottom, while the P-type column has an increased volume and a gradually increased width from the top to the bottom, under the condition that the total doping amount of the N-type column of the super-junction unit, namely the total doping amount of the P-type column is kept unchanged, compared with the existing structure, the super-junction unit can increase the doping concentration of the N-type column and simultaneously reduce the doping concentration of the P-type column, and combined with the width change of the N-type column and the P-type column, compared with the existing structure, the super-junction unit can simultaneously reduce the difference of the impurity amount between the P-type column and the N-type column at the top and the bottom of the super-junction unit, the invention can improve the charge matching between the P-type column and the N-type column of the super junction unit at the top and bottom positions.
Meanwhile, the P-type impurity amount of the P-type column at the bottom of the super-junction unit is larger than the N-type impurity amount of the N-type column, and the first N-type epitaxial layer is arranged at the bottom of the super-junction structure, so that more P-type impurities in the P-type column can be exhausted from the bottom through the first N-type epitaxial layer, the influence of the P-type impurity amount of the P-type column at the bottom of the super-junction unit larger than the N-type impurity amount of the N-type column on the reduction of the breakdown voltage can be compensated, and the breakdown voltage of the device is finally improved; on the contrary, in the existing structure, since the P-type impurity amount of the P-type column at the bottom position of the super junction unit is less than the N-type impurity amount of the N-type column, similar compensation of the invention cannot be performed through the N-type epitaxial layer arranged at the bottom, and certainly, the breakdown voltage of the device cannot be improved.
Meanwhile, the P-type impurity amount of the P-type column at the bottom of the super-junction unit is smaller than the N-type impurity amount of the N-type column, and because a P-type body area is usually formed at the top of the super-junction structure, the P-type body area can be used up from more than N-type impurities at the top of the N-type column, so that the influence of the P-type impurity amount of the P-type column at the top of the super-junction unit being smaller than the N-type impurity amount of the N-type column on the reduction of the breakdown voltage can be compensated, and the breakdown voltage of the device is finally improved; on the contrary, in the existing structure, the P-type impurity amount of the P-type column at the top position of the super junction unit is larger than the N-type impurity amount of the N-type column, so that similar compensation of the invention cannot be performed through the P-type body region, and certainly, the breakdown voltage of the device cannot be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic structural diagram of a conventional superjunction device;
fig. 2 is a schematic structural diagram of a super junction device according to a first embodiment of the present invention;
fig. 3A to 3B are schematic device structure diagrams in the steps of forming a super junction structure of the method of manufacturing a super junction device according to the first embodiment of the present invention;
fig. 4 is a graph of the on-resistance of the superjunction device of the first embodiment of the present invention and the existing superjunction device as a function of temperature;
fig. 5 is a distribution curve of electric field intensity in the longitudinal direction in the superjunction unit of the superjunction device of the first embodiment of the present invention and the existing superjunction device.
Detailed Description
The existing super junction device:
for comparison with the superjunction device of the first embodiment of the present invention, a superjunction device of the prior art is introduced, and as shown in fig. 1, the superjunction device of the prior art is schematically illustrated in structure; the existing super junction device comprises a super junction structure formed by alternately arranging P-type columns 103 and N-type columns 101; the super junction device is an N-type device and is formed on the super junction structure; one P-type column 103 and an adjacent N-type column 101 constitute a super junction unit.
In the prior art, the P-type column 103 is composed of a P-type epitaxial layer filled in the trench 102. N-type pillars 101 are comprised of N-type epitaxial layer 101 between trenches 102. Trenches 102 are located in N-type epitaxial layer 101 and N-type epitaxial layer 101 at the bottom of trenches 102 serves as a buffer layer.
The N-type epitaxial layer 101 is formed on an N-type highly doped semiconductor substrate 10.
The width of the P-type column 103 at the top position of the super junction unit is smaller than the width of the N-type column 101 and the sum of the widths of the P-type column 103 and the N-type column 101 is unchanged, so as to increase the volume of the N-type column 101 and thereby reduce the specific on-resistance of the super junction device.
The super junction device comprises a plurality of super junction device units, and each super junction device unit is formed on the corresponding super junction unit.
The super junction device unit comprises a P-type body region 1, wherein the P-type body region 1 is formed on the top of the P-type column 103 and extends into the N-type column 101.
Further comprising: the structure comprises a grid structure, a source region 4, an interlayer film 7, a contact hole 8 and a front metal layer 9, wherein the front metal layer 9 is patterned to form a grid and a source.
In fig. 1, the gate structure is a planar gate, and is formed by stacking a gate dielectric layer, such as a gate oxide layer 2, and a polysilicon gate 3. Can also be: the grid structure is a trench grid.
The drain region is composed of the semiconductor substrate 10 with the back surface thinned. Can also be: the drain region is composed of an N + ion implantation region formed in the semiconductor substrate 10 after the back surface is thinned.
And forming a back metal layer 11 on the back of the drain region. The drain is constituted by the back metal layer 11.
Typically, a contact region 5 consisting of a P + region is formed on top of the contact hole 8 on top of the source region 4.
The surface of the body region 1 covered by the polysilicon gate 3 is used to form a channel. In order to reduce the on-resistance of the top region of the N-type pillar 101 between two adjacent body regions 1, a JFET implant region 6 is also typically formed.
The first embodiment of the invention is a super junction device:
as shown in fig. 2, it is a schematic structural diagram of a super junction device according to a first embodiment of the present invention; the super junction device of the first embodiment of the invention comprises a super junction structure formed by alternately arranging P-type columns 202 and N-type columns 204; the super junction device is an N-type device and is formed on the super junction structure; one P-type column 202 and an adjacent N-type column 204 form a super junction cell.
The super junction structure is formed above the surface of a first N-type epitaxial layer 201, the first N-type epitaxial layer 201 is formed on an N-type high-concentration doped semiconductor substrate 10, and the first N-type epitaxial layer 201 serves as a buffer layer at the bottom of the super junction structure. The semiconductor substrate 10 includes a silicon substrate.
The width of the P-type column 202 at the top position of the superjunction unit is smaller than the width of the N-type column 204 and the sum of the widths of the P-type column 202 and the N-type column 204 is unchanged to increase the volume of the N-type column 204 to reduce the specific on-resistance of the superjunction device.
The N-type column 204 with the larger top width of the super junction unit is composed of a second N-type epitaxial layer filled in the trenches 203, the P-type column 202 with the smaller top width of the super junction unit is composed of a first P-type epitaxial layer between the trenches 203, and the first P-type epitaxial layer is formed on the first N-type epitaxial layer 201; the trench 203 passes through the first P-type epitaxial layer and is in contact with the first N-type epitaxial layer 201 at the bottom.
The total amount of P-type impurities of the P-type column 202 and the total amount of N-type impurities of the N-type column 204 in the super junction unit are matched, and the doping concentration of the P-type column 202 is higher than that of the N-type column 204.
The top opening of the trench 203 is set according to the top width of the N-type column 204 with the larger top width of the super junction unit and is defined through lithography, so as to reduce the aspect ratio of the trench 203; the doping concentration of the second N-type epitaxial layer filling the trench 203 is set according to the doping concentration of the N-type column 204 with the lower doping concentration of the super junction unit so as to reduce the variation of the impurity amount of the epitaxial filling process of the trench 203.
The super junction device comprises a plurality of super junction device units, and each super junction device unit is formed on the corresponding super junction unit.
The superjunction device unit comprises a P-type body region 1, wherein the P-type body region 1 is formed on the top of the P-type column 202 and extends into the N-type column 204.
Further comprising: the structure comprises a grid structure, a source region 4, an interlayer film 7, a contact hole 8 and a front metal layer 9, wherein the front metal layer 9 is patterned to form a grid and a source.
In fig. 2, the gate structure is a planar gate, and is formed by stacking a gate dielectric layer, such as a gate oxide layer 2, and a polysilicon gate 3. In other embodiments can also be: the grid structure is a trench grid.
The drain region is composed of the semiconductor substrate 10 with the back surface thinned. In other embodiments, this can also be: the drain region is composed of an N + ion implantation region formed in the semiconductor substrate 10 after the back surface is thinned.
And forming a back metal layer 11 on the back of the drain region. The drain is constituted by the back metal layer 11.
Typically, a contact region 5 consisting of a P + region is formed on top of the contact hole 8 on top of the source region 4.
The surface of the body region 1 covered by the polysilicon gate 3 is used to form a channel. In order to reduce the on-resistance of the top region of the N-type pillar 204 between two adjacent body regions 1, a JFET implant region 6 is also typically formed.
In the first embodiment of the present invention, the thickness of the first N-type epitaxial layer 201 is 5 micrometers to 20 micrometers, and the body diode characteristic of the device is adjusted by the thickness of the first N-type epitaxial layer 201, and the thicker the thickness of the first N-type epitaxial layer 201 is, the better the body diode characteristic of the device is. The body diode is a parasitic diode formed between the body region 1 and a drift region, and the drift region is formed by the N-type column 204 and the first N-type epitaxial layer 201 together.
The side of the trench 203 is in an inclined structure, the top width of the N-type pillar 204 is greater than the bottom width, and the top width of the P-type pillar 202 is less than the bottom width.
The structure that the width of N-type column 204 gradually decreases from top to bottom reduces the volume of N-type column 204 and increases the doping concentration of N-type column 204 under the condition that the super junction unit is not stepped and the total amount of N-type doping is not changed, so as to reduce the high-temperature on-resistance of the super junction device.
The first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.
The doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer enable the P-type impurity amount of the P-type column 202 and the N-type impurity amount of the N-type column 204 at the middle position of the super junction unit at the bottom of the P-type well in depth to form optimal matching.
The P-type impurity amount of the P-type column 202 at each position above the middle position in depth of the super junction unit is smaller than the N-type impurity amount of the N-type column 204.
The P-type impurity amount of the P-type column 202 at each position above the middle position in depth of the super junction unit is larger than the N-type impurity amount of the N-type column 204.
The first N-type epitaxial layer 201 simultaneously forms a compensation structure for depleting P-type impurities of the P-type columns 202 from the bottom, so as to compensate the influence of the fact that the P-type impurity amount of the P-type columns 202 at the bottom of the super junction unit is larger than the N-type impurity amount of the N-type columns 204 on breakdown voltage reduction.
The P-type body region 1 simultaneously forms a compensation structure for depleting the N-type impurities of the N-type column 204 from the top, so as to compensate the influence of the fact that the P-type impurity amount of the P-type column 202 at the top of the super junction unit is smaller than the N-type impurity amount of the N-type column 204 on the reduction of the breakdown voltage.
The embodiment of the invention particularly sets the super junction structure from the overall structure of the super junction device, and increases the volume of the N-type column 204 under the condition that the stepping of the super junction unit, namely the width and the keeping of the P-type column 202 and the N-type column 204 are unchanged according to the requirement of the N-type device, so that the specific on-resistance of the super junction device is reduced; on this basis, in the embodiment of the present invention, the top width of the N-type pillar 204 with a larger width is selected as the width of the top opening of the trench 203, and the N-type pillar 204 is configured to be composed of the N-type epitaxial layer filled in the trench 203, i.e., the second N-type epitaxial layer, and the epitaxial layer formed by the trench 203 is the P-type epitaxial layer, i.e., the first P-type epitaxial layer, because the width of the top opening of the trench 203 is increased, the aspect ratio of the trench 203 is reduced, thereby reducing the process control difficulty, including reducing the control difficulty of the etching, cleaning and filling processes of the trench 203.
In the embodiment of the invention, because the width of the P-type column 202 on the top position of the super junction unit is smaller than the width of the N-type column 204, that is, the volume of the N-type column 204 is larger than the volume of the P-type column 202, and the embodiment of the invention also utilizes the characteristic that the doping concentration of the N-type column 204 is lower than the doping concentration of the P-type column 202 when the charge of the super junction unit is matched and the volume of the N-type column 204 is larger than the volume of the P-type column 202, the process of filling the trench 203 with the second N-type epitaxial layer is adopted to realize the N-type column 204, compared with the technical scheme of filling the trench 203 with the P-type epitaxial layer to form the P-type column 202 in the prior art, the embodiment of the invention can reduce the doping concentration of the epitaxial layer filling the trench 203, and because the offset of the doping concentration of the epitaxial layer in the process of filling the trench 203 is changed according to the percentage offset, the embodiment of the invention can reduce the doping concentration of the Therefore, the charge unbalance of the super junction unit can be reduced, the performance of the device such as the deviation of breakdown voltage can be reduced, and finally the consistency of the device can be improved.
In addition, the trench 203 usually has a certain inclination angle, that is, the side surface of the trench 203 is in an inclined structure, which is more beneficial to etching, cleaning and filling the trench 203; meanwhile, when the trench 203 with the side surface inclined structure is applied to the N-type column 204 in the embodiment of the present invention, since the top width of the N-type column 204, that is, the top opening width of the trench 203, is directly defined by photolithography, and the width of the N-type column 204 from the top to the bottom is gradually reduced, compared with the N-type column 204 composed of the N-type epitaxial layer between the trenches 203 in the prior art, the N-type column 204 in the embodiment of the present invention has a smaller volume under the condition that the top widths are the same, and meanwhile, the N-type column 204 in the embodiment of the present invention has a higher doping concentration under the condition that the total doping amount of the two is consistent, compared with the N-type column 204 in the prior art, the N-type column 204 with the higher doping concentration in the embodiment of the present invention can reduce the high temperature on resistance of the super junction device; however, in practical use, due to the switching loss and the conduction loss, the actual working temperature of the device is not room temperature, but can reach 50-120 ℃, and after the on-resistance of the device at high temperature is reduced, the loss of the device can be reduced, the junction temperature of the device can be reduced, and the service life of the device can be prolonged.
In addition, when trench 203 is tilted, since the volume of N-type column 204 is reduced and the width is gradually reduced from top to bottom, and the volume of P-type column 202 is increased and the width is gradually increased from top to bottom, under the condition that the widths of the top of N-type column 204 and P-type column 202 are kept unchanged, compared with the conventional superjunction structure in which P-type column 202 is formed by filling trench 203, the embodiments of the present invention can simultaneously reduce the difference in impurity amount between P-type column 202 and P-type column 202 at the top and bottom positions of the superjunction unit, in combination with the change in the widths of N-type column 204 and P-type column 202, compared with the conventional structure, under the condition that the total doping amount of N-type column 204 of the superjunction unit, that is, the total doping amount of P-type column 202, is kept unchanged, embodiments of the present invention can improve charge matching between P-type columns 202 and N-type columns 204 of a superjunction cell at the top and bottom locations.
Meanwhile, the embodiment of the invention can realize that the P-type impurity amount of the P-type column 202 at the bottom of the super junction unit is larger than the N-type impurity amount of the N-type column 204, and the first N-type epitaxial layer 201 is arranged at the bottom of the super junction structure, so that more P-type impurities than the P-type column 202 can be exhausted from the bottom through the first N-type epitaxial layer 201, thereby compensating the influence of the P-type impurity amount of the P-type column 202 at the bottom of the super junction unit larger than the N-type impurity amount of the N-type column 204 on the reduction of the breakdown voltage, and finally improving the breakdown voltage of the device; on the contrary, in the conventional structure, since the P-type impurity amount of P-type column 202 at the bottom of the super junction unit is less than the N-type impurity amount of N-type column 204, similar compensation in the embodiment of the present invention cannot be performed through the N-type epitaxial layer disposed at the bottom, and certainly, the breakdown voltage of the device cannot be increased.
Meanwhile, the embodiment of the invention can realize that the P-type impurity amount of the P-type column 202 at the bottom of the super junction unit is less than the N-type impurity amount of the N-type column 204, and because the P-type body region 1 is usually formed at the top of the super junction structure, the P-type body region 1 can be used up from more than N-type impurities at the top of the N-type column 204, so that the influence of the P-type impurity amount of the P-type column 202 at the top of the super junction unit being less than the N-type impurity amount of the N-type column 204 on the reduction of the breakdown voltage can be compensated, and the breakdown voltage of the device can be finally improved; on the contrary, in the conventional structure, since the P-type impurity amount of P-type column 202 at the top of the super junction unit is greater than the N-type impurity amount of N-type column 204, similar compensation in the embodiment of the present invention cannot be performed through P-type body region 1, and certainly, the breakdown voltage of the device cannot be increased.
The difference between the superjunction device according to the first embodiment of the present invention and the existing superjunction device is specifically described below with a specific parameter:
the existing super junction device shown in fig. 1 and the super junction device shown in fig. 2 according to the first embodiment of the present invention are only partially different in the super junction structure, and other structures are the same and are denoted by the same reference numerals.
In the super junction device of the first embodiment of the invention, for example, a 600V high-voltage NMOSFET is used, and the super junction device has the following parameters:
the semiconductor substrate 10 has a doping concentration higher than 1E19cm-3Corresponding to a resistivity of, for example, 0.001 ohm-cm to 0.003 ohm-cm, and a thickness of about 725 μm.
The thickness of the first N-type epitaxial layer 201 is about 5-20 microns, the buffer layer with large thickness can improve the body diode performance of the device, the current surge resistance (EAS) capability of the device is improved, and the buffer layer with thin thickness can reduce the specific on-resistance (Rsp) of the device.
In device design, the P-type body region 1 is usually formed by a P-type well, the depth of the P-type body region 1 is 2 micrometers, the thickness of the first P-type epitaxial layer, i.e., the P-type column 202 is 40 micrometers, the depth of the trench 203 is equal to 40 micrometers or deeper than 40 micrometers, and the total impurity amount of the N-type region, i.e., the N-type column 204, is kept consistent in design so as to keep the same Rsp. The side inclination angle of the trench 203 is 88.6 degrees to 89 degrees, and here, assuming that the inclination angle of the trench 203 is 88.6 degrees, the width of the top of the trench 203 is set to be 5 micrometers, the width of the top of the P-type pillar 202 is 4 micrometers, and the step of the super junction unit is 9 micrometers.
The thickness from line A1A2 to line C1C2 in FIG. 2 is 40 microns; the P-type body region 1 depth corresponds to the distance between line B1B2 to line C1C2, being 2 microns; the P-type pillars 202 withstand voltage to a thickness between line A1A2 and line B1B2, measuring 38 microns.
The concentrations of the N-type columns 204 and the P-type columns 202 are uniform, and the P-type impurity obtained by multiplying the concentration of the P-type columns 202 by the width at the center line from the line A1a2 to the line B1B2 and the N-type impurity obtained by multiplying the concentration of the N-type columns 204 by the width are maintained to be equal, because the characteristic that the trenches 203 are wide at the top and narrow at the bottom cannot ensure the P-N balance on all the parallel lines, and the charge balance on the center line, that is, the P-type impurity and the N-type impurity are balanced in the total amount is maintained. The P-N balance indicates that the doping amounts of the P-type column and the N-type column are equal.
The above arrangement is also applicable to existing superjunction devices.
In the device of the first embodiment of the present invention: the groove 203 corresponding to the N-type column 204 is an inclined groove, the width of the top of the groove 203 is set to be 5 micrometers, the width of the N-type column 204 is 3.97 micrometers, and the width of the bottom groove is 3.05 micrometers on the median line of the line A1A2 and the line B1B 2.
The width of the top of the P-type pillars 202 is 4 microns, the width of the P-type pillars 202 on the median line from line A1a2 to line B1B2 is 5.03 microns, and the width of the bottom of the P-type pillars 202 is 5.95 microns.
The N-type column 204 is uniformly doped with a doping concentration of 4E15cm-3Then the total amount of N-type impurities of the N-type column 204 from line A1A2 to line B1B2 is 6.04E9cm-1。
The total amount of P-type impurities in P-type column 202 at the optimum balance is also 6.04E9cm-1. The P-type impurity of the P-type column 202 is also uniform, and the optimal concentration of the P-type impurity of the P-type column 202 is 3.16E15cm-3. I.e., at the level of the median line from line A1A2 to line B1B2, the P-N charges are balanced.
In the part of the middle line upward, the P-type impurity is less than the N-type impurity on the same horizontal line, in the part below the middle line, the P-type impurity is more than the N-type impurity, in the grooveThe product of the concentration of the P-type impurity, i.e., the concentration of the P-type impurity multiplied by the width of the bottom of the trench, is 6.62E11cm more than that of the N-type impurity at the bottom of the trench 203, i.e., at the level of the line A1A2-2(ii) a On the horizontal line of line B1B2, which is the region where the top of trench 203 meets P-type body region 1, the P-type impurity is less than the N-type impurity and on the line B1B2, the P-type impurity is less than the N-type impurity by 6.65E11cm, regardless of the effects of the ion implantation of P-type body region 1 and the ion implantation of JFET implantation region 6-2。
In the conventional superjunction device shown in fig. 1: the width of the top of the P-type pillar 103 is 4 microns, the corresponding trench 102 is set as an inclined trench, the width of the top of the trench 102 is set to 4 microns, on the median line from the line A1a2 to the line B1B2, the width of the P-type pillar 103 is 2.97 microns, and the width of the bottom trench 102 is 2.05 microns.
The width of the top of the N-type pillar 101 is 5 microns, the width of the N-type pillar 101 on the median line from line A1a2 to line B1B2 is 6.03 microns, and the width of the bottom of the N-type pillar 101 is 6.95 microns.
The impurity concentration of the N-type column 101 was set to 2.64E15cm-3Then the total amount of N-type impurities of the N-type column 101 from the line A1A2 to the line B1B2 is 6.04E9cm-1The total amount of P-type impurities in the P-type column 103 at the optimum balance is also 6.04E9cm-1。
The P-type impurity of the P-type column 103 is also uniform, and then the optimal concentration of the P-type impurity of the P-type column 103 is 5.35E15cm-3. That is, in the horizontal line from the line A1a2 to the center line of the line B1B2, the P-N charge is balanced, the P-type impurity is more than the N-type impurity in the same horizontal line in the upward part of the center line, the P-type impurity is less than the N-type impurity in the part below the center line, and the product of the concentration of the P-type impurity, i.e., the concentration of the P-type impurity and the width of the bottom of the trench is 7.37E11cm less than the N-type impurity in the horizontal line corresponding to the line A1a2, which is the bottom of the trench 102-2(ii) a In the horizontal line of line B1B2, which is the region where the top of trench 102 meets P-type body region 1, P-type impurities are more than N-type impurities regardless of the effects of ion implantation of P-type body region 1 and ion implantation of JFET implantation region 6, and in the line B1B2, P-type impurities are 7.43E11/cm2 more than N-type impurities. The data above are summarized in the following table one.
Watch 1
Figure BDA0002257349290000141
It can be seen that since the super junction device of the first embodiment of the present invention and the existing super junction device maintain the same step (pitch), that is, 9 μm step and the same total amount of N-type impurities in one step is 6.04E9cm-1Keeping their rsps consistent at room temperature.
N-type impurity concentration 4E15cm due to super junction device of first embodiment of the present invention-3Is obviously higher than the prior art 2.64E15cm-3Therefore, the increased amplitude of Rsp of the super junction device according to the first embodiment of the present invention is lower than that of the existing super junction device when the temperature rises, so that the high-temperature on-resistance of the super junction device according to the first embodiment of the present invention is lower than that of the existing super junction device, and the high-temperature applicable characteristics of the device are improved. As shown in fig. 4, which is a curve of the on-resistance of the superjunction device according to the first embodiment of the present invention and the existing superjunction device as a function of temperature, a curve 301 is a curve of the on-resistance of the existing superjunction device as a function of temperature, and a curve 302 is a curve of the on-resistance of the superjunction device according to the first embodiment of the present invention as a function of temperature, it can be seen that the on-resistance of the superjunction device according to the first embodiment of the present invention is lower at high temperature.
Considering only the case of epitaxial deposition and epitaxial filling of trenches, i.e., one of the N-type column and the P-type column is composed of a deposited epitaxial layer, and the other is composed of an epitaxial layer filled in trenches formed in a deposited epitaxial layer, under the condition that the set P, N impurities are completely balanced in the PN column, i.e., the median line of the superjunction cell, the amount of the P-type impurity at the bottom of the superjunction device of the first embodiment of the present invention which is more than the N-type impurity is less than the amount of the P-type impurity at the bottom of the superjunction device of the prior art, particularly under the condition of the superjunction device of the first embodiment of the present invention, the portion with more P-type impurities at the bottom can be balanced by the impurities of the N-type buffer layer, i.e., the first N-type epitaxy 201, below the P-type column 202.
On the other hand, in the case of considering only epitaxial deposition and epitaxial filling of the trench on the top, i.e., the horizontal line of the line B1B2, the amount of the P-type impurity on the top of the superjunction device of the first embodiment of the present invention, which is less than the amount of the N-type impurity, is less than the amount of the P-type impurity on the top of the superjunction device of the prior art, which is more than the amount of the N-type impurity, and particularly, under the condition of the superjunction device of the first embodiment of the present invention, the portion with less P-type impurity on the top can be supplemented by the impurity of the P-type well. This relationship is shown in fig. 5, fig. 5 is a distribution curve of electric field intensity in the longitudinal direction in the superjunction unit of the superjunction device according to the first embodiment of the present invention and the superjunction device of the related art, curve 303 corresponds to a distribution curve of electric field intensity in the longitudinal direction in the superjunction unit of the related superjunction device, and curve 304 corresponds to a distribution curve of electric field intensity in the longitudinal direction in the superjunction unit of the superjunction device according to the first embodiment of the present invention, and it can be seen that at line A1a2 and line B1B2, the electric field intensity of curve 304 is improved, so that the breakdown voltage can be improved.
The super junction device of the first embodiment of the invention obtains the same Rsp and higher BVds, and is filled with N-type impurity concentration 4E15cm-3Concentration of 5.35E15cm significantly lower than the P-type impurity fill of existing superjunction devices-3Therefore, under the condition that the concentration of the filling impurities changes by the same percentage, the super junction device of the first embodiment of the invention has small impurity amount change, which is beneficial to the consistency of the device, because in the process of filling the doping epitaxy in the groove, the concentration control is more difficult than that in the epitaxy deposition process on the plane, and the process margin of the groove filling process is more important.
The second embodiment of the invention is a super junction device:
the super junction device is different from the super junction device of the first embodiment of the invention in that the side surface of the trench 203 in the super junction device of the second embodiment of the invention is in a vertical structure; the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.
The difference between the superjunction device according to the second embodiment of the present invention and the conventional superjunction device with vertical trench sides is described below with a specific parameter:
in the existing super junction device, the width of the top of a P-type column is 4 micrometers, the width of the top of an N-type column is 5 micrometers, and the step of super junction unitFurther 9 microns, the concentration of the planar deposited N epitaxial layer, i.e., the epitaxial layer corresponding to the N-type pillars, was 3.18e15cm-3The concentration of the P-type impurity, i.e. P-type column, filled in the trench is 3.97E15 cm-3。
In the super junction device of the second embodiment of the invention, the width of the top of the P-type column is 4 micrometers, the width of the top of the N-type column is 5 micrometers, the step of the super junction unit is 9 micrometers, and the concentration of the plane-deposited P epitaxial layer, i.e. the P-type column, is 3.97e15 cm-3The concentration of the P-type impurity, i.e. P-type column, filled in the trench is 3.18E15cm-3。
It can be seen that the concentration of the impurity filled in the trench of the superjunction device according to the second embodiment of the present invention is lower than that of the superjunction device in the related art, because the control of the impurity concentration in the trench filling is significantly higher than that of the impurity deposited on the plane, the related art superjunction device makes the difficulty of the manufacturing technology lower or improves the uniformity of the device.
The manufacturing method of the super junction device of the first embodiment of the invention comprises the following steps:
as shown in fig. 3A to 3B, there are schematic device structures in the steps of forming the superjunction structure in the method of manufacturing a superjunction device according to the first embodiment of the present invention; in the method for manufacturing the super junction device according to the first embodiment of the present invention, the super junction device is an N-type device and is formed on the super junction structure; the super junction structure is formed by alternately arranging P-type columns 202 and N-type columns 204, and one P-type column 202 and one adjacent N-type column 204 form a super junction unit; the width of the P-type column 202 at the top position of the superjunction unit is smaller than the width of the N-type column 204 and the sum of the widths of the P-type column 202 and the N-type column 204 is unchanged, so as to increase the volume of the N-type column 204 and reduce the specific on-resistance of the superjunction device; manufacturing the super junction structure by adopting the following steps:
step one, as shown in fig. 3A, providing an N-type semiconductor substrate 10 doped with high concentration, and forming a first N-type epitaxial layer 201 on the semiconductor substrate 10; the first N-type epitaxial layer 201 serves as a buffer layer at the bottom of the super junction structure.
Step two, as shown in fig. 3A, a first P-type epitaxial layer is formed on the surface of the first N-type epitaxial layer 201.
Step three, as shown in fig. 3A, a trench 203 is formed in the first P-type epitaxial layer by using a lithography definition plus etching process, wherein the trench 203 penetrates through the first P-type epitaxial layer and the bottom of the trench is in contact with the first N-type epitaxial layer 201.
The top opening of the trench 203 is set according to the top width of the N-type column 204 with the larger top width of the super junction unit, so that the aspect ratio of the trench 203 can be reduced.
In the third step, before performing the photolithography definition, a step of forming a hard mask layer 205 on the surface of the first P-type epitaxial layer is further included, the hard mask layer 205 is etched in the etching process, then the first P-type epitaxial layer is etched, and after the etching in the third step is completed, the hard mask layer 205 with a partial thickness is removed.
Preferably, the hard mask layer 205 is formed by stacking a first oxide film, a second nitride film, and a third oxide film.
And after the etching process of the groove 203 is finished, removing the third oxide film and the second nitride film by adopting a dry etching process or a wet etching process.
Step four, as shown in fig. 3B, a second N-type epitaxial layer is filled in the trench 203, the N-type column 204 is composed of the second N-type epitaxial layer filled in the trench 203, and the P-type column 202 is composed of the first P-type epitaxial layer between the trenches 203.
In the fourth step, an epitaxial growth process of the second N-type epitaxial layer is performed first, and the second N-type epitaxial layer after the growth is completed further extends to the outer surface of the trench 203; then, a chemical mechanical polishing process is used to remove all the second N-type epitaxial layer on the outer surface of the trench 203, and then the remaining hard mask layer 205, i.e., the first oxide film, is removed.
The total amount of P-type impurities of the P-type column 202 and the total amount of N-type impurities of the N-type column 204 in the super junction unit are matched, and the doping concentration of the P-type column 202 is lower than that of the N-type column 204; the doping concentration of the second N-type epitaxial layer filling the trench 203 is set according to the doping concentration of the N-type column 204 with the lower doping concentration of the super junction unit so as to reduce the variation of the impurity amount of the epitaxial filling process of the trench 203.
As shown in fig. 2, the super junction device includes a plurality of super junction device units, each of which is formed on a corresponding super junction unit; after the super junction structure is formed, the method further comprises the following steps:
forming a P-type body region 1, wherein the P-type body region 1 is formed on the top of the P-type pillar 202 and extends into the N-type pillar 204;
forming a gate structure, a source region 4, an interlayer film 7, a contact hole 8 and a front metal layer 9, and patterning the front metal layer 9 to form a gate and a source.
And thinning the back surface of the semiconductor substrate 10, forming a drain region on the back surface of the semiconductor substrate 10, and forming a back surface metal layer 11 on the back surface of the drain region.
The grid structure is a planar grid and is formed by superposing a grid dielectric layer such as a grid oxide layer 2 and a polysilicon grid 3. In other embodiments the method can also be: the grid structure is a trench grid.
The drain region is composed of the semiconductor substrate 10 with the back surface thinned. In other embodiments, this can also be: the drain region is composed of an N + ion implantation region formed in the semiconductor substrate 10 after the back surface is thinned.
Typically, a contact region 5 consisting of a P + region is formed on top of the contact hole 8 on top of the source region 4, the contact region 5 being formed by ion implantation after opening of the contact hole 8 and before metal filling.
The surface of the body region 1 covered by the polysilicon gate 3 is used to form a channel. In order to reduce the on-resistance of the top region of the N-type pillar 204 between two adjacent body regions 1, a JFET implant region 6 is also typically formed.
The thickness of the first N-type epitaxial layer 201 is 5-20 microns, and the body diode characteristic of the device is adjusted through the thickness of the first N-type epitaxial layer 201, so that the thicker the thickness of the first N-type epitaxial layer 201 is, the better the body diode characteristic of the device is.
In the method of the embodiment of the present invention, the side surface of the trench 203 is in an inclined structure, the top width of the N-type pillar 204 is greater than the bottom width, and the top width of the P-type pillar 202 is less than the bottom width.
The structure that the width of N-type column 204 gradually decreases from top to bottom reduces the volume of N-type column 204 and increases the doping concentration of N-type column 204 under the condition that the super junction unit is not stepped and the total amount of N-type doping is not changed, so as to reduce the high-temperature on-resistance of the super junction device.
The first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.
The doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer enable the P-type impurity amount of the P-type column 202 and the N-type impurity amount of the N-type column 204 at the middle position of the super junction unit at the bottom of the P-type well in depth to form optimal matching.
The P-type impurity amount of the P-type column 202 at each position above the middle position in depth of the super junction unit is smaller than the N-type impurity amount of the N-type column 204.
The P-type impurity amount of the P-type column 202 at each position above the middle position in depth of the super junction unit is larger than the N-type impurity amount of the N-type column 204.
The first N-type epitaxial layer 201 simultaneously forms a compensation structure for depleting P-type impurities of the P-type columns 202 from the bottom, so as to compensate the influence of the fact that the P-type impurity amount of the P-type columns 202 at the bottom of the super junction unit is larger than the N-type impurity amount of the N-type columns 204 on breakdown voltage reduction.
The P-type body region 1 simultaneously forms a compensation structure for depleting the N-type impurities of the N-type column 204 from the top, so as to compensate the influence of the fact that the P-type impurity amount of the P-type column 202 at the top of the super junction unit is smaller than the N-type impurity amount of the N-type column 204 on the reduction of the breakdown voltage.
The method for manufacturing the super junction device comprises the following steps:
the manufacturing method of the superjunction device according to the second embodiment of the present invention is different from the manufacturing method of the superjunction device according to the first embodiment of the present invention in that the side surface of the trench 203 in the manufacturing method of the superjunction device according to the second embodiment of the present invention is in a vertical structure; the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A super junction device is characterized by comprising a super junction structure formed by alternately arranging P-type columns and N-type columns; the super junction device is an N-type device and is formed on the super junction structure; one P-type column and one adjacent N-type column form a super junction unit;
the super junction structure is formed above the surface of a first N-type epitaxial layer, the first N-type epitaxial layer is formed on an N-type high-concentration doped semiconductor substrate, and the first N-type epitaxial layer is used as a buffer layer at the bottom of the super junction structure;
the width of the P-type column at the top position of the super junction unit is smaller than that of the N-type column, and the width of the P-type column and the width of the N-type column are not changed, so that the volume of the N-type column is increased, and the specific on-resistance of the super junction device is reduced;
the N-type column with the larger top width of the super junction unit is composed of a second N-type epitaxial layer filled in the grooves, the P-type column with the smaller top width of the super junction unit is composed of a first P-type epitaxial layer between the grooves, and the first P-type epitaxial layer is formed on the first N-type epitaxial layer; the groove penetrates through the first P-type epitaxial layer, and the bottom of the groove is in contact with the first N-type epitaxial layer;
the total amount of P-type impurities of the P-type column in the super junction unit is matched with the total amount of N-type impurities of the N-type column, and the doping concentration of the P-type column is higher than that of the N-type column;
the top opening of the groove is arranged according to the top width of the N-type column with the larger top width of the super junction unit and is defined through photoetching so as to reduce the height-to-width ratio of the groove; the doping concentration of the second N-type epitaxial layer filling the groove is set according to the doping concentration of the N-type column with the lower doping concentration of the super junction unit so as to reduce the change of the impurity amount of the epitaxial filling process of the groove.
2. The superjunction device of claim 1, wherein: the super junction device comprises a plurality of super junction device units, and each super junction device unit is formed on the corresponding super junction unit;
the superjunction device unit comprises a P-type body region formed at the top of the P-type column and extending into the N-type column.
3. The superjunction device of claim 2, wherein: the thickness of the first N-type epitaxial layer is 5-20 microns, and the body diode characteristic of the device is adjusted through the thickness of the first N-type epitaxial layer, so that the thicker the thickness of the first N-type epitaxial layer is, the better the body diode characteristic of the device is.
4. The superjunction device of claim 2, wherein: the side surface of the groove is of a vertical structure; the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.
5. The superjunction device of claim 2, wherein: the side surface of the groove is of an inclined structure, the width of the top of the N-type column is larger than that of the bottom of the groove, and the width of the top of the P-type column is smaller than that of the bottom of the groove;
the structure that the width of the N-type column is gradually reduced from the top to the bottom enables the volume of the N-type column to be reduced and the doping concentration of the N-type column to be improved under the condition that the step of the super junction unit is not changed and the total amount of N-type doping is not changed, so that the high-temperature on-resistance of the super junction device is reduced.
6. The superjunction device of claim 5, wherein: the first P type epitaxial layer is uniformly doped, and the second N type epitaxial layer is uniformly doped;
the doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer enable the P-type impurity amount of the P-type column and the N-type impurity amount of the N-type column at the middle position of the super junction unit at the bottom of the P-type well in depth to form optimal matching;
the P-type impurity amount of the P-type column at each position above the middle position of the super junction unit in depth is less than the N-type impurity amount of the N-type column;
the P-type impurity amount of the P-type column at each position above the middle position of the super junction unit in depth is larger than the N-type impurity amount of the N-type column.
7. The superjunction device of claim 6, wherein: the first N-type epitaxial layer simultaneously forms a compensation structure for depleting P-type impurities of the P-type column from the bottom so as to compensate the influence of the fact that the P-type impurity amount of the P-type column at the bottom of the super junction unit is larger than the N-type impurity amount of the N-type column on the reduction of breakdown voltage;
and the P-type body region simultaneously forms a compensation structure for depleting N-type impurities of the N-type column from the top so as to compensate the influence of the fact that the P-type impurity amount of the P-type column at the top of the super junction unit is smaller than the N-type impurity amount of the N-type column on the reduction of breakdown voltage.
8. A manufacturing method of a super junction device is characterized in that the super junction device is an N-type device and is formed on a super junction structure; the super junction structure is formed by alternately arranging P-type columns and N-type columns, and one P-type column and one adjacent N-type column form a super junction unit; the width of the P-type column at the top position of the super junction unit is smaller than that of the N-type column, and the width of the P-type column and the width of the N-type column are not changed, so that the volume of the N-type column is increased, and the specific on-resistance of the super junction device is reduced; manufacturing the super junction structure by adopting the following steps:
providing an N-type high-concentration doped semiconductor substrate, and forming a first N-type epitaxial layer on the semiconductor substrate; the first N-type epitaxial layer is used as a buffer layer at the bottom of the super junction structure;
step two, forming a first P-type epitaxial layer on the surface of the first N-type epitaxial layer;
step three, forming a groove in the first P-type epitaxial layer by adopting a photoetching definition and etching process, wherein the groove penetrates through the first P-type epitaxial layer and the bottom of the groove is in contact with the first N-type epitaxial layer;
the top opening of the groove is arranged according to the width of the top of the N-type column with the larger width of the top of the super junction unit, so that the aspect ratio of the groove can be reduced;
filling a second N-type epitaxial layer in the groove, wherein the N-type column is composed of the second N-type epitaxial layer filled in the groove, and the P-type column is composed of the first P-type epitaxial layer between the grooves;
the total amount of P-type impurities of the P-type column in the super junction unit is matched with the total amount of N-type impurities of the N-type column, and the doping concentration of the P-type column is lower than that of the N-type column; the doping concentration of the second N-type epitaxial layer filling the groove is set according to the doping concentration of the N-type column with the lower doping concentration of the super junction unit so as to reduce the change of the impurity amount of the epitaxial filling process of the groove.
9. The manufacturing method of the super junction device manufacturing method according to claim 8, characterized in that: in the third step, before the photoetching definition, a step of forming a hard mask layer on the surface of the first P-type epitaxial layer is also included, the hard mask layer is etched firstly in an etching process, then the first P-type epitaxial layer is etched, and the hard mask layer with partial thickness is removed after the etching in the third step is finished; in the fourth step, an epitaxial growth process of the second N-type epitaxial layer is performed first, and the second N-type epitaxial layer after the growth is completed further extends to the outer surface of the trench; and then removing the second N-type epitaxial layer on the outer surface of the groove by adopting a chemical mechanical polishing process, and then removing the residual hard mask layer.
10. The manufacturing method of the super junction device manufacturing method according to claim 8, characterized in that: the super junction device comprises a plurality of super junction device units, and each super junction device unit is formed on the corresponding super junction unit; after the super junction structure is formed, the method further comprises the following steps:
and forming a P-type body region which is formed at the top of the P-type column and extends into the N-type column.
11. The method of manufacturing a superjunction device of claim 10, wherein: the thickness of the first N-type epitaxial layer is 5-20 microns, and the body diode characteristic of the device is adjusted through the thickness of the first N-type epitaxial layer, so that the thicker the thickness of the first N-type epitaxial layer is, the better the body diode characteristic of the device is.
12. The method of manufacturing a superjunction device of claim 10, wherein: the side surface of the groove is of a vertical structure; the first P-type epitaxial layer is uniformly doped, and the second N-type epitaxial layer is uniformly doped.
13. The method of manufacturing a superjunction device of claim 10, wherein: the side surface of the groove is of an inclined structure, the width of the top of the N-type column is larger than that of the bottom of the groove, and the width of the top of the P-type column is smaller than that of the bottom of the groove;
the structure that the width of the N-type column is gradually reduced from the top to the bottom enables the volume of the N-type column to be reduced and the doping concentration of the N-type column to be improved under the condition that the super-junction unit is not stepped and the total amount of N-type doping is not changed, so that the high-temperature on-resistance of the super-junction device is reduced.
14. The method of manufacturing a superjunction device of claim 13, wherein: the first P type epitaxial layer is uniformly doped, and the second N type epitaxial layer is uniformly doped;
the doping concentrations of the first P-type epitaxial layer and the second N-type epitaxial layer enable the P-type impurity amount of the P-type column and the N-type impurity amount of the N-type column at the middle position of the super junction unit at the bottom of the P-type well in depth to form optimal matching;
the P-type impurity amount of the P-type column at each position above the middle position of the super junction unit in depth is less than the N-type impurity amount of the N-type column;
the P-type impurity amount of the P-type column at each position above the middle position of the super junction unit in depth is larger than the N-type impurity amount of the N-type column.
15. The method of manufacturing a superjunction device of claim 14, wherein: the first N-type epitaxial layer simultaneously forms a compensation structure for depleting P-type impurities of the P-type column from the bottom so as to compensate the influence of the fact that the P-type impurity amount of the P-type column at the bottom of the super junction unit is larger than the N-type impurity amount of the N-type column on the reduction of breakdown voltage;
and the P-type body region simultaneously forms a compensation structure for depleting N-type impurities of the N-type column from the top so as to compensate the influence of the fact that the P-type impurity amount of the P-type column at the top of the super junction unit is smaller than the N-type impurity amount of the N-type column on the reduction of breakdown voltage.
CN201911058984.8A 2019-11-01 2019-11-01 Super junction device and manufacturing method thereof Pending CN112768522A (en)

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