CN117637836A

CN117637836A - Trench gate superjunction device and manufacturing method thereof

Info

Publication number: CN117637836A
Application number: CN202210949444.4A
Authority: CN
Inventors: 肖胜安; 曾大杰
Original assignee: Shenzhen Shangyangtong Technology Co ltd
Current assignee: Shenzhen Shangyangtong Technology Co ltd
Priority date: 2022-08-09
Filing date: 2022-08-09
Publication date: 2024-03-01

Abstract

The invention discloses a trench gate superjunction device, wherein a trench gate of a device unit structure is formed by laminating a bottom dielectric layer, a gate dielectric layer and a gate conductive material which are formed in a gate trench. The bottom dielectric layer is formed at the bottom of the gate trench. Each gate trench is formed by the same trench etching process, the bottom surface of each gate trench is not flat and the positional deviation of the bottom surface is determined by the trench etching process. The bottom dielectric layer is formed by etching the first dielectric layer completely filled in the gate trenches from top to bottom, the etching process of the first dielectric layer enables the top surfaces of the bottom dielectric layers to be leveled, and the thickness deviation of the bottom dielectric layers just compensates the position deviation of the bottom surfaces of the gate trenches. The invention also discloses a manufacturing method of the trench gate superjunction device. The invention can improve the consistency of the length of the conducting channel and the length of the accumulation region of the device, thereby improving the consistency of the performance of the device.

Description

Trench gate superjunction device and manufacturing method thereof

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench gate super junction (super junction) device. The invention also relates to a manufacturing method of the trench gate superjunction device.

Background

The super junction structure is a structure of alternately arranged N-type columns and P-type columns. If the N-type drift region in a Vertical Double-diffused Metal-Oxide-Semiconductor (VDMOS) device is replaced with a superjunction structure, a superjunction Metal-Oxide-Semiconductor field effect transistor (MOSFET) is formed by providing an on-state (only N-type pillars provide the on-state, P-type pillars do not provide the on-state) and by receiving a reverse bias voltage (PN pillars commonly received) in an off-state. The super junction MOSFET can greatly reduce the on-resistance of the device by using an epitaxial layer with low resistivity under the condition that the reverse breakdown voltage is consistent with that of a traditional VDMOS device.

A typical superjunction device includes a charge flow region, a transition region, and a termination region. The charge flow region is formed by alternating P-type and N-type pillars, or to obtain a lower resistance value when turned on, it is necessary to employ a higher concentration of P-N pillars in combination with a smaller step, the P-N pillars representing alternating P-type and N-type pillars. However, in the P-N column filled with the trench, the width of the trench needs to be reduced by smaller steps, the transition region is adjacent to the charge flow region, namely the current flow region and surrounds the charge flow region, the transition region comprises a P-type region with larger width, a dielectric film with a certain thickness can be arranged on at least the P-type region, and the dielectric film can be provided with polysilicon and a contact hole and metal on the polysilicon, wherein the polysilicon and the metal are respectively used as a polysilicon field plate and a metal field plate and are connected with a gate pad (gate pad) formed by a front metal layer and are connected with a polysilicon gate of the charge flow region, so that the potential control on the gate is realized; the metal connected with the polysilicon gate through the contact hole, namely the metal of the gate and the metal on the charge flow region and part of the transition region (one part of the P-type ring is connected), namely the metal of the source, are physically separated by a certain distance, such as 2-10 microns; the transition area is provided with a terminal area, the terminal area is provided with P-type columns and N-type columns which are alternately arranged, a dielectric film can be arranged on the terminal area, the dielectric film can be provided with a floating polycrystalline silicon field plate and a metal field plate, the area of the terminal close to the scribing groove can be provided with an N+ cut-off ring, the terminal area can be provided with a floating metal field plate or a metal field plate connected to the N+ cut-off ring, and the terminal area is used for bearing the reverse bias voltage of the chip and protecting the chip physically to a certain extent.

In the prior art, N-type epitaxy is deposited on a high concentration N-type semiconductor substrate, for example, for superjunction devices above 600V, the impurity concentration of the N-type substrate is higher than 1E19cm ^-3 The concentration of the N-type epitaxy is 1E15cm ^-3 ～1E16cm ^-3 In order to reduce the specific on-resistance, the concentration of the N-type epitaxial impurities of the chip is continuously improved, the lateral dimension of the P-N column is continuously reduced, namely, the step size is reduced, and meanwhile, the advantage of adopting the trench gate is higher and higher, because the trench gate can increase the channel density, reduce the specific on-resistance, and simultaneously eliminate the JFET region of the planar gate, the N region of the planar gate between the P-type wells under the polycrystalline gate is smaller and smaller under the condition that the step size is continuously reduced, the JFET effect is more and more serious, and the trench gate is beneficial to further reducing the specific on-resistance after eliminating the JFET effect. However, the adoption of the trench gate brings about a problem of large Cgd, particularly a problem of relatively large variation of Cgd, wherein Cgd represents a gate-drain capacitance, so that the trench etching process of the trench gate has great control difficulty and relatively large variation of depth, for example: the depth of the groove with the depth of 4 microns can reach the range of +0.4mu.m to-0.4mu.m, cgd is in direct proportion to the contact area between the grid and the N-type column, and the change of the groove grid, namely the groove of the grid, leads the change of Cgd of the device to be large, and affects the uniformity of the switching characteristic of the device.

As shown in fig. 1, a top view of a prior art superjunction device; a typical superjunction device structure includes a current flow region, a termination region that is laterally subject to a reverse bias voltage, and a transition region between the current flow region and the termination region, the termination region surrounding the periphery of the current flow region, region 1 in fig. 1 representing the current flow region, region 2 representing the transition region, and region 3 representing the termination region.

Region 1 includes a superjunction structure composed of alternating P-type pillars 22 and N-type pillars 23, with both the P-type pillars 22 and N-type pillars 23 in the stripe-shaped structure of fig. 1. The N-type pillar 23 provides a conduction path when the superjunction device is turned on, and the P-type pillar 22 and the N-type pillar 23 are depleted from each other when the superjunction device is reverse biased and commonly receive a reverse bias.

The region 2 and the region 3 are positioned at the terminal of the superjunction device and are jointly used as a terminal protection structure for representing the superjunction device. The regions 2 and 3 provide no current when the device is on, and in the reverse bias state are used to assume a voltage from the surface of the peripheral cell of region 1 to the substrate at the outermost surface of the device, which is a lateral voltage, and a voltage from the surface of the peripheral cell of region 1 to the substrate, which is a longitudinal voltage.

At least one P-type ring 25 is provided in region 2, and in fig. 1, one P-type ring 25 is provided, wherein the P-type ring 25 is generally connected with a P-type back gate, i.e., a P-type well, in region 1; in the prior art, a field plate dielectric film with a certain inclination angle is generally arranged in the region 2, a field plate 24 for slowing down the abrupt change of a surface electric field is also arranged in the region 2, the field plate 24 is a polycrystalline field plate or a metal field plate, and the P-type column 22; the metal field plate may not be disposed in the region 2.

The 3 region includes a super junction structure composed of alternately arranged P-type columns 22 and N-type columns 23, and the P-type columns 22 and N-type columns 23 in the 3 region in fig. 1 are respectively formed by extending and expanding the P-type columns 22 and N-type columns 23 in the 1 region, and the alternately arranged directions are the same. In other configurations, the region 3P-type pillars 22 and N-type pillars 23 can also be end-to-end ring-type structures.

The metal field plate is arranged in the region 3, and the metal field plate is not arranged in the region 3; the region 3 may or may not have a P-type ring 25, where the P-type ring 25 is not connected to the P-type back gate connection of the current flow region (floating); at the outermost end of zone 3 there is a terminal stop ring 21, said terminal stop ring 21 being formed of an n+ implant zone or an n+ implant zone plus a dielectric or a dielectric plus a metal formed thereon.

FIG. 2A is a schematic cross-sectional view of a conventional trench gate superjunction device; as shown in fig. 2B, a partial enlarged view of a top view of a prior trench gate superjunction device; the middle area of the conventional trench gate superjunction device is a current flowing area, a terminal area surrounds the periphery of the current flowing area, and a transition area is positioned between the current flowing area and the terminal area. In fig. 2A, the current flowing area is 1 area, the transition area is 2 area, the terminal area is 3 area, and the top plane structure is shown in fig. 1.

An epitaxial layer 102 is formed on a semiconductor substrate 101, and a superjunction structure formed by alternately arranging N-type columns 102a and P-type columns 103 is formed in the epitaxial layer 102. N-type column 102a corresponds to N-type column 23 in fig. 1 and P-type column 103 corresponds to P-type column 22 in fig. 1.

The super junction structures are formed in the region 1, the region 2 and the region 3, and a device unit structure of a plurality of super junction devices in parallel structures is formed on the top of the super junction structure of the current flow region.

The trench gate of each device unit structure is formed by overlapping a gate dielectric layer 104 and a polysilicon gate 105 formed in the gate trench.

The gate trench is wholly or partially located in the N-type pillar 102a, the gate dielectric layer 104 is formed on the side of the gate trench, and the polysilicon gate 105 completely fills the gate trench.

The channel region of each device unit structure is composed of a P-type well region 106 formed on the surface of the superjunction structure, the polysilicon gate 105 penetrates through the channel region in the longitudinal direction, the surface of the channel region covered by the side surface of the polysilicon gate 105 located in the N-type column 102a is used for forming a conductive channel, and the surface of the N-type column 102a below the conductive channel covered by the side surface of the polysilicon gate 105 is used for forming an accumulation region.

When the gate trenches are all located in the N-type pillars 102a, both sides of the polysilicon gate 105 cover the corresponding channel regions and form the conductive channel.

When the gate trench portion is located in the N-type pillar 102a, one side of the gate trench is located in the N-type pillar 102a and the other side is located in the P-type pillar 103, so that only one side of the polysilicon gate 105, i.e., the side located in the N-type pillar 102a, covers the corresponding channel region and forms the conductive channel.

A source region 107 composed of an N-type heavily doped region is formed on the surface of the channel region.

A P-type ring 106a is formed in the transition region. P-type ring 106a corresponds to P-type ring 25 in fig. 1.

A guard ring dielectric layer 109 is further formed in the termination region 3; the material of the guard ring dielectric layer 109 is typically an oxide layer, and the inner side of the guard ring dielectric layer 109 typically extends into the transition region.

A polysilicon field plate 105a is also formed on top of the guard ring dielectric layer 109 in the transition region, the polysilicon field plate 105a being typically formed simultaneously with the polysilicon gate 105, i.e., by patterning the polysilicon.

The superjunction device also includes a source and gate electrode formed by patterning the front side metal layer 112, the gate electrode including a gate pad (gate pad), a gate bus (gate bus), and a gate finger (gate finger). Typically, the front side metal layer 112 comprises a plurality of layers, only one of which is shown in fig. 2A.

The channel region and the source region 107 are connected to the source via a top corresponding contact hole 112. The contact hole 112 penetrates the interlayer film 110.

The P-ring 106a is connected to the source through a top corresponding contact hole 112. A P-type heavily doped contact region 108 is formed at the bottom of the contact hole 112 corresponding to the source region 107 and the P-type ring 106a, and ohmic contact between the contact hole 112 and the channel region corresponding to the bottom and the P-type ring 106a is achieved through the contact region 108.

The polysilicon field plate 105a is connected to the gate through a top corresponding contact hole 112. The contact hole 112 at the top of the polysilicon gate 105 is not shown in the corresponding cross section of fig. 2A, and in other cross sections, the polysilicon gate 105 may be connected to the corresponding gate bus line or the gate finger through the contact hole 112 at the top, and finally connected to the gate pad through the gate bus line or the gate finger.

A cutoff ring 107a composed of an n+ region is also formed at the outermost side of the termination region, and the cutoff ring 107a corresponds to the cutoff ring 21 in fig. 1.

The superjunction device further includes the following back side structure:

the drain region formed by the thinned back surface of the semiconductor substrate 101, wherein the back surface implantation or the increase of n+ back surface ion implantation is not required when the semiconductor substrate 101 is heavily doped with N type; if the semiconductor substrate 101 is not heavily doped with N-type, then n+ back side ion implantation needs to be added to make the doping of the drain region satisfactory.

A drain electrode composed of a back metal layer 113 is formed on the back of the drain region.

In fig. 2A, region 1 is located on the left side of line AA, region 2 is located between line AA and line BB, and region 3 is located on the right side of line BB. Since only the cross-sectional structure of the trench gate superjunction device partial region is shown in fig. 2A, there is a certain omission, for example, a certain omission at the dashed line AA between the 1 region and the 2 region. To facilitate understanding, circuit connections associated with the source, drain, and gate are added to fig. 2A, and these circuit connections merely represent electrical connections between the metal layers, and are not intended to limit the specific connection structure of the metal layers. For example, in the cross-section of fig. 2A, the front metal layer 112 on top of the source region 107 of the current flow region and the front metal layer 112 on top of the P-type ring 106a of the transition region, although not shown directly contacting each other, can generally be directly contacted together and be of unitary construction, i.e., the front metal layer 112 on top of the source region 107 of the current flow region and the front metal layer 112 on top of the P-type ring 106a of the transition region can be contacted together without the need for additional contact holes and additional metal layers.

Also, in fig. 2A, the front metal layer 112 on top of the polysilicon field plate 105a is a metal that serves as a gate bus, the gate bus and the polysilicon gate 105 of the gate trench of the current flow region cannot be directly contacted, and an electrical connection needs to be achieved between the gate bus and the polysilicon gate 105 through the contact hole 112, and in fig. 2A, the circuit connection related to the gate shows that the polysilicon gate 105 of the current flow region and the front metal layer 112 on top of the polysilicon field plate 105a are electrically connected together.

Disclosure of Invention

The technical problem to be solved by the invention is to provide the trench gate superjunction device, which can eliminate the adverse effect of the position deviation of the bottom surfaces of different gate trenches on the bottom surface of the gate conductive material layer, so that the consistency of the length of a conductive channel and the length of an accumulation region of the device can be improved, and the consistency of the performance of the device can be improved. Therefore, the invention also provides a manufacturing method of the trench gate superjunction device.

In order to solve the technical problems, the middle area of the trench gate superjunction device provided by the invention is a current flowing area, a terminal area surrounds the periphery of the current flowing area, and a transition area is positioned between the current flowing area and the terminal area.

A superjunction structure formed by alternately arranging first conductivity type pillars and second conductivity type pillars is formed on a semiconductor substrate.

The super junction structure is formed in the current flow region, and a plurality of device unit structures of super junction devices in parallel structures are formed at the top of the super junction structure of the current flow region.

The trench gate of each device unit structure is formed by laminating a bottom dielectric layer, a gate dielectric layer and a gate conductive material layer which are formed in the gate trench.

The gate trench is wholly or partially located in the first conductivity type column, the bottom dielectric layer is formed at the bottom of the gate trench, the gate dielectric layer is formed at the side face of the gate trench, and the gate conductive material layer completely fills the gate trench where the bottom dielectric layer and the gate dielectric layer are formed.

The channel region of each device unit structure is composed of a second conductive type well region formed on the surface of the super junction structure, the grid conductive material layer penetrates through the channel region in the longitudinal direction, the surface of the channel region covered by the side surface of the grid conductive material layer located in the first conductive type column is used for forming a conductive channel, and the surface of the first conductive type column below the conductive channel and covered by the side surface of the grid conductive material layer is used for forming an accumulation region.

A source region composed of a heavily doped region of the first conductivity type is formed on a surface of the channel region.

A second conductivity type ring is formed in the transition region.

Each of the gate trenches is formed by the same trench etching process, a top surface of each of the gate trenches is leveled, a bottom surface of each of the gate trenches is not leveled, and a positional deviation of the bottom surface of each of the gate trenches is determined by the trench etching process.

The bottom dielectric layers are formed by etching the first dielectric layers which are completely filled in the gate trenches from top to bottom, the etching process of the first dielectric layers enables the top surfaces of the bottom dielectric layers to be leveled, and the thickness deviation of the bottom dielectric layers just compensates the position deviation of the bottom surfaces of the gate trenches.

The bottom surface of the gate conductive material layer is defined by the top surface of the bottom dielectric layer such that the bottom surface of each of the gate conductive material layers is leveled, thereby improving the uniformity of the length of the conductive channel and the length of the accumulation region.

The etching process of the first dielectric layer is a graphical etching process, and the etching process of the first dielectric layer simultaneously forms a protective ring dielectric layer; the guard ring dielectric layer covers at least part of the terminal region and extends into the transition region, the inner side surface of the guard ring dielectric layer is located on the transition region, the inner side surface of the guard ring dielectric layer divides the transition region into a first transition region and a second transition region, the first transition region is located on the inner side of the inner side surface of the guard ring dielectric layer, and the second transition region is located on the outer side of the inner side surface of the guard ring dielectric layer.

A further improvement is that the guard ring dielectric layer is also formed in the gate finger forming region and the gate pad forming region.

The first dielectric layer is an oxide layer.

In a further improvement, the first dielectric layer is formed by laminating a thermal oxide layer and a CVD deposited oxide layer.

A further improvement is that the gate conductive material layer is a polysilicon gate.

The polysilicon gate is further improved by performing full back etching or patterned etching on the first polysilicon layer.

When the polysilicon gate is formed by carrying out patterned etching on the first polysilicon layer, the patterned etching of the first polysilicon layer also simultaneously forms a first polysilicon field plate or the patterned etching of the first polysilicon layer also simultaneously forms the first polysilicon field plate and a second polysilicon field plate; the first polysilicon field plate is located on the guard ring dielectric layer of the second transition region, the second polysilicon field plate is located on the guard ring dielectric layer of the terminal region, and the second polysilicon field plate is of a floating structure.

A further improvement is that the superjunction device further includes a source and a gate patterned from the front side metal layer, the gate including a gate pad (gate pad), a gate bus (gate bus), and a gate finger (gate finger).

The channel region and the source region are connected to the source electrode through a top corresponding contact hole.

The second conductivity type ring is connected to the source through a contact hole on top and in the first transition region.

The first polysilicon field plate is connected to the grid electrode through a corresponding contact hole at the top.

A further improvement is that the gate trench also extends into the first transition region and the gate conductive material layer also extends into the second transition region and into contact with the first polysilicon field plate in a length direction along a top view of the gate trench.

In order to solve the technical problems, in the manufacturing method of the trench gate superjunction device, the superjunction device is divided into a current flowing region, a transition region and a terminal region, wherein the middle region is the current flowing region, the terminal region surrounds the periphery of the current flowing region, and the transition region is positioned between the current flowing region and the terminal region; the method comprises the following steps:

and step one, performing ion implantation of the second conduction type ring to form the second conduction type ring in the transition region.

Step two, forming a super junction structure formed by alternately arranging first conductive type columns and second conductive type columns on a semiconductor substrate; the current flow region has the superjunction structure therein.

Step three, forming a trench gate of each device unit structure of the superjunction device, wherein each device unit structure is formed at the top of the superjunction structure of the current flow area and is in a parallel structure, and the formation process of the trench gate comprises the following sub-steps:

step 31, forming a grid groove corresponding to each device unit structure by a patterned groove etching process; the gate trenches are located in the first conductivity type pillars in whole or in part, top surfaces of the gate trenches are leveled, bottom surfaces of the gate trenches are not leveled, and positional deviations of the bottom surfaces of the gate trenches are determined by the trench etching process.

Step 32, forming a bottom dielectric layer in the gate trench, including:

and forming a first dielectric layer, wherein the first dielectric layer completely fills the gate trench and the top surface of the first dielectric layer is flat.

And carrying out an etching process on the first dielectric layer from top to bottom to form the bottom dielectric layer only in the bottom area of the gate trench, wherein the etching process of the first dielectric layer enables the top surface of each bottom dielectric layer to be flat, and enables the thickness deviation of each bottom dielectric layer to exactly compensate the position deviation of the bottom surface of each gate trench.

And step 33, forming a gate dielectric layer on the side surface of the gate trench.

And step 34, filling a gate conductive material layer in the gate trench, wherein the bottom surface of the gate conductive material layer is determined by the top surface of the bottom dielectric layer, so that the bottom surface of each of the electrode conductive material layers is leveled.

Step four, injecting a second conductive type well into the surface of the super junction structure to form a second conductive type well region, wherein a channel region of each device unit structure is formed by the second conductive type well region, and the grid conductive material layer longitudinally penetrates through the channel region; the channel region surface covered by the side of the gate conductive material layer located in the first conductive type column is used to form a conductive channel, and the surface of the first conductive type column below the conductive channel covered by the side of the gate conductive material layer is used to form an accumulation region; the bottom surface of each of the layers of polar conductive material is flattened to promote uniformity of the length of the conductive channel and the length of the accumulation region.

And fifthly, performing first-conductivity-type heavily-doped ion implantation to form a source region on the surface of the channel region.

In a further improvement, in step 32, the etching process of the first dielectric layer is a patterned etching process, and the etching process of the first dielectric layer forms a protection ring dielectric layer at the same time; the guard ring dielectric layer covers at least part of the terminal region and extends into the transition region, the inner side surface of the guard ring dielectric layer is located on the transition region, the inner side surface of the guard ring dielectric layer divides the transition region into a first transition region and a second transition region, the first transition region is located on the inner side of the inner side surface of the guard ring dielectric layer, and the second transition region is located on the outer side of the inner side surface of the guard ring dielectric layer.

The first dielectric layer is an oxide layer.

In a further improvement, in step 34, the gate conductive material layer is a polysilicon gate.

In a further improvement, in step 34, the substep of forming the layer of gate conductive material includes:

a first polysilicon layer is formed that completely fills and extends the gate trench out of the gate trench.

Carrying out overall back etching on the first polysilicon layer to form the polysilicon gate; or performing graphical etching on the first polysilicon layer to form the polysilicon gate.

Further improvement is that after the fifth step, the method further comprises: forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode, wherein the grid electrode comprises a grid electrode pad, a grid electrode bus and a grid electrode finger;

the channel region and the source region are connected to the source electrode through the contact hole corresponding to the top;

the second conductivity type ring is connected to the source electrode through a contact hole on top and located in the first transition region;

The further improvement is that the etching process of the first dielectric layer adopts wet etching.

The bottom dielectric layer in the grid groove is specially arranged, the characteristic that the bottom dielectric layer is formed by etching the first dielectric layer which is completely filled in the grid groove from top to bottom is utilized, so that the top surface of the bottom dielectric layer is not influenced by the bottom surface of the grid groove, the top surface of the bottom dielectric layer is completely determined by the etching process of the first dielectric layer, the height of the top surface of the bottom dielectric layer in the grid groove with uneven bottom surface is enabled to be equal, namely the height difference of the top surfaces of the bottom dielectric layers in different grid grooves is smaller or not smaller than the height difference of the bottom surfaces of the grid groove, but the thickness of each bottom dielectric layer is different, and the position difference of the bottom surface of the grid groove is exactly compensated by the thickness difference of the bottom dielectric layer; the bottom surface of the grid electrode conductive material layer formed on the bottom dielectric layer is the bottom surface of the bottom dielectric layer, so that adverse effects of uneven bottom surface of each grid electrode groove on the bottom surface of each electrode conductive material layer can be eliminated, the bottom surfaces of the electrode conductive material layers are leveled, and accordingly the consistency of the length of the conductive channel and the length of the accumulation area is improved, and particularly the consistency of the length of the accumulation area is improved, and the consistency of device performance is improved.

Compared with the etching process for forming the gate trench, the etching process for the first dielectric layer in the gate trench is a top-to-bottom etching process, is easy to control, and can obtain the required bottom dielectric layers by adopting wet etching and controlling time, so that the topography of the top surface of each bottom dielectric layer is good, the position difference of the top surface between each bottom dielectric layer is reduced to the minimum, and finally, the performance consistency of the device is improved to the optimal level.

The first dielectric layer of the bottom dielectric layer can be used as the protective ring dielectric layer at the same time, so that the bottom dielectric layer can be formed without adding extra photoetching technology and can be compatible with the existing technology without forming the bottom dielectric layer, and the invention has the advantages of simple technology and low technology cost

The first dielectric layer of the bottom dielectric layer can be formed by stacking a thermal oxide layer and a CVD deposited oxide layer, wherein the thermal oxide layer can replace a sacrificial oxide layer to eliminate defects on the inner side surface of the gate trench, so that the growth and removal process of the sacrificial oxide layer for removing the defects on the inner side surface of the gate trench can be eliminated, and the cost for carrying out the growth and removal process of the sacrificial oxide layer can be saved.

The invention is convenient to control the position of the top surface of the bottom dielectric layer, for example, the position of the top surface of the bottom dielectric layer can be controlled by controlling the etching time of the etching process of the first dielectric layer, so that the invention can thicken the bottom dielectric layer, and the gate-drain capacitance of the device can be reduced by thickening the bottom dielectric layer; meanwhile, after the bottom dielectric layer is thickened, the length of the accumulation area can be reduced, so that the gate-drain capacitance of the device can be further reduced.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

FIG. 1 is a top view of a prior art superjunction device;

FIG. 2A is a schematic cross-sectional view of a prior art trench gate superjunction device;

FIG. 2B is an enlarged view of the current flow region of FIG. 2A;

fig. 3A is a schematic cross-sectional view of a trench-gate superjunction device according to a first embodiment of the present invention;

fig. 3B is an enlarged partial view of a top view of a trench gate superjunction device of the first embodiment of the present invention;

fig. 4A is a schematic cross-sectional view of a trench-gate superjunction device according to a second embodiment of the present invention;

fig. 4B is an enlarged partial view of a top view of a trench-gate superjunction device according to a second embodiment of the present invention;

Fig. 5 is a flow chart of a method of fabricating a trench gate superjunction device according to a first embodiment of the present invention;

FIGS. 6A-6I are schematic cross-sectional views of a device in a current flow region at various steps in a method of fabricating a trench gate superjunction device according to a first embodiment of the present invention;

fig. 7 is a flow chart of a method of fabricating a trench gate superjunction device according to a second embodiment of the present invention.

Detailed Description

FIG. 3A is a schematic cross-sectional view of a trench-gate superjunction device according to a first embodiment of the present invention; as shown in fig. 3B, a partial enlarged view of a top view of a trench gate superjunction device according to a first embodiment of the present invention; in the trench gate superjunction device of the first embodiment of the present invention, the middle region is a current flow region, the terminal region surrounds the periphery of the current flow region, and the transition region is located between the current flow region and the terminal region. In fig. 3A, the current flow region is region 1, and the transition region is divided into a first transition region and a second transition region, wherein the first transition region is region 2a, and the second transition region is region 2 b; the terminal region is also divided into a 3a region and a 3b region. In fig. 3A, the 1 region is located on the left side of line CC, the 2a region is located between line CC and line DD, the 2b region is located between line DD and line EE, the 3A region is located between line EE and line FF, and the 3b region is located between line FF and line GG.

A superjunction structure formed by alternately arranging the first conductive type pillars 202a and the second conductive type pillars 203 is formed on the semiconductor substrate 201.

Typically, an epitaxial layer 202 of the first conductivity type is further formed on the surface of the semiconductor substrate 201, the superjunction structure is formed in the epitaxial layer 202, the second conductivity type pillars 203 are composed of the epitaxial layer of the second conductivity type filled in the trenches formed in the epitaxial layer 202, and the first conductivity type pillars 202a are composed of the epitaxial layer 202 between the second conductivity type pillars 203.

The semiconductor substrate 201 is typically a silicon substrate, and the epitaxial layer 202 is a silicon epitaxial layer.

The super junction structure is formed in the current flow region, and a plurality of device unit structures of super junction devices in parallel structures are formed at the top of the super junction structure of the current flow region. In a first embodiment of the invention, the superjunction structure also extends into the transition region and the termination region.

The trench gate of each device cell structure is formed by stacking a bottom dielectric layer 205, a gate dielectric layer 206, and a gate conductive material layer 207 formed in the gate trench 204.

The gate trench 204 is wholly or partially located in the first conductivity type pillar 202a, the bottom dielectric layer 205 is formed at the bottom of the gate trench 204, the gate dielectric layer 206 is formed at the side of the gate trench 204, and the gate conductive material layer 207 completely fills the gate trench 204 with the bottom dielectric layer 205 and the gate dielectric layer 206.

The channel region of each device cell structure is composed of a second conductivity type well region 208 formed on the surface of the superjunction structure, the gate conductive material layer 207 penetrates the channel region in the longitudinal direction, the channel region surface covered by the side surface of the gate conductive material layer 207 located in the first conductivity type column 202a is used to form a conductive channel, and the surface of the first conductivity type column 202a below the conductive channel covered by the side surface of the gate conductive material layer 207 is used to form an accumulation region.

A source region 209 composed of a heavily doped region of the first conductivity type is formed at a surface of the channel region.

A second conductivity type ring is formed in the transition region. In fig. 3A, the second conductivity type rings in the region 2a are individually marked with marks 208a and the second conductivity type rings in the region 2b are individually marked with marks 208b, respectively, depending on the positions where the second conductivity type rings are located. In the first embodiment of the present invention, doped impurities of the second conductivity type well region 208 are further stacked in the second conductivity type ring 208 a; the second conductive-type well region 208 is not overlapped with the impurity doped in the second conductive-type ring 208 a.

Each of the gate trenches 204 is formed by the same trench etching process, a top surface of each of the gate trenches 204 is leveled, a bottom surface of each of the gate trenches 204 is not leveled, and a positional deviation of the bottom surface of each of the gate trenches 204 is determined by the trench etching process. Referring to fig. 6G, the line HH represents the bottom surface position of each of the gate trenches 204, but in reality, the bottom surface position of each of the gate trenches 204 fluctuates up and down along the line HH, some of the bottom surface positions of the gate trenches 204 are located above the line HH, and some of the bottom surface positions of the gate trenches 204 are located below the line HH, and the position deviations are different in magnitude and are completely determined by the trench etching process.

The bottom dielectric layer 205 is formed by etching the first dielectric layer 304 completely filled in the gate trench 204 from top to bottom, and the etching process of the first dielectric layer 304 makes the top surface of each bottom dielectric layer 205 be flat, and makes the thickness deviation of each bottom dielectric layer 205 exactly compensate the position deviation of the bottom surface of each gate trench 204. Also, referring to fig. 6G, the line II represents the top surface position of each bottom dielectric layer 205, and in the first embodiment of the present invention, the top surface position of each bottom dielectric layer 205 is on the line II or the deviation value between the top surface position of each bottom dielectric layer 205 and the line II is small, i.e. within the required accuracy range. The line JJ represents the top surface position of each of the gate trenches 204, and the top surface position of each of the gate trenches 204 is on the line JJ.

The bottom surface of the gate conductive material layer 207 is defined by the top surface of the bottom dielectric layer 205 such that the bottom surface of each of the gate conductive material layers is leveled, thereby improving the uniformity of the length of the conductive channel and the length of the accumulation region, and in particular, the uniformity of the length of the accumulation region. As can be seen from fig. 3A, the length of the conductive channel is the distance between the bottom surface of the source region 209 and the bottom surface of the second conductivity type well region 208; the length of the accumulation region is the distance between the second conductivity type well region 208 and the top surface of the bottom dielectric layer 205, and since the top surface of the bottom dielectric layer 205 in each gate trench 204 is located at the same level, the lengths of the accumulation regions corresponding to the two sides of each gate trench 204 are identical.

In the first embodiment of the present invention, the etching process of the first dielectric layer 304 is a patterned etching process, and the etching process of the first dielectric layer 304 simultaneously forms the guard ring dielectric layer 205a; the first dielectric layer 304 is shown in fig. 6E. The guard ring dielectric layer 205a covers at least a portion of the termination region and extends into the transition region, an inner side surface of the guard ring dielectric layer 205a is located on the transition region, and the inner side surface of the guard ring dielectric layer 205a divides the transition region into a first transition region, i.e., a 2a region, located inside an inner side surface of the guard ring dielectric layer 205a, and a second transition region, i.e., a 2b region, located outside the inner side surface of the guard ring dielectric layer 205 a.

The guard ring dielectric layer 205a is also formed in the gate finger formation region and the gate pad formation region.

The first dielectric layer 304 is an oxide layer. In some preferred embodiments, the first dielectric layer 304 is formed by stacking a thermal oxide layer and a CVD deposited oxide layer.

The gate conductive material layer 207 is a polysilicon gate.

In the first embodiment of the present invention, the polysilicon gate is formed by performing patterned etching on the first polysilicon layer.

When the polysilicon gate is formed by performing patterned etching on the first polysilicon layer, the patterned etching of the first polysilicon layer also simultaneously forms the first polysilicon field plate 207a or the patterned etching of the first polysilicon layer also simultaneously forms the first polysilicon field plate 207a and the second polysilicon field plate (not shown). The first polysilicon field plate 207a is located on the guard ring dielectric layer 205a of the second transition region, and in fig. 3A, the first polysilicon field plate 207a extends into the region 3A of the termination region.

The second polysilicon field plate is located in the guard ring dielectric layer 205a of the termination region and is in a floating structure.

The superjunction device also includes a source electrode and a gate electrode formed by patterning the front side metal layer 213, the gate electrode including a gate pad, a gate bus line, and a gate finger. Typically, the front side metal layer 213 comprises a plurality of layers, only one of which is shown in fig. 3A.

The channel region and the source region 209 are connected to the source through a top corresponding contact hole 212. The contact hole 212 penetrates the interlayer film 211.

The second conductivity type ring is connected to the source through a contact hole 212 on top and in the first transition region, region 2 a. Namely: in fig. 3A, the second conductivity type ring is connected to the source through a contact hole 212 located on top of the second conductivity type ring 208a in region 2 a. A second conductive type heavily doped contact region 210 is formed at the bottom of the contact hole 212 corresponding to the source region 209 and the second conductive type ring 208a, and ohmic contact between the contact hole 212 and the channel region corresponding to the bottom and the second conductive type ring 208a is achieved through the contact region 210.

In some embodiments, the first transition region, region 2a, wherein the second conductivity type ring 208a is a deeper P-type region formed by a P-type ring implant, is formed in conjunction with a P-type well implant. The region having the second conductivity type ring 208a can have a contact hole and a metal thereon, which is connected to the source metal of the charge flow region.

In the second transition region, region 2b, the second conductive-type ring 208b is formed solely from the region where the P-type ring is implanted, and may have an oxide film, polysilicon, a contact hole, and metal thereon. The metal is isolated from the metal of the source and is connected to the metal of the gate pad. This metal may extend to the 3a region of the termination region.

In some embodiments, there may or may not be floating polysilicon, floating metal field plates in region 3b of the termination region. Outside the 3b region of the termination region there is an N + implant region in the substrate as a stop ring.

The first polysilicon field plate 207a is connected to the gate through a top corresponding contact hole 212. The contact hole 212 on top of the gate conductive material layer 207 is not shown in the corresponding cross section of fig. 3A, and in other cross sections, the gate conductive material layer 207 may be connected to the corresponding gate bus line or the gate finger through the contact hole 212 on top, and finally connected to the gate pad through the gate bus line or the gate finger.

In the embodiment of the present invention, since only the cross-sectional structure of the partial region of the trench gate superjunction device is shown in fig. 3A and omitted to some extent, in order to facilitate understanding, circuit wires related to the source, the drain and the gate are added in fig. 3A, and these circuit wires only represent the electrical connection relationship of each metal layer, and do not specifically limit the specific connection structure of each metal layer. For example, in the cross-section of fig. 3A, the front metal layer 213 on top of the source region 209 of the current flow region and the front metal layer 213 on top of the second conductivity type ring 208a of the 2a region of the transition region are not shown directly contacting each other, but in practice can be directly contacted together and have a unitary structure, i.e., the front metal layer 213 on top of the source region 209 of the current flow region and the front metal layer 213 on top of the second conductivity type ring 208a of the 2a region of the transition region can be contacted together without the need for additional contact holes 212 and additional metal layers. In addition, the second conductive type rings 208a and 208b of the second conductive type rings 208a and 2b of the transition region are actually of a unitary structure, and the second conductive type rings 208a and 208b are not directly shown in the cross-section as a part of the region is omitted at the dividing line DD, but the second conductive type rings 208a and 208b are actually directly contacted together.

Also, in fig. 3A, the front metal layer 213 on top of the first polysilicon field plate 207a is a metal that is used as a gate bus, and the gate bus and the polysilicon gate 207 of the gate trench 204 of the current flow region cannot directly form a contact, and need to be electrically connected through polysilicon and a contact hole 212, and in fig. 3A, the circuit connection related to the gate shows that the polysilicon gate 207 of the current flow region and the front metal layer 213 on top of the first polysilicon field plate 207a are electrically connected together.

As shown in fig. 3B, the gate trench 204 also extends into the first transition region and the gate conductive material layer 207 also extends into the second transition region and contacts the first polysilicon field plate 207a in a length direction along a top view of the gate trench 204. In fig. 3B, the area of the wire frame 401 is area 1, the wire frame 402 corresponds to the inner side surface of the guard ring dielectric layer 205a, and fig. 3A is a cross-sectional view along the line LL; in fig. 3B, the length direction along the gate trench 204 is X direction, the width direction is Y direction, the X direction is also the length direction of the first conductive type pillar 202a and the second conductive type pillar 203, the 2a region and the 2B region are divided into two regions according to the X direction and the Y direction, respectively, the 2ax region and the 2ay region, and the 2bx region and the 2by region, the 2ax region is located between the line CCX and the line DDX, the 2bx region is located between the line DDX and the line EEX, the 2ay region is located between the line CCY and the line DDY, and the 2by region is located between the line DDY and the line EEY. In fig. 3A, the contact hole 212 on top of the second conductivity type ring 208a is in the region of 2ax in fig. 3B. In fig. 3B, the gate trench 204 extends into the 2ay region, and the gate conductive material layer 207 also extends into the 2by region and contacts the first polysilicon field plate 207 a.

In fig. 3B, a trench gate (trench gate) is formed in the N region of the PN column, i.e., the first conductive type column 202a, and a contact hole 212 and an N-type source region 209 are formed between the two sides of the trench gate and the P-type column, i.e., the second conductive type column 203, so that a certain distance, for example, more than 5 micrometers, can be maintained between the region boundary of the N-type source region 209 and the region boundary of the P-type ring 208a, i.e., the inner boundary of the 2a region, to ensure that Vth of the NMOSFET is not affected by the P-type ring 208a, thereby improving consistency of Vth and also contributing to EAS.

In fig. 3B, the 2ax region, the 2ay region, the 2bx region, and the 2by region are regions formed by the P-type ring 208a, and at least a portion of the 2ax region has a contact hole, so that the P-type ring 208a is connected to the source metal, and of course, there may be no contact hole or no contact hole in part in order to obtain different gate resistances.

The trench gate is left with polysilicon along the X-direction at its end portions and is connected to the bulk polysilicon of the transition region, i.e. to the first polysilicon field plate 207 a.

As shown in fig. 3B, in the P-type pillar, a contact hole 212 may be provided in the charge flow region, and the contact hole 212 is connected to the source region metal through the p+ contact region, so that EAS of the device may be improved; it is also possible to provide a contact hole in the 2a region of the transition region and connect the source metal only, so that the P-type pillar in the chip charge flow region is actually in a half floating (half floating) state, and the change curve of Cgd Vs Vds is improved, so that the curve is relaxed, the switching softness of the device is improved, vs represents the source voltage, and Vds represents the source drain voltage.

In some embodiments, instead of providing a contact hole in the entire P-type pillar, the P-type pillar is completely floating, and polysilicon, i.e., the first polysilicon field plate 207a, is provided only in the region 2a of the transition region, so that the top point of the P-type pillar in the region 2a is affected by the gate potential, which is achieved by the parasitic capacitance formed by the gate poly-ox-P-type pillar top Si, where gate poly is the first polysilicon field plate 207a, ox connected to the gate, represents the oxide layer of the interlayer film, which improves the change curve of Cgd Vs Vds, eases the curve, and thus improves the switching softness of the device.

The trench gate superjunction device of the first embodiment of the invention is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments can also be: the trench gate superjunction device of the first embodiment of the invention is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

The trench gate superjunction device of the first embodiment of the present invention is a MOS transistor, and the semiconductor substrate 201 is thinned and a heavily doped drain region of the first conductivity type is formed. In some embodiments, the semiconductor substrate 201 is heavily doped with the first conductivity type, and the drain region is directly formed by the thinned semiconductor substrate 201; in other embodiments, the semiconductor substrate 201 is thinned and then subjected to back ion implantation heavily doped with the first conductivity type to form the drain region.

A back metal layer 214 is also formed on the back of the drain region and the drain is composed of the back metal layer 214.

The first embodiment of the present invention makes a special setting on the bottom dielectric layer 205 in the gate trench 204, and uses the characteristic that the bottom dielectric layer 205 is formed by etching the first dielectric layer 304 completely filling the gate trench 204 from top to bottom, so that the top surface of the bottom dielectric layer 205 is not affected by the bottom surface of the gate trench 204, and the top surface of the bottom dielectric layer 205 is completely determined by the etching process of the first dielectric layer 304, so that the height of the top surface of the bottom dielectric layer 205 in the gate trench 204 with uneven bottom surface is equal, that is, the difference in height of the top surface of the bottom dielectric layer 205 in different gate trenches 204 is smaller or not enough to meet the precision requirement and is smaller than the difference in height of the bottom surface of the gate trench 204, but the thickness of each bottom dielectric layer 205 will be different, and the difference in thickness of the bottom dielectric layer 205 is used to exactly compensate the difference in position of the bottom surface of the gate trench 204; the bottom surface of the gate conductive material layer 207 formed on the bottom dielectric layer 205 is the bottom surface of the bottom dielectric layer 205, so the adverse effect of the uneven bottom surface of each gate trench 204 on the bottom surface of each electrode conductive material layer can be eliminated, the bottom surface of each electrode conductive material layer is leveled, and the uniformity of the length of the conductive channel and the length of the accumulation region, particularly the uniformity of the length of the accumulation region, can be improved, so that the uniformity of the device performance can be improved.

Compared to the etching process for forming the gate trench 204, the etching process for the first dielectric layer 304 in the gate trench 204 according to the first embodiment of the present invention is a top-to-bottom etching process, which is easier to control, for example, by using a wet etching process and by controlling the time to obtain the required bottom dielectric layers 205, the topography of the top surface of each bottom dielectric layer 205 is better, so that the difference in the positions of the top surfaces between each bottom dielectric layer 205 is minimized, and finally, the performance uniformity of the device is improved to an optimal level.

The first dielectric layer 304 of the bottom dielectric layer 205 of the first embodiment of the present invention can be used as the guard ring dielectric layer 205a at the same time, so that the bottom dielectric layer 205 of the present invention can be formed without adding additional photolithography process and is compatible with the existing process of not forming the bottom dielectric layer 205, and the first embodiment of the present invention has the advantages of simple process and low process cost

The first dielectric layer 304 of the bottom dielectric layer 205 of the first embodiment of the present invention can be formed by stacking a thermal oxide layer and a CVD deposited oxide layer, wherein the thermal oxide layer can replace the sacrificial oxide layer to eliminate the defects on the inner side surface of the gate trench 204, so that the growth and removal process of the sacrificial oxide layer for removing the defects on the inner side surface of the gate trench 204 can also be eliminated, and the cost for performing the growth and removal process of the sacrificial oxide layer can be saved.

Because the first embodiment of the present invention facilitates controlling the position of the top surface of the bottom dielectric layer 205, for example, the position of the top surface of the bottom dielectric layer 205 can be controlled by controlling the etching time of the etching process of the first dielectric layer 304, this makes the first embodiment of the present invention capable of thickening the bottom dielectric layer 205, thereby reducing the gate-drain capacitance of the device by thickening the bottom dielectric layer 205; meanwhile, after the bottom dielectric layer 205 is thickened, the length of the accumulation region is reduced, which can further reduce the gate-drain capacitance of the device.

FIG. 4A is a schematic cross-sectional view of a trench-gate superjunction device according to a second embodiment of the present invention; as shown in fig. 4B, a partial enlarged view of a top view of a trench gate superjunction device according to a second embodiment of the present invention; the trench gate superjunction device of the second embodiment of the present invention differs from the trench gate superjunction device of the first embodiment of the present invention in that:

in the trench gate superjunction device of the second embodiment of the present invention, the polysilicon gate is formed by performing full back etching on the first polysilicon layer, so that the first polysilicon field plate is not formed in the 2b region, and the second polysilicon field plate is not formed in the terminal region, but a photoresist for defining the first polysilicon field plate or the second polysilicon field plate can be saved.

In fig. 4A, although the first polysilicon field plate is not formed any more in region 2b, a metal field plate consisting of the front side metal layer 212 is formed, which is still connected to the gate electrode.

Referring to fig. 5, a flowchart of a method for manufacturing a trench gate superjunction device according to a first embodiment of the present invention is shown, and the flowchart is described in terms of photolithography process levels in fig. 5; fig. 6A to 6I are schematic cross-sectional views of a device in a current flow region in each step of a method for manufacturing a trench gate superjunction device according to a first embodiment of the present invention; in the manufacturing method of the trench gate superjunction device, the superjunction device is divided into a current flowing region, a transition region and a terminal region, wherein the middle region is the current flowing region, the terminal region surrounds the periphery of the current flowing region, and the transition region is positioned between the current flowing region and the terminal region. In fig. 3A, the current flow region is region 1, and the transition region is divided into a first transition region and a second transition region, wherein the first transition region is region 2a, and the second transition region is region 2 b; the terminal region is also divided into a 3a region and a 3b region. In fig. 3A, the 1 region is located on the left side of line CC, the 2a region is located between line CC and line DD, the 2b region is located between line DD and line EE, the 3A region is located between line EE and line FF, and the 3b region is located between line FF and line GG. The method comprises the following steps:

Step one corresponds to step S102 in fig. 5, namely, "P-type guard ring photo & IMP". The trench gate superjunction device formed by the method for manufacturing the trench gate superjunction device of the first embodiment of the invention is an N-type device, the first conductive type is N-type, the second conductive type is P-type, and the second conductive type ring is a P-type ring. In the first step, the second conductive type ring, i.e., the P-type ring, is a ring structure surrounding the current flow region, and thus is defined by a photolithography process, wherein photo represents photolithography, and IMP represents ion implantation, i.e., the first step is to perform the photolithography and ion implantation process of the P-type ring.

In the method of the first embodiment of the invention, the ions of the P-type ring, namely the second conductive type ring, are implanted in the transition region, comprising the first transition region and the second transition region, P-type impurities such as B are implanted under the gate pad and the gate finger, the implantation energy is 60keV-120keV, and the implantation dosage is 2E12cm ^-2 -5E13cm ^-2 。

Because the forming process of the P-type ring is before the subsequent super junction structure forming process, an annealing process with high temperature and long time can be adopted for annealing activation, so that the P-type region of the P-type ring is pushed deeper, and the parameters of the annealing process are as follows: the temperature is 1000-1150 ℃ and the time is 60-300 minutes, and specific parameters can be adjusted according to the depth of the P-type ring 208a to be formed: for example, the temperature can be set at 1100℃for 60 to 300 minutes, and the temperature can be set at 1150℃for 30 to 60 minutes. Since the annealing process of the P-type ring is completed before the subsequent second conductivity type pillar 203, i.e., the P-type pillar, is formed, the impurity interdiffusion of the PN pillar is not affected, and thus the Rsp of the device is not affected.

Generally, a first Zero layer lithography is required to form alignment or test marks in the scribe line of the semiconductor substrate 201 before the first step, which corresponds to step S101 in fig. 5, i.e., "Zero photo & etch", where Zero represents Zero layer lithography, etch represents etching, and Zero photo & etch represents forming Zero layer marks by a lithography definition plus etching process.

Step two, forming a super junction structure formed by alternately arranging the first conductive type pillars 202a and the second conductive type pillars 203 on the semiconductor substrate 201; the current flow region has the superjunction structure therein. In the method of the first embodiment of the present invention, the transition region and the termination region each have the superjunction structure therein.

Step two corresponds to step S103 in fig. 5, namely "P pillar photo & etch", the second conductivity type pillar is a P pillar, trench represents a Trench of the P pillar, and P pillar photo & etch represents a Trench of the P pillar formed by using a photolithography definition plus etching process.

As shown in fig. 6A, first, an epitaxial layer 202 doped with a first conductivity type is further formed on the surface of the semiconductor substrate 201, and a hard mask layer 301 is formed on the surface of the epitaxial layer 202.

Thereafter, a formation region of the trench 302 of the P pillar is defined by photolithography and the epitaxial layer 202 is etched to form the trench 302.

Thereafter, the second conductivity-type epitaxial layer 303 is filled to completely fill the trench 302, and the second conductivity-type epitaxial layer 303 also extends onto the surface of the hard mask layer 301 outside the trench 302. Typically, the semiconductor substrate 201 is a silicon substrate, the epitaxial layer 202 is a silicon epitaxial layer, and the second conductivity type epitaxial layer 303 is also a silicon epitaxial layer. The resistivity or impurity concentration of this second conductivity type epitaxial layer 303 is selected to provide a good charge balance with the impurities in the N-type epitaxial layer 202 to achieve the desired reverse breakdown voltage capability.

As shown in fig. 6C, chemical mechanical polishing is performed to polish away the second conductivity type epitaxial layer 303 on the top surface of the epitaxial layer 202, and the hard mask layer 301 is also polished away; the second conductivity type epitaxial layer 302 is located only in the trench 302 and constitutes the second conductivity type pillars 203, the epitaxial layer 202 between the second conductivity type pillars 203 constitutes first conductivity type pillars 202a, and the superjunction structure is formed by alternately arranging the first conductivity type pillars 202a and the second conductivity type pillars 203.

Step 31, as shown in fig. 6D, performing a patterned trench etching process to form a gate trench 204 corresponding to each device unit structure; the gate trenches 204 are located in whole or in part in the first conductivity type pillars 202a, a top surface of each of the gate trenches 204 is leveled, a bottom surface of each of the gate trenches 204 is not leveled, and a positional deviation of the bottom surface of each of the gate trenches 204 is determined by the trench etching process.

Step 31 corresponds to step S104 in fig. 5, namely "trench gate photo & etch", which represents the formation of the gate trench 204 of the trench gate using a photolithographic definition plus etching process.

Step 32, forming a bottom dielectric layer 205 in the gate trench 204, including:

as shown in fig. 6E, a first dielectric layer 304 is formed, the first dielectric layer 304 completely fills the gate trench 204 and a top surface of the first dielectric layer 304 is planar.

The first dielectric layer 304 is subjected to a top-to-bottom etching process to form the bottom dielectric layer 205 only in the bottom region of the gate trench 204, and the etching process of the first dielectric layer 304 makes the top surface of each bottom dielectric layer 205 be leveled and makes the thickness deviation of each bottom dielectric layer 205 exactly compensate the position deviation of the bottom surface of each gate trench 204.

As shown in fig. 6F, the etching process of the first dielectric layer 304 first removes the first dielectric layer 304 over the top surface of the gate trench 204.

As shown in fig. 6G, the etching is continued such that the top surface of the first dielectric layer 304 in the gate trench 204 is lowered until the desired location and finally the bottom dielectric layer 205 is formed. In fig. 6G, a line JJ represents the position of the top surface of the gate trench 204, i.e., the top surface of the superjunction structure, a line II represents the position of the top surface of the bottom dielectric layer 205, and a line HH represents the position of the bottom surface of the gate trench 204. The top surface of the gate trench 204 and the line JJ are level, or deviate less than the precision requirement; there is a large deviation between the bottom surface of the gate trench 204 and the line HH, which is generated by the etching process, which may result in a large variation in the depth T101 of the gate trench 204, for example, when the design value of T101 is 4 micrometers, the deviation value of the depth T101 may reach ±0.4 micrometers. That is, there is a deviation of + -0.4 microns between the bottom surface of the gate trench 204 and the line HH.

The top surface of the bottom dielectric layer 205 is level with line II. This keeps the depth T102 of the trench remaining from the bottom surface of the bottom dielectric layer 205 to the top surface of the gate trench 204 constant, or the variation in T102 is within the accuracy requirements.

In the method of the first embodiment of the present invention, the etching process of the first dielectric layer 304 is a patterned etching process, and the etching process of the first dielectric layer 304 simultaneously forms the guard ring dielectric layer 205a; the guard ring dielectric layer 205a covers at least a portion of the termination region and extends into the transition region, an inner side surface of the guard ring dielectric layer 205a is located on the transition region, and the inner side surface of the guard ring dielectric layer 205a divides the transition region into a first transition region located inside an inner side surface of the guard ring dielectric layer 205a and a second transition region located outside the inner side surface of the guard ring dielectric layer 205 a.

The first dielectric layer 304 is an oxide layer. In some preferred embodiment methods, the first dielectric layer 304 is formed by stacking a thermal oxide layer and a CVD deposited oxide layer. When a thermal oxide layer is used in the first dielectric layer 304, the quality of the guard ring dielectric layer 205a can be better, so that the reliability of the device can be improved.

In some preferred embodiments, the etching process of the first dielectric layer 304 uses wet etching.

Step 32 corresponds to step S105 in fig. 5, "Bottom Oxide formation and photo & etch", where Bottom Oxide represents the Bottom dielectric layer 205, information represents the growth of the first dielectric layer 304, bottom Oxide formation and photo & etch represents the growth, lithographic definition and etching of the first dielectric layer 304 and the formation of the Bottom dielectric layer 205.

In the method of the first embodiment of the present invention, in the area of the transition area 2a, the etched area of the first dielectric layer 304 is generally doped with P-type impurities in the subsequent P-type well implantation, and some contact holes 212 are formed in this area to connect with source metal in future, so that when EAS occurs, carriers in the nearby termination area and charge flow area are easily carried away, and the EAS capability of the chip is improved. The first dielectric layer 304 is left as the guard ring dielectric layer 205a on the 2b region and the termination region of the transition region, and there may be polysilicon, a contact hole and a metal field plate formed of metal on the guard ring dielectric layer 205a on the 2b region of the transition region.

In step 33, as shown in fig. 6H, a gate dielectric layer 206 is formed on the side surface of the gate trench 204.

In some embodiments, the gate dielectric layer 206 is a gate oxide layer.

In step 34, as shown in fig. 6H, the gate trenches 204 are filled with a gate conductive material layer 207, and a bottom surface of the gate conductive material layer 207 is defined by a top surface of the bottom dielectric layer 205 so that a bottom surface of each of the gate conductive material layers is leveled.

In the method of the first embodiment of the present invention, the gate conductive material layer 207 is a polysilicon gate.

The substeps of forming the gate conductive material layer 207 include:

a first polysilicon layer is formed that completely fills the gate trench 204 and extends outside the gate trench 204.

And carrying out graphical etching on the first polysilicon layer to form the polysilicon gate.

Referring to fig. 3A, when the polysilicon gate is formed by performing patterned etching on a first polysilicon layer, the patterned etching of the first polysilicon layer also simultaneously forms a first polysilicon field plate 207a or the patterned etching of the first polysilicon layer also simultaneously forms the first polysilicon field plate 207a and a second polysilicon field plate; the first polysilicon field plate 207a is located on the guard ring dielectric layer 205a of the second transition region, the second polysilicon field plate is located on the guard ring dielectric layer 205a of the terminal region, and the second polysilicon field plate is in a floating structure.

As shown in fig. 3B, the gate trench 204 also extends into the first transition region and the gate conductive material layer 207 also extends into the second transition region and contacts the first polysilicon field plate 207a in a length direction along a top view of the gate trench 204.

Steps 33 and 34 correspond to step S106 in fig. 5, i.e. "Gox & poly gate photo & etch", gox representing a gate oxide layer, i.e. the gate dielectric layer 206, and poly gate representing the polysilicon gate. Gox & poly gate photo & etch represents growing the gate dielectric layer 206 and the first polysilicon layer, and performing photolithography and etching to form the polysilicon gate and the first and second polysilicon field plates 207a and 207 b.

Step four, as shown in fig. 6H, performing a second conductivity type well implantation to form a second conductivity type well region 208 on the surface of the superjunction structure, wherein a channel region of each device unit structure is formed by the second conductivity type well region 208, and the gate conductive material layer 207 penetrates through the channel region in a longitudinal direction; the channel region surface covered by the side of the gate conductive material layer 207 located in the first conductive type column 202a is used to form a conductive channel, and the surface of the first conductive type column 202a below the conductive channel, which is covered by the side of the gate conductive material layer 207, is used to form an accumulation region; the bottom surface of each of the layers of polar conductive material is flattened to promote uniformity of the length of the conductive channel and the length of the accumulation region.

Step four corresponds to step S107 in fig. 5, namely "Pwell IMP", in which the second conductivity type is P-type, so that the second conductivity type well region 208 is a P-type well, pwell represents a P-type well, IMP represents ion implantation, and Pwell IMP represents formation of the P-type well by ion implantation. In the method of the first embodiment of the present invention, the second conductivity type well region 208 is implemented by full ion implantation, that is, it is not required to perform photolithography definition, and as shown in fig. 3A, since the guard ring dielectric layer 205a is formed in the 2b region and the terminal region, the second conductivity type well region 208 is formed only in the 1 region and the 2a region, and therefore, the ion implantation impurities of the second conductivity type well region 208 are also overlapped in the second conductivity type ring 208a in the 2a region.

The ion implantation of the second conductivity type well region 208 is typically followed by an annealing process at a temperature of 1000-1050 c for 30-60 minutes, which is primarily set by the desired depth of the second conductivity type well region 208.

Step five, as shown in fig. 6I, a first conductivity type heavily doped ion implantation is performed to form a source region 209 on the surface of the channel region.

Step five corresponds to step S108 in fig. 5, namely, "Nplus photo & IMP", in which the source region 209 is an n+ doped region since the first conductivity type is N type, nplus represents an n+ doped region, nplus photo & IMP represents formation of the source region 209 by photolithography and ion implantation.

Typically at the outermost end stop ring of the termination region, which is also formed simultaneously with the source region 209 by the first conductivity type heavily doped ion implantation of step five.

In the method of the first embodiment of the present invention, after the fifth step, the method further includes:

an interlayer film 211 and a contact hole 212 are formed.

The process of forming the contact hole 212 corresponds to step S109 in fig. 5, "contact photo & etch", where contact is the abbreviation of the contact hole 212, and contact photo & etch means etching the interlayer film 211 by photolithography definition to form the contact hole 212.

Forming a front metal layer 213, and patterning the front metal layer 213 to form a source electrode and a gate electrode, wherein the gate electrode comprises a gate pad, a gate bus line and a gate finger;

the channel region and the source region 209 are connected to the source electrode through the contact hole 212 corresponding to the top;

the second conductivity type ring is connected to the source through a contact hole 212 on top and in the first transition region.

The first polysilicon field plate 207a is connected to the gate through a top corresponding contact hole 212.

The step of patterning the front Metal layer 213 to form the source and the gate corresponds to step S110 in fig. 5, namely, "Metal photo & etch", where Metal represents the front Metal layer 213,Metal photo&etch represents the front Metal layer 213 being patterned by a photolithography and etching process.

In some embodiments, the trench gate superjunction device is a MOS transistor, and the N-type device is an NMOS, and further comprising:

and thinning the back surface of the semiconductor substrate 201, and forming a drain region by self first conductivity type heavy doping of the semiconductor substrate 201 or adding back surface first conductivity type ion implantation.

A back metal layer 214 is then formed on the back of the drain region and the drain is composed of the back metal layer 214.

As shown in fig. 5, the entire process flow of the method according to the first embodiment of the present invention can be implemented by only 9 times of photolithography, and in some processes, the zeroth layer of photolithography, i.e. step S101, can be omitted, and only 8 times of photolithography can be implemented.

The method according to the first embodiment of the invention achieves the following advantages:

except for the zero layer, the trench gate superjunction MOSFET with bottom oxide, i.e. the bottom dielectric layer 205, is completed only by 8 times of photoetching, and the cost is reasonable.

The film of the bottom oxide is utilized, and meanwhile, the protective film of the terminal area, namely the protective ring dielectric layer 205a, is simple in process, and can be used as a sacrificial oxide film of a trench gate, so that compatibility with a manufacturing process without the bottom oxide is ensured.

By adopting the bottom oxide, cgd of the device can be obviously reduced, and the switching loss of the device can be reduced.

Since the bottom oxide is obtained by wet etching after the gate trench 204 is formed and the gate trench 204 is filled, etching or CMP is performed. Thus, when the depth of the pole trench 204 is changed, the main change will be the thickness of the bottom ox, and the length of the conductive channel and the accumulation region, i.e. the longitudinal length of the polysilicon gate 207, as the MOSFET will be changed relatively little, thus improving the uniformity of Cgd of the device.

As shown in fig. 7, a flowchart of a method for manufacturing a trench gate superjunction device according to a second embodiment of the present invention is shown, and the method for manufacturing a trench gate superjunction device according to the second embodiment of the present invention differs from the method for manufacturing a trench gate superjunction device according to the first embodiment of the present invention in that:

in the method for manufacturing a trench gate superjunction device according to the second embodiment of the present invention, in step S106a, the photolithography process is no longer required, that is, in step S34, the polysilicon gate is directly formed by performing full back etching on the first polysilicon layer, so that the first polysilicon field plate 207a shown in fig. 3A is not formed, but the structure without the first polysilicon field plate 207a shown in fig. 4A is formed.

As can be seen from comparing fig. 7 and fig. 5, the method for manufacturing a trench gate superjunction device according to the second embodiment of the present invention can further reduce one photolithography process.

The following describes the method for manufacturing the superjunction device according to the first embodiment of the present invention in more detail with reference to specific parameters:

the method for manufacturing the superjunction device according to the first embodiment of the present invention forms the superjunction device according to the first embodiment of the present invention shown in fig. 3A, and is described below by taking the superjunction NMOSFET of 600V as an example.

In step S101 before the first step, the semiconductor substrate 201 is an N-type substrate, and the material is silicon (Si); the resistivity of the N-type substrate is less than 0.01 ohm-cm, and typical values are 0.003-0.005 ohm-cm, and the thickness is about 725 micrometers; the epitaxial layer 202 of the semiconductor substrate 201 is an N-type epitaxial layer and doped with phosphorus, the resistivity of the epitaxial layer 202 is 1.2 ohm cm, and the corresponding impurity concentration is 4E15cm ^-3 The thickness was 50 microns.

The step S101 includes: depositionIs formed in the scribe line by lithography etching>The photoresist is removed as an alignment or measurement mark. />

In step one, use is made ofox is used as mask (screen) ox, P-type ring (P ring) photoetching is carried out, boron implantation is carried out under the transition region, gate pad and gate finger, and the implantation conditions are B60 Kev-80Kev,5E12cm ^-2 -5E13cm ^-2 The method comprises the steps of carrying out a first treatment on the surface of the Removing the photoresist, and performing high-temperature annealing, wherein the annealing process parameters can be as follows: the temperature is 1100 ℃, the time is 30-300min, and the temperature is set according to the requirements of terminal design and reliability. This B implant and anneal set may also have an effect on the single pulse avalanche Energy (EAS) capability of the chip. The ox of the si surface is then removed entirely.

In step two, an oxide film is deposited on the epitaxial layer 202 as a hard mask layer 301. The forming process of the hard mask layer 301 includes: formation of thermal oxidationFilm thickness ofThen forming a silicon nitride film, which can be a film deposited by CVD film, i.e. CVD process, with a thickness of +.>Then forming oxide film, which can be formed by CVD deposition, with a thickness of +.>Or thicker, for example, when needed as a barrier to deep trench etching.

After etching the hard mask layer 301 in the selected area by photolithography and etching, silicon etching is performed by using the hard mask layer 301 as a mask or directly using photoresist as a mask, so as to form a trench 302, wherein a certain distance is formed between the bottom surface of the trench 302 and the bottom surface of the epitaxial layer 202. The N-type epitaxial portion between adjacent trenches 302 constitutes an N-type pillar 202a. The top width of the trench 302 may be set to 4.5 μm, the top width of the N-type pillar 202a may be set to 4.5 μm, the depth may be set to 40 μm to 42 μm, the trench 302 may be vertical or may have an inclination angle, and the distance between the bottom surface of the trench 302 and the bottom surface of the epitaxial layer 202 may be 8 μm to 10 μm.

Thereafter, the P-type epitaxial layer 303 is filled in the trench 302, and the trench 302 is completely filled. The hard mask layer 301 is also deposited with a P-type epitaxy. The design and distribution of the impurity concentration of the P-type epitaxy may be set according to the inclination angle of the trench. To select good charge balance with the impurities in the N-type epitaxial layer 202 to achieve the desired reverse breakdown voltage, an example is where the trench 302 is vertical, then the concentration of the P-type epitaxial layer 303 may also be selected to be 4E15cm ^-3 . And then, the surface silicon is completely removed by chemical mechanical polishing, and then, the surface hard mask layer 301 is completely removed, and the hard mask layer 301 is generally removed by wet etching. P-type pillars 203 and N-type pillars 202a are formed, the P-type pillars 203 and N-type pillars 202a being adjacent to each other, forming an alternating arrangementThe P-N type column is a super junction structure.

In step 31, a second dielectric film is deposited followed by photolithography and etching to form gate trenches 204 in the N-type pillars 202 a. The second dielectric film is typically a silicon oxide film with a thickness of 3000-10000 a, and the gate trench 204 is typically disposed in the N-type pillar 202a, but may be partially disposed in the P-type pillar 203 in some embodiments. The gate trench 204 has a width less than the N-type pillars 202a, e.g., leaving at least 0.5 μm on each side for forming n+ source regions, and may be designed to have a width of 1 micron to 1.2 microns, a depth of 2 microns to 4 microns, or even thicker, e.g., 6 μm.

In step 32, a first dielectric layer 304, which may be a partial thermal oxide film, is deposited, for example, to a thickness of 2000 angstroms to 3000 angstroms on the sidewalls of the gate trench 204, followed by a CVD film, such as a SACVD film or an HDPCVD film, for example, to a thickness of 8000 angstroms, to completely fill the trench. A first dielectric layer 304 is deposited on the surface of the semiconductor substrate 201.

The first dielectric layer 304 in the second transition region and the terminal region is then kept by photolithography, the first dielectric layer 304 in the charge flow region and the first transition region is etched away, and etching is continued until the first dielectric layer 304 in the gate trench 204 is partially etched away, and only the first dielectric layer 304 is left at the bottom of the gate trench 204. The thickness T103 of the first dielectric layer 304 left at the bottom of the gate trench 204 is determined by device design requirements, for example, one configuration is to leave a trench depth T102 of 0.8 microns to 1 micron, the bottom is completely left, and if the trench depth T101 is 4 microns, the thickness T103 of the first dielectric layer 304 is 3 microns to 3.2 microns. The portion of the first dielectric layer 304 that is not etched out of the gate trench 204 is 10000 a to 11000 a thick, which is easy to obtain the desired thickness for the termination, or guard ring dielectric layer 205a under the gate pad.

In step 33, the gate dielectric layer 206 is deposited by depositing the gate dielectric layer 206, typically a gate oxide layer, having a thickness of 1000 angstroms to 1200 angstroms.

In step 34, a first polysilicon layer corresponding to the gate conductive material layer 207 is formed to completely fill the gate trench 204, and the thickness of the first polysilicon layer is generally 8000-12000 angstroms, and typically, the first polysilicon layer is highly doped with N-type, and the doped impurities are phosphorus; then, completely etching the first polysilicon layer of the charge flow region and the first transition region by photolithography and etching, and reserving the first polysilicon layer on the second transition region as the first polysilicon field plate 207a; a floating second polysilicon field plate can also be formed in the termination region.

In the fourth step, the P-type well region 208 is formed by ion implantation, and the implantation energy of the P-type well region 208 is typically 60Kev; b is injected with impurities; the implantation impurity dose is set according to the requirement of the threshold voltage of the device, and is generally 2E12cm ^-2 ～2E13cm ^-2 。

In the fifth step, the N-type source region 209 is formed by photolithography, the implantation energy of ion implantation of the N-type source region 209 is set to 40 keV-80 keV, arsenic impurity is implanted, and the implantation dose is 3E15cm ^-2 -6E15cm ^-2 . The ion implantation may be followed by an activation process, for example, a thermal process at 950 c for 30min, or a rapid thermal anneal (RTP) at 1000 c to 1050 c.

In the subsequent process after the fifth step, an interlayer film 211 is deposited to form an isolation film between the polysilicon and the front metal layer 213, and the interlayer film 211 is generally deposited with an undoped oxide film with a thickness of 1000-2000 angstroms; then depositing an oxide film of BPSG with the thickness of 8000 angstrom-10000, and then annealing at 950 ℃ for 30min to realize planarization.

Then, forming a contact hole 212 by photoetching and etching, leading out an N+ source region 209 by the contact hole 212, injecting high-concentration P-type impurities at the bottom of the contact hole 212 to be connected with a P-type well 208, wherein the injection energy of P-type impurities in the contact hole 212 is 60keV-80keV, the injection impurities are B or BF2 or the combination of the B and BF2, and the injection dosage is 3E13cm ^-2 -2E15cm ^-2 Finally, a contact region 210 is formed.

Thereafter, the front metal layer 213 is formed by metal deposition. Metal photolithography and etching are then performed to form the source and gate electrodes comprised of the front side metal layer 213. The front metal layer 213 leading out of the source will be connected to the corresponding source region through the contact hole 212. The grid electrode is connected with the polysilicon gate through a grid pad (pad) and a grid bus (bus) formed by the front metal layer 213, and a corresponding contact hole 212 at the bottom of a grid finger (finger); a full or multiple turn metal ring can also be formed on the protected area near the scribe line for electrical and physical protection. The metal of the front metal layer 213 may be AlSiCu or ALCu, and the thickness is 4-5 microns, the thicker the thickness is, the better the product formation is, and after metal etching, a metal alloy (metal alloy) with a temperature of 400-450 ℃ may be used to repair some dangling bonds of the SiO2-Si interface, so as to improve the stability of the threshold voltage.

Thereafter, the drain electrode composed of the back metal layer 214 is formed by polishing and thinning the back surface of the chip, that is, the back surface of the semiconductor substrate 201, and depositing the back metal layer 214. The thickness of the semiconductor substrate 201 is typically reduced from 725 microns to 60 microns-200 microns; the metal of the back metal layer 214 may be TiNiAg having a total thickness of about 10000 angstroms.

The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims

1. The utility model provides a trench gate superjunction device which characterized in that: the middle area of the super junction device is a current flowing area, the terminal area surrounds the periphery of the current flowing area, and the transition area is positioned between the current flowing area and the terminal area;

forming a super junction structure formed by alternately arranging first conductive type columns and second conductive type columns on a semiconductor substrate;

the super junction structure is formed in the current flow area, and a device unit structure of a plurality of super junction devices in parallel structures is formed at the top of the super junction structure of the current flow area;

The trench gate of each device unit structure is formed by laminating a bottom dielectric layer, a gate dielectric layer and a gate conductive material layer which are formed in a gate trench;

the grid electrode groove is wholly or partially positioned in the first conductive type column, the bottom dielectric layer is formed at the bottom of the grid electrode groove, the grid dielectric layer is formed on the side face of the grid electrode groove, and the grid electrode conductive material layer completely fills the grid electrode groove with the bottom dielectric layer and the grid dielectric layer;

the channel region of each device unit structure is composed of a second conductive type well region formed on the surface of the super junction structure, the grid conductive material layer penetrates through the channel region in the longitudinal direction, the surface of the channel region covered by the side surface of the grid conductive material layer positioned in the first conductive type column is used for forming a conductive channel, and the surface of the first conductive type column covered by the side surface of the grid conductive material layer below the conductive channel is used for forming an accumulation region;

forming a source region composed of a first conductive type heavily doped region on the surface of the channel region;

forming a second conductivity type ring in the transition region;

Each gate trench is formed by the same trench etching process, the top surface of each gate trench is leveled, the bottom surface of each gate trench is not leveled and the positional deviation of the bottom surface of each gate trench is determined by the trench etching process;

the bottom dielectric layers are formed by etching the first dielectric layers which are completely filled in the gate trenches from top to bottom, the etching process of the first dielectric layers enables the top surfaces of the bottom dielectric layers to be leveled, and the thickness deviation of the bottom dielectric layers just compensates the position deviation of the bottom surfaces of the gate trenches;

2. The trench-gate superjunction device of claim 1, wherein: the etching process of the first dielectric layer is a patterned etching process, and the etching process of the first dielectric layer simultaneously forms a protective ring dielectric layer; the guard ring dielectric layer covers at least part of the terminal region and extends into the transition region, the inner side surface of the guard ring dielectric layer is located on the transition region, the inner side surface of the guard ring dielectric layer divides the transition region into a first transition region and a second transition region, the first transition region is located on the inner side of the inner side surface of the guard ring dielectric layer, and the second transition region is located on the outer side of the inner side surface of the guard ring dielectric layer.

3. The trench-gate superjunction device of claim 2, wherein: the guard ring dielectric layer is also formed in the gate finger forming region and the gate pad forming region.

4. The trench-gate superjunction device of claim 2, wherein: the first dielectric layer is an oxide layer.

5. The trench-gate superjunction device of claim 4, wherein: the first dielectric layer is formed by laminating a thermal oxide layer and a CVD deposited oxide layer.

6. The trench-gate superjunction device of claim 2, wherein: the gate conductive material layer is a polysilicon gate.

7. The trench-gate superjunction device of claim 6, wherein: the polysilicon gate is formed by comprehensively back etching the first polysilicon layer or performing patterned etching;

8. The trench-gate superjunction device of claim 7, wherein: the superjunction device further comprises a source electrode and a grid electrode which are formed by patterning the front metal layer, wherein the grid electrode comprises a grid electrode pad, a grid electrode bus and a grid electrode finger;

the channel region and the source region are connected to the source electrode through corresponding contact holes at the top;

9. The trench-gate superjunction device of claim 7, wherein: the gate trench also extends into the first transition region and the gate conductive material layer also extends into the second transition region and into contact with the first polysilicon field plate along a length of a top-down face of the gate trench.

10. A manufacturing method of a trench gate superjunction device is characterized by comprising the following steps: the super junction device is divided into a current flowing area, a transition area and a terminal area, wherein the middle area is the current flowing area, the terminal area surrounds the periphery of the current flowing area, and the transition area is positioned between the current flowing area and the terminal area; the method comprises the following steps:

Step one, performing ion implantation of a second conduction type ring to form the second conduction type ring in the transition region;

step two, forming a super junction structure formed by alternately arranging first conductive type columns and second conductive type columns on a semiconductor substrate; the current flow area is provided with the super junction structure;

step 31, forming a grid groove corresponding to each device unit structure by a patterned groove etching process; the gate trenches are all or partially positioned in the first conductive type column, the top surfaces of the gate trenches are flat, the bottom surfaces of the gate trenches are not flat, and the position deviation of the bottom surfaces of the gate trenches is determined by the trench etching process;

step 32, forming a bottom dielectric layer in the gate trench, including:

forming a first dielectric layer, wherein the first dielectric layer completely fills the gate trench and the top surface of the first dielectric layer is flat;

Performing an etching process on the first dielectric layer from top to bottom to form the bottom dielectric layer only in the bottom area of the gate trench, wherein the etching process of the first dielectric layer enables the top surface of each bottom dielectric layer to be flat, and enables the thickness deviation of each bottom dielectric layer to exactly compensate the position deviation of the bottom surface of each gate trench;

step 33, forming a gate dielectric layer on the side surface of the gate trench;

step 34, filling a gate conductive material layer in the gate trench, wherein the bottom surface of the gate conductive material layer is determined by the top surface of the bottom dielectric layer, so that the bottom surfaces of the electrode conductive material layers are leveled;

step four, injecting a second conductive type well into the surface of the super junction structure to form a second conductive type well region, wherein a channel region of each device unit structure is formed by the second conductive type well region, and the grid conductive material layer longitudinally penetrates through the channel region; the channel region surface covered by the side of the gate conductive material layer located in the first conductive type column is used to form a conductive channel, and the surface of the first conductive type column below the conductive channel covered by the side of the gate conductive material layer is used to form an accumulation region; the bottom surface of each polar conductive material layer is leveled so that the consistency of the length of the conductive channel and the length of the accumulation region is improved;

11. The method of manufacturing a trench gate superjunction device of claim 10, wherein: in step 32, the etching process of the first dielectric layer is a patterned etching process, and the etching process of the first dielectric layer forms a protection ring dielectric layer at the same time; the guard ring dielectric layer covers at least part of the terminal region and extends into the transition region, the inner side surface of the guard ring dielectric layer is located on the transition region, the inner side surface of the guard ring dielectric layer divides the transition region into a first transition region and a second transition region, the first transition region is located on the inner side of the inner side surface of the guard ring dielectric layer, and the second transition region is located on the outer side of the inner side surface of the guard ring dielectric layer.

12. The method of manufacturing a trench gate superjunction device of claim 11, wherein: the guard ring dielectric layer is also formed in the gate finger forming region and the gate pad forming region.

13. The method of manufacturing a trench gate superjunction device of claim 11, wherein: the first dielectric layer is an oxide layer.

14. The method of manufacturing a trench gate superjunction device of claim 13, wherein: the first dielectric layer is formed by laminating a thermal oxide layer and a CVD deposited oxide layer.

15. The method of manufacturing a trench gate superjunction device of claim 11, wherein: in step 34, the gate conductive material layer is a polysilicon gate.

16. The method of fabricating a trench gate superjunction device of claim 15, wherein: in step 34, the sub-step of forming the gate conductive material layer includes:

forming a first polysilicon layer which completely fills and extends the gate trench out of the gate trench;

carrying out overall back etching on the first polysilicon layer to form the polysilicon gate; or performing graphical etching on the first polysilicon layer to form the polysilicon gate;

17. The method of fabricating a trench gate superjunction device of claim 16, wherein: after the fifth step, the method further comprises: forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a source electrode and a grid electrode, wherein the grid electrode comprises a grid electrode pad, a grid electrode bus and a grid electrode finger;

18. The method of fabricating a trench gate superjunction device of claim 16, wherein: the gate trench also extends into the first transition region and the gate conductive material layer also extends into the second transition region and into contact with the first polysilicon field plate along a length of a top-down face of the gate trench.

19. The method of manufacturing a trench gate superjunction device of claim 13, wherein: the etching process of the first dielectric layer adopts wet etching.