CN110034183B - Transverse Schottky gate bipolar transistor and manufacturing method thereof - Google Patents
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/6625—Lateral transistors
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- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66257—Schottky transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
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- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
Abstract
The invention provides a transverse Schottky gate bipolar transistor (LSGBT) and a manufacturing method thereof. The LSGBT device combines a source-drain region of a LIGBT structure with a Schottky gate of a MESFET structure, uses the Schottky gate to replace an insulated gate, and has a gate structure similar to a trench gate structure of a conventional MESFET and other parts similar to the conventional LIGBT structure. Compared with the LIGBT, the LSGBT device has no parasitic NPN transistor structure, so that the latch-up effect is eliminated, and the stability of the device is enhanced; the gate control mode is changed from an insulated gate to a Schottky gate, so that the complexity of a gate process can be reduced, the problem of oxidation of a wide-band-gap semiconductor material can be solved, and the advantage of a voltage control device can be kept, namely high input impedance is achieved. The LSGBT device is particularly suitable for the field of low voltage and large current.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a transverse grid-control bipolar transistor.
Background
The power semiconductor device is a high-power electronic device mainly used for an electric energy conversion and control circuit of power equipment. With the rapid development of power electronic technology, power semiconductor devices have been widely used in modern industrial control and defense equipment.
Lateral Insulated Gate Bipolar Transistor (LIGBT) is a power device that is well suited for high voltage power supply ics (hvics) because it combines high input impedance and bipolar current conduction, while the Lateral device is easy to integrate and its process is compatible with that of conventional complementary mos (cmos) chips. In recent years, the optimization of the characteristics of LIGBT devices has mainly been the study of LIGBT devices with low static and dynamic power consumption. At present, the process difficulty of the wide band gap semiconductor material LIGBT device is high, and the latch-up effect may cause the device to be unstable.
Disclosure of Invention
The invention provides a transverse Schottky gate bipolar transistor and a manufacturing method thereof, aiming at reducing the process difficulty, eliminating the latch-up effect and improving the device performance.
The technical scheme of the invention is as follows:
the lateral Schottky gate bipolar transistor comprises:
a P-type substrate;
an N-type epitaxial layer formed on the upper surface of the P-type substrate;
an N-type buffer area is formed in the right end area of the upper portion of the N-type epitaxial layer, and a P-type drain area is formed in the upper portion of the N-type buffer area;
an N-type source region formed at the left end region of the upper part of the N-type epitaxial layer;
the source electrode is positioned on the upper surface of the N-type source region;
the drain electrode is positioned on the upper surface of the P-type drain region;
forming a gate groove in the central area of the upper part of the N-type epitaxial layer, wherein a gate is positioned at the bottom of the gate groove, the gate length is 0.5-1 micron, and the distances between the gate and a source electrode and between the gate and a drain electrode are 0.2-0.5 micron and 0.6-0.9 micron respectively; the depth of the gate groove is 1-3 microns, and the gate groove is determined according to the source and drain saturation current (the deeper the gate groove, the narrower the N-type channel, and the smaller the source and drain saturation current).
On the basis of the scheme, the invention further optimizes the following steps:
the doping concentration of the N type epitaxial layer is 2 multiplied by 1017cm-3。
The doping concentration of the N-type epitaxial layer is 1-2 orders of magnitude higher than that of the P-type substrate.
The N-type buffer region and the P-type drain region are formed on the upper portion of the N-type epitaxial layer through ion implantation and double diffusion technology, and the N-type source region is formed through ion implantation technology.
The process for forming the gate groove is wet etching.
The source and drain metal is in ohmic contact with the semiconductor material, and the gate metal is in schottky contact with the semiconductor material.
The P-type substrate and the N-type epitaxial layer are made of wide band gap semiconductor materials, and specifically, silicon carbide or gallium nitride is selected.
A method for manufacturing the transverse Schottky gate bipolar transistor comprises the following steps:
(1) preparing a P-type wide band gap semiconductor material as a P-type substrate;
(2) epitaxially growing an N-type epitaxial layer on the upper surface of the P-type substrate;
(3) forming an N-type buffer region in the right side area of the upper part of the N-type epitaxial layer through an ion implantation process, and performing a trap pushing process at a higher temperature, wherein the junction depth finally depends on the temperature and time of the trap;
(4) forming a heavily doped P-type drain region by ion implantation and double diffusion technology, and performing rapid annealing treatment after the implantation is finished;
(5) forming a heavily doped N-type source region in the left region of the upper part of the N-type epitaxial layer through an ion implantation process, and performing rapid annealing treatment after implantation is completed;
(6) forming a source electrode and a drain electrode which are in ohmic contact on the upper surfaces of the N-type source region and the P-type drain region respectively through a metal electron beam evaporation process;
(7) forming a gate groove with a certain depth and width on the upper part of the N-type epitaxial layer by a wet etching process;
(8) forming a gate electrode in Schottky contact in the bottom region of the gate groove by a metal electron beam evaporation process; the width of the grid electrode is smaller than that of the grid groove, namely the grid electrode cannot be contacted with the side edge of the grid groove.
The technical scheme of the invention has the following beneficial effects:
the transverse Schottky Gate Bipolar Transistor (LSGBT) is a novel device structure combining a source drain region of a LIGBT structure and a Schottky Gate of a MESFET structure, uses the Schottky Gate to replace an insulated Gate, and has a Gate structure similar to a trench Gate structure of a conventional MESFET, while the rest parts are similar to the conventional LIGBT structure. Compared with the LIGBT, the LSGBT device has no parasitic NPN transistor structure, so that the latch-up effect is eliminated, and the stability of the device is enhanced.
The LSGBT device also reserves the advantages of a bipolar device, has low conduction voltage drop and high carrier density, and simultaneously, the gate control mode is changed from an insulated gate to a Schottky gate, so that the complexity of a gate process can be reduced, the problem of oxidation of a wide-band-gap semiconductor material is solved, and the advantages of a voltage control device, namely high input impedance, can be reserved.
The LSGBT device is a power device that is well suited for low voltage and high current applications because it combines high input impedance with bipolar current conduction, while the lateral device is easy to integrate and its process is compatible with that of a conventional complementary MOS chip.
Drawings
Fig. 1 is a schematic structural view of the present invention.
Wherein, 101-source electrode; 102-a drain electrode; 103-a gate; 104-N type source region; 105-P type drain region; 106-N type buffer; a 801-P type substrate; an 802-N type epitaxial layer.
Detailed Description
The invention will be described below by taking an N-channel LSGBT as an example with reference to the accompanying drawings.
As shown in fig. 1, this example includes:
a P-type substrate 801 of wide bandgap semiconductor material;
an N-type epitaxial layer of wide band gap semiconductor material formed on the upper surface of a P-type substrate 801 and marked as an N-type epitaxial layer 802;
an N-type buffer region 106 formed in the right end region of the upper portion of the N-type epitaxial layer 802, and a P-type drain region 105 formed inside the N-type buffer region 106;
an N-type source region 104 formed in the left end region of the upper part of the N-type epitaxial layer 802;
a source 101 located on the upper surface of the N-type source region 104;
a drain electrode 102 positioned on the upper surface of the P-type drain region 105;
a gate trench formed on the upper part of the N-type epitaxial layer 802 by using a wet etching process;
and a gate 103 located in a region at the bottom of the gate trench.
The N-channel LSGBT device can be prepared by the following steps:
(1) preparing a P-type wide band gap semiconductor material as a P-type substrate 801;
(2) epitaxially growing an N-type epitaxial layer 802 on the upper surface of the P-type substrate 801, wherein the doping concentration of the N-type epitaxial layer 802 is 2 orders of magnitude higher than that of the P-type substrate 801;
(3) forming an N-type buffer region 106 in the right region of the upper part of the N-type epitaxial layer 802 through an ion implantation process, and performing a well pushing process at a higher temperature, wherein the junction depth depends on the temperature and time of the well pushing process;
(4) forming a heavily doped P-type drain region 105 by ion implantation and double diffusion technology, and performing rapid annealing treatment after the implantation is finished;
(5) forming a heavily doped N-type source region 104 in the left region of the upper part of the N-type epitaxial layer 802 through an ion implantation process, and performing rapid annealing treatment after implantation;
(6) forming a source electrode 101 and a drain electrode 102 which are in ohmic contact on the upper surfaces of the N-type source region 104 and the P-type drain region 105 through a metal electron beam evaporation process;
(7) forming a gate groove with a certain depth and width on the upper part of the N-type epitaxial layer 802 by a wet etching process, wherein the depth of the gate groove is determined according to the designed source-drain saturation current, and the deeper the gate groove is, the narrower the N-type channel is, and the smaller the source-drain saturation current is;
(8) and forming a gate 103 with Schottky contact in the area of the bottom of the gate groove by a metal electron beam evaporation process, wherein the width of the gate 103 is smaller than that of the gate groove, namely the gate cannot be contacted with the side edge of the gate groove.
ISE TCAD simulation shows that the latch-up failure condition of the device can be eliminated, the breakdown voltage can be improved to more than 100V compared with the traditional silicon-based MESFET device, and meanwhile, the device has the forward characteristic similar to the traditional LIGBT.
The LSGBT in the present invention may also be a P-channel, and its structure is equivalent to that of an N-channel LSGBT, and it is also considered to be within the protection scope of the claims of the present application, and is not described herein again.
The material used in this embodiment is a wide bandgap semiconductor material, but obviously, other common semiconductor materials are also applicable, such as silicon, germanium, gallium arsenide, etc. The LSGBT made of these materials should be regarded as an equivalent solution of the LSGBT of this embodiment, and therefore, the LSGBT also belongs to the protection scope of the claims of this application, and the description thereof is omitted.
Claims (7)
1. A lateral schottky gate bipolar transistor comprising:
a P-type substrate (801);
an N-type epitaxial layer (802) formed on the upper surface of a P-type substrate (801);
an N-type buffer region (106) formed in the right end region of the upper portion of the N-type epitaxial layer (802) and a P-type drain region (105) formed in the upper portion of the N-type buffer region (106);
an N-type source region (104) formed in the left end region of the upper part of the N-type epitaxial layer (802);
a source (101) located on an upper surface of the N-type source region (104);
the drain electrode (102) is positioned on the upper surface of the P-type drain region (105);
forming a gate groove in the central area of the upper part of the N-type epitaxial layer (802), wherein the gate (103) is positioned at the bottom of the gate groove, the gate length is 0.5-1 micron, and the distances between the gate (103) and the source (101) and the drain (102) are 0.2-0.5 micron and 0.6-0.9 micron respectively; the depth of the gate groove is 1-3 microns and is determined according to source-drain saturation current; the source and drain metal is in ohmic contact with the semiconductor material, and the gate metal is in schottky contact with the semiconductor material.
2. The lateral schottky gate bipolar transistor of claim 1 wherein: the doping concentration of the N-type epitaxial layer (802) is 2 x 1017cm-3。
3. The lateral schottky gate bipolar transistor of claim 1 wherein: the doping concentration of the N-type epitaxial layer (802) is 1-2 orders of magnitude higher than that of the P-type substrate (801).
4. The lateral schottky gate bipolar transistor of claim 1 wherein: the N-type buffer region (106) and the P-type drain region (105) are formed by ion implantation and double diffusion techniques on top of the N-type epitaxial layer (802), and the N-type source region (104) is formed by ion implantation techniques.
5. The lateral schottky gate bipolar transistor of claim 1 wherein: the process used for forming the gate groove is wet etching.
6. The lateral schottky gate bipolar transistor of claim 1 wherein: the P-type substrate (801) and the N-type epitaxial layer (802) are wide bandgap semiconductor materials.
7. A method of fabricating the lateral schottky gate bipolar transistor of claim 1, comprising the steps of:
1) preparing a P-type wide band gap semiconductor material as a P-type substrate (801);
2) epitaxially growing an N-type epitaxial layer (802) on the upper surface of the P-type substrate (801);
3) forming an N-type buffer region (106) in the upper right region of the N-type epitaxial layer (802) through an ion implantation process, wherein the junction depth finally depends on the temperature and time of a well;
4) forming a heavily doped P-type drain region (105) by ion implantation and double diffusion technology, and performing rapid annealing treatment after the implantation is finished;
5) forming a heavily doped N-type source region (104) in the left region of the upper part of the N-type epitaxial layer (802) through an ion implantation process, and performing rapid annealing treatment after implantation;
6) forming a source electrode (101) and a drain electrode (102) which are in ohmic contact on the upper surfaces of the N-type source region (104) and the P-type drain region (105) through a metal electron beam evaporation process;
7) forming a gate groove with required depth and width on the upper part of the N-type epitaxial layer (802) by a wet etching process;
8) and forming a gate electrode (103) of a Schottky contact in the bottom region of the gate groove through a metal electron beam evaporation process.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101419981A (en) * | 2008-12-04 | 2009-04-29 | 电子科技大学 | Trench gate SOI LIGBT device |
| CN109417091A (en) * | 2016-05-09 | 2019-03-01 | 卡塔尔大学 | Heterojunction schottky grid bipolar transistor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101419981A (en) * | 2008-12-04 | 2009-04-29 | 电子科技大学 | Trench gate SOI LIGBT device |
| CN109417091A (en) * | 2016-05-09 | 2019-03-01 | 卡塔尔大学 | Heterojunction schottky grid bipolar transistor |
Non-Patent Citations (2)
| Title |
|---|
| 4H-SiC MESFET的特性研究;徐昌发,etal;《材料研究》;20020822;第75页左栏第2-3段及图1 * |
| New SOI structure for LIGBT with improved thermal and latch-up characteristics;Yung C.Liang,etal;《IEEE 1999 International Conference on Power Electronics and Drive Systems》;19990630;第258页第2段及图1 * |
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