JP4628485B2 - Method for manufacturing thin film transistor - Google Patents

Description

The present invention relates to a structure of a TFT (thin film transistor) or a semiconductor integrated circuit having a TFT, and a manufacturing method thereof. In particular, the present invention relates to a wiring of a TFT or a semiconductor integrated circuit having a TFT and a method for forming the wiring.

2. Description of the Related Art Conventionally, a technique of using a TFT (Thin Film Transistor) in a device integrated on a glass substrate such as an active matrix type liquid crystal display device or an image sensor is widely known. What is important in these circuits is to reliably form a contact between the semiconductor region (source and drain) of the TFT and the wiring, and to reduce the resistance of the circuit. These issues become more important as the degree of circuit integration progresses, and technical difficulties appear.

The former problem is related to the very thin semiconductor coating used. In general, a semiconductor film is required to be thin in order to obtain high characteristics, but it is not usual to form a contact on a thin semiconductor film of about several hundreds of millimeters. With a fairly high probability, holes may be formed in the semiconductor film by being over-etched in the contact hole formation stage. This is because the etching rate (especially in the case of dry etching) of silicon oxide, silicon nitride generally used as an interlayer insulator and silicon used as a semiconductor film is not so large.

Furthermore, regarding the latter problem, most of the resistance is the resistance of the semiconductor film, and it is an effective measure to reduce the semiconductor film part in the circuit.
It cannot be solved by circuit arrangement alone.
As a method for solving the latter of such problems, a method has been proposed in which most of the portions corresponding to the source and drain of the TFT are silicided. An example will be described with reference to FIG.

A semiconductor film (active layer) 22 is formed on the substrate 21 and covers the gate insulating layer 2.
3. Furthermore, a gate electrode 24 and a gate wiring 25 are provided. The gate electrode 24 and the gate wiring 25 are in the same layer. That is, they are formed simultaneously. The active layer 22 has a source 2
6. Impurity regions such as the drain 27 are formed. (Fig. 2 (A))

Thereafter, sidewall insulators 28 are formed on the side surfaces of the gate electrode 24 and the gate wiring 25 using a known anisotropic etching technique. This is usually obtained by a method of performing anisotropic etching after covering the entire surface with an insulator. At that time, the gate insulating layer 23 is also etched, and the surface of the active layer is exposed. Further, a gate insulating film 23 a is obtained under the gate electrode 24, and a gate insulating film 23 b is obtained under the gate wiring 25. (Fig. 2 (B))

Next, a metal layer 29 is formed on the entire surface. (Fig. 2 (C))
Then, the silicide layers 30 and 31 are obtained by reacting the metal layer 29 and the active layer 22 at the interface by means of thermal annealing, rapid thermal annealing, optical annealing or the like. The silicide layer may be reacted until reaching the bottom of the active layer as shown in the figure, or may be reacted to the extent that it stops in the middle. In any case, since the reaction proceeds from the contact portion between the metal layer 29 and the active layer 22, the source and drain below the side wall 28 remain as semiconductors. (Fig. 2 (D)
)

Next, the unreacted metal layer is removed entirely. (Figure 2 (E))
Finally, upper wirings 34 and 35 are formed on the interlayer insulator 33 by using a known multilayer wiring technique. The upper wiring forms silicide layers 30 and 31 and contacts 32a and 32b, respectively, and gate wiring 25 and contacts 32c.
In the example of FIG. 2, the case where the side wall by anisotropic etching is used is shown.
169974, 7-169975, 7-218932, etc. may employ an anodizing technique for gate electrodes.

In such a method, since the resistivity of the silicide is smaller than that of the semiconductor material, the resistance of the circuit passing through the TFT can be reduced. However, the problems in forming contact holes cannot be almost solved. This is because the etching rate by the dry etching method of silicide and silicon oxide or silicon nitride is not sufficiently high. In particular, it is known that a method using silicon nitride as an interlayer insulating film of a TFT is effective (for example, JP-A-7-3267).
68) In this case, however, if the etching rate of the silicon nitride and the active layer at the time of etching the interlayer insulator is not sufficiently high, the former has a thickness about 10 times that of the latter, so that the etching end point is determined. It is difficult to determine accurately.

Further, depending on the circuit, another problem may occur. For example, the drain 27 (
Alternatively, since it is necessary to go through the upper wiring 35 from the silicide 31) to the gate wiring 25, two contacts are passed through. Needless to say, it is desirable that the number of contacts in the circuit is small because the contact has a high probability of failure and the resistance is large. further,
Although the probability of over-etching is reduced, the silicide layer is very thin, so there is a high probability that a defect will occur at the contact portion. For this reason, the contact hole is required to be sufficiently wide, which is a problem when the circuit is highly integrated.

The present invention is a semiconductor device having the following basic configuration. That is,
A gate electrode, a gate insulating film wider than the gate electrode,
A pair of N-type or P-type impurity regions formed in the active layer;
A pair of silicide layers formed in a self-aligned manner with respect to the gate insulating film;
A metal layer in close contact with the silicide layer and selectively provided;
The silicide layer is mainly composed of a metal element constituting the metal layer and silicon (Invention 1).
.

There are several variations of this, each of which has an effect.
An upper layer wiring is provided in a layer above the gate electrode, and this and the metal layer may have at least one contact (Invention 2). For example, upper layer wiring and TFT source and drain (
The contact between the silicide layers) should be made like this. In particular, this is effective in preventing contact failure between the extremely thin silicide layer and the upper wiring, which has been a problem in the conventional example shown in FIG.

Although the active layer of the TFT is required to be extremely thin due to the required characteristics, the metal layer of the present invention is intended to form a silicide layer in the active layer, so that it is not particularly required to be thin,
It may be thick enough. In the present invention, the source and drain (silicide layer) are bonded to the entire surface of the metal layer (in an alloy), and the metal layer is in contact with the upper wiring. The probability of the former contact failure is very low, and the probability of the latter failure is significantly lower than that in the case of FIG. 2 because the metal layer is sufficiently thick. Therefore, overall, the probability of contact failure is significantly reduced.

In the above basic configuration, the gate wiring in the same layer as the gate electrode may have at least one contact with the metal layer coupled to the silicide layer (Invention 3). In this configuration, it is possible to connect the drain 27 (silicide layer 31) and the gate wiring 25 in FIG. 2 without providing a contact hole.
In general, the gate electrode / wiring and the source / drain wiring are formed with an interlayer insulator therebetween, so that a contact hole is always necessary to obtain a contact between them. Needless to say, it is advantageous in terms of circuit arrangement if a contact hole is not required to connect the gate wiring to the source and drain.

Further, the metal layer is also used as a wiring as it is as described above, but the resistivity of the metal forming the silicide is one digit or more than the resistivity of the metal used for the wiring material,
Since it is high, another metal layer made of a material having a low resistivity may be stacked on the metal layer in order to reduce the resistance of the wiring (Invention 4).
Note that the material of the metal layer is preferably composed mainly of an element selected from titanium, molybdenum, tungsten, platinum, chromium, and cobalt.

In order to obtain the semiconductor device having the above structure, it is preferable to use the following manufacturing steps. That is,
(1) Step of forming a gate insulating layer and a gate electrode on the active layer (2) Step of etching the gate insulating layer to form a gate insulating film wider than the gate electrode (3) Metal in close contact with the active layer Step of forming layer (4) Step of reacting active layer and metal layer to form silicide layer in self-alignment with gate insulating film (5) Step of selectively etching metal layer

In order to obtain the configuration of the present invention 4 described above, between the step (3) and the step (5),
It is preferable to provide a step of forming another metal layer of a material having a lower resistivity than the material of the metal layer in close contact with the metal layer. For example, double the use of a metal having low heat resistance such as aluminum. It is better to avoid step (4) involving high temperature. Therefore, the above steps are the steps (4) and (5).
).

In the above steps (1) to (5), the source and drain (impurity region) manufacturing steps are not particularly described, but it is generally desirable to form them before the step (3). In the present invention, the impurity region may or may not be formed in a self-aligned manner (with respect to the gate electrode). The following two ways are conceivable for forming in a self-aligned manner. Most generally, an impurity region forming step is provided between the first step and the second step. This is effective when a side wall is used as shown in FIG.

In that case, a step of forming an impurity region having the same conductivity type and a higher impurity concentration than the impurity region formed in the above step may be provided between the step (2) and the step (3). .
Thus, a double drain (low concentration drain) structure can be obtained. However, this step may be performed after step (3). In that case, it should be noted that it is not doped to an appropriate depth depending on the thickness of the metal layer. However, if it is after the step (5), there is no problem in doping the portion of the double drain structure.

Further, when the anodic oxidation of the gate electrode is used, the formation of the impurity region is performed between the step (2) and the step (3).
In the step (2), when the gate wiring is also exposed, the metal layer forms a junction with the gate wiring. Therefore, the configuration of the present invention 3 can be obtained by appropriate selective etching.

A known multilayer wiring technology step may be added after the above basic steps (1) to (5). That is, the following three steps are added. Thus, the configuration of the present invention 2 can be obtained.
(6) Step of forming an interlayer insulator (7) Step of etching the interlayer insulator to form a contact hole reaching the metal layer (8) Step of forming an upper layer wiring that contacts the metal layer through the contact hole

A silicide layer is formed in a self-aligned manner on the source and drain, and the metal layer used for forming the silicide layer is used for a wiring or a contact pad, thereby reducing the resistance of the circuit and increasing the degree of integration of the circuit. be able to. In particular,
(1) There is no problem of mask alignment.
(2) There are no problems in contact formation.
Such usefulness can be obtained. Thus, the characteristics, yield, reliability, and productivity of the TFT and the semiconductor circuit can be improved.

The manufacturing process of the semiconductor circuit of Example 1 is shown. The structure of a conventional TFT is shown. The manufacturing process of the semiconductor circuit of Example 2 is shown. The manufacturing process of the semiconductor circuit of Example 3 is shown. The manufacturing process of the semiconductor circuit of Example 4 is shown. FIG. 3 shows an enlarged conceptual diagram of a cross section of the TFT of Example 1; The expansion conceptual diagram of the cross section of TFT of Example 3 is shown. The manufacturing process of the semiconductor circuit of Example 5 is shown. The manufacturing process of the semiconductor circuit of Example 6 is shown. The expansion conceptual diagram of the cross section of TFT of Example 6 is shown.

FIG. 1 shows a schematic manufacturing process of the TFT of this embodiment. In this embodiment, an N-channel TFT is manufactured. If the source / drain region is formed of a P-type semiconductor, a P-channel TF is used.
It goes without saying that T can be done. The TFT of this embodiment can be used for a TFT provided in a pixel of a liquid crystal display device, a TFT used for a peripheral circuit, an image sensor, and other integrated circuits.

In this embodiment, a glass substrate coated with a silicon oxide film (not shown) having a thickness of 2000 mm is used as the substrate 1. As a coating method, a sputtering method or a plasma CVD method is used. Next, an amorphous silicon film is formed by a plasma CVD method to a thickness of 500 mm.
The film is formed to a thickness of. The film forming method and film thickness of the amorphous silicon film are determined by the embodiment and are not particularly limited. A crystalline silicon film (eg, a microcrystalline silicon film or a polycrystalline silicon film) can also be used.

Next, the amorphous silicon film is crystallized to form a crystalline silicon film. Crystallization is between 550 and 700
The heating is generally performed at 1 ° C. for 48 hours, but may be performed by laser light irradiation or strong light irradiation. The silicon film crystallized in this way is etched into an island shape for element isolation, and the active layer region 2 is determined. The active layer region is an island-shaped semiconductor region in which a source / drain region and a channel formation region are formed.

Next, a silicon oxide film 3 serving as a gate insulating layer is formed to a thickness of 1200 mm. Silicon oxide film 3
The film is formed by sputtering or plasma CVD using organosilane (eg, TEOS) and oxygen.
The method by the method is used. Next, a polycrystalline phosphorus-doped silicon film serving as a gate electrode is formed at 6000.
The film is formed to a thickness of ˜8000 mm, in this embodiment, 6000 mm. As the gate electrode, in addition to silicon, a silicide of silicon and metal, a laminate of silicon and metal, or the like can be used.

Next, the polycrystalline silicon film is patterned to form the gate electrode 4 and the gate wiring 5.
Next, an impurity P (phosphorus) for imparting an N-type conductivity is doped into the active layer 2 by ion implantation. At this time, the gate electrode 4 serves as a mask, and the source / drain regions 6 and 7 are formed in a self-aligning manner. (Fig. 1 (A))

Thereafter, annealing by laser light irradiation is performed to activate the doped P and to anneal the silicon film having deteriorated crystallization. This annealing may be performed by lamp annealing by irradiation with infrared light. Annealing with infrared rays (for example, 1.2 μm infrared rays) suppresses heating of the glass substrate by selectively absorbing the infrared rays into the silicon semiconductor, not heating the glass substrate so much, and shortening the irradiation time once. It is extremely useful.

Next, the silicon oxide film 20 is formed to a thickness of 6000 mm to 2 μm, here 9000 mm. The silicon oxide film can be formed by sputtering or plasma CV using TEOS and oxygen.
The D method is used. Then, the silicon oxide film is etched by performing anisotropic dry etching by a known RIE (reactive ion etching) method. On this occasion,
On the side surface of the gate electrode 4 having a height of 9000 mm, the thickness in the height direction is the film thickness (
It is about twice the thickness of the silicon oxide film (9000 mm).
A substantially triangular side wall 8 of silicon oxide can be left.

In this embodiment, the width of the side wall 8 of the triangular silicon oxide is about 3000 mm, but the value can be determined by the thickness of the silicon oxide film, the etching conditions, and the height of the gate electrode 4. it can. At this time, the gate insulating layer is also continuously etched to expose the source 6 and the drain 7. Further, the upper surfaces of the gate electrode 4 and the gate wiring 5 are also exposed.

On the other hand, a silicon oxide film remains under the gate electrode 4 and the gate wiring 5 and their side walls. This is called a gate insulating film in order to emphasize that it is slightly different from the previous gate insulating layer 3.
That is, the gate insulating film 3a is obtained under the gate electrode 4 and its side wall, and the gate insulating film 3b is obtained under the gate wiring 5 and its side wall. (Fig. 1 (B))
Next, a Ti (titanium) film is formed. In this example, Ti having a thickness of 3000 to 6000 mm
A film 9 is formed on the entire surface by sputtering. (Figure 1 (C))

Then, Ti and the active layer (silicon) are reacted by thermal annealing to form silicide. In this embodiment, annealing is performed at 550 to 600 ° C., and silicide layers 10 and 11 are formed on the source 6 and the drain 7, respectively. Although not explicitly shown in the figure, since silicon is used as the material for the gate wiring / electrode in this embodiment, the silicidation reaction also proceeds in that portion. However, this has an effect of reducing the resistance of the gate wiring / electrode, but does not adversely affect other characteristics.

This annealing may be performed by infrared lamp annealing. When lamp annealing is performed, lamp irradiation is performed for several minutes at 600 ° C. and for several seconds at 1000 ° C. so that the surface to be irradiated is about 600 to 1000 ° C. Here, the thermal annealing after forming the Ti film is 450 ° C., but depending on the heat resistance of the substrate, it may be performed at a temperature of 500 ° C. or higher. (Figure 1 (D))
In the figure, the silicide layers 10 and 11 are drawn in a state of reaching the bottom of the active layer. However, the reaction may be stopped halfway and the silicide layer may not reach the bottom of the active layer as shown in FIG. Good. There is no essential difference in either. (Fig. 6)

Thereafter, the Ti film is selectively etched. For etching, a known photolithography method is used, and an etching solution in which hydrogen peroxide, ammonia and water are mixed at a ratio of 5: 2: 2 is used. As a result of the above process, Ti bonded to the source 6 (silicide 10) through the contact 14a.
A Ti film (titanium wiring) 13 bonded to the film (titanium wiring) 12 and the drain 7 (silicide 11) through a contact 14b is obtained. The Ti film 13 is also joined to the gate wiring 5 at the contact 14c. (Figure 1 (E))

Next, an interlayer insulator (preferably silicon nitride or silicon oxide) 16 is deposited by plasma CVD. Further, contact holes 15a and 15b are formed in this. Then, a film of a metal wiring material is deposited by a sputtering method, and this is etched to form upper wirings 17, 1
8 is formed. Aluminum may be used as it is as a wiring material. This is because, in this embodiment, the contact portion is Ti, so that contact deterioration due to the alloying reaction is small. This is an advantage compared with the conventional example shown in FIG. (Fig. 1 (F)

The circuit including the N-channel TFT thus completed is substantially the same as the circuit obtained in FIG. However, in the present invention, an extra photolithography process is required for the selective etching process of the Ti film. However, in this embodiment, the number of contact holes can be reduced by one. In particular, if the distance between the drain 7 and the gate wiring 5 is not large, the wiring resistance is not greatly different in this embodiment or FIG.

In addition, in this embodiment, the area of the active layer can be reduced. This is because, in FIG. 2, the contact between the source / drain and the upper layer wiring is formed on the active layer, whereas in this embodiment, there is no restriction. Further, in the case of forming a contact with the gate wiring, in FIG. 2, since the contact hole is required, the gate wiring 25 in the contact portion requires a large area. Since no contact hole is required between 13 and the gate wiring 5, a small area is sufficient. This is advantageous in terms of circuit arrangement.

FIG. 3 shows a schematic manufacturing process of the TFT of this embodiment. In this embodiment, an N-channel TFT is manufactured. If the source / drain region is formed of a P-type semiconductor, a P-channel TF is used.
It goes without saying that T can be done. The TFT of this embodiment can be used for a TFT provided in a pixel of a liquid crystal display device, a TFT used for a peripheral circuit, an image sensor, and other integrated circuits.

In this embodiment, a glass substrate coated with a silicon oxide film (not shown) having a thickness of 2000 mm is used as the substrate 41. An island-like crystalline silicon film (active layer) 42 is formed on the substrate, and a silicon oxide film 43 serving as a gate insulating layer is formed to a thickness of 1200 mm so as to cover it.
Further, the gate electrode 44 and the gate wiring 45 are formed of a polycrystalline phosphorus-doped silicon film. Then N
Impurity P (phosphorus) for imparting a conductive type is doped into the active layer 42 by ion implantation. At this time, the source / drain regions 46 and 47 are formed in a self-aligning manner using the gate electrode 44 as a mask. (Fig. 3 (A))

Next, as in the first embodiment, the side wall 48 is provided on the side surface of the gate electrode / wiring. At that time, the gate insulating layer is also continuously etched to expose the source 46 and the drain 47.
Further, the upper surfaces of the gate electrode 44 and the gate wiring 45 are also exposed. On the other hand, gate insulating films 43a and 43b are obtained under the gate electrode 44 and the gate wiring 45 and their side walls. (
(Fig. 3 (B))

Next, a Ti (titanium) film is formed. In this embodiment, the thickness is 500 to thinner than that of the first embodiment.
A 1000 Ｔｉ Ti film 49 is formed on the entire surface by sputtering. (Figure 3 (C))
Then, Ti and the active layer (silicon) are reacted by thermal annealing to form silicide layers 50, 5
1 is formed in the source 46 and the drain 47. (Fig. 3 (D))
Further, an aluminum film 52 having a thickness of 6000 to 10,000 mm is deposited on the entire surface by sputtering. (Figure 3 (E))

Thereafter, the aluminum film and the Ti film are selectively etched. In etching Ti, the previously etched aluminum film is used as a mask. If both aluminum and Ti are wet-etched, it is preferable to etch the side surfaces of the aluminum by first etching the aluminum, then etching the Ti, and then again etching the aluminum. In this way, the etching step can be smoothed.

As a result of the above process, a wiring 53 joined to the source 46 (silicide 50) by the contact 55a and a wiring 54 joined to the drain 47 (silicide 51) by the contact 55b are obtained. The wiring 54 is also joined to the gate wiring 45 at the contact 55c. In this example,
The wiring 54 is a multilayer of a Ti film and an aluminum film, and has a lower resistance than that of the first embodiment. Therefore, it is possible to cope with a case where the distance between the drain 47 and the gate wiring 45 is larger than that in the first embodiment. (Fig. 3 (F))
Further, as in the first embodiment, upper layer wiring may be provided by a multilayer wiring technique.

FIG. 4 shows a schematic manufacturing process of the TFT of this embodiment. In this embodiment, a glass substrate coated with a silicon oxide film (not shown) having a thickness of 2000 mm is used as the substrate 61. An island-like crystalline silicon film (active layer) 62 is formed on the substrate, and a silicon oxide film 63 serving as a gate insulating layer is formed to a thickness of 1200 mm so as to cover it. Further, the gate electrode 64 and the gate wiring 65 are formed of a polycrystalline phosphorus-doped silicon film. Next, an impurity P for imparting an N-type conductivity type
(Phosphorus) is doped into the active layer 62 by ion implantation. At this time, the gate electrode 64 serves as a mask, and impurity regions 66 and 67 are formed in a self-aligning manner. However, the impurity concentration at this time is a low concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ . (Fig. 4 (A))

Next, as in the first embodiment, side walls 68 are provided on the side surfaces of the gate electrode / wiring. At that time, the gate insulating layer is continuously etched to expose the impurity regions 66 and 67. Further, the upper surfaces of the gate electrode 64 and the gate wiring 65 are also exposed. On the other hand, gate insulating films 63a and 63b are obtained under the gate electrode 64 and the gate wiring 65 and their side walls.

Next, the impurity P is doped again by ion implantation. At this time, the impurity concentration is set to a high concentration of 2 × 10 ^{19 to} 5 × 10 ²¹ atoms / cm ³ . Thus, the source 69 and the drain 70 are formed. (Fig. 4 (B))
Further, a Ti (titanium) film is formed. In this embodiment, a Ti film 71 having a thickness of 3000 to 6000 mm is formed on the entire surface by sputtering. (Fig. 4 (C))

Then, Ti and the active layer (silicon) are reacted by thermal annealing to form silicide layers 72, 7
3 is formed in the source 69 and the drain 70. (Fig. 4 (D))
Thereafter, the Ti film is selectively etched. The etching conditions for Ti are the same as in Example 1. As a result of the above process, the wiring 74 joined to the source 69 (silicide 72) by the contact 76a and the wiring 75 joined to the drain 70 (silicide 73) by the contact 76b.
Get. The wiring 75 is also joined to the gate wiring 65 at the contact 76c. (Fig. 4 (E
))

Further, similarly to the first embodiment, an interlayer insulator 78 is deposited by a multilayer wiring technique, contact holes 77a and 77b are formed therein, and wirings 79 and 80 are provided. (Fig. 4 (F))
In this embodiment, as shown in FIG. 7, the silicide layers 72 and 73 may not reach the bottom of the active layer. Although it is not clear in FIG. 4, in any case, a source (high concentration impurity region) 69 remains between the low concentration N-type impurity region 66 and the silicide layer 72 as shown in FIG. The same applies to the vicinity of the drain. Such a structure is effective in reducing the electric field strength in the vicinity of the source and drain. (Fig. 7)

FIG. 5 shows a schematic manufacturing process of the TFT of this embodiment. In this embodiment, a glass substrate coated with a silicon oxide film (not shown) having a thickness of 2000 mm is used as the substrate 81. An island-like crystalline silicon film (active layer) 82 is formed on the substrate, and a silicon oxide film 83 serving as a gate insulating layer is formed to a thickness of 1200 mm so as to cover it. Further, gate electrodes 84 and 85 are formed of an aluminum film. (Fig. 5 (A))

Next, the gate electrode and the gate insulating layer are processed using the anodizing technique disclosed in Japanese Patent Application Laid-Open Nos. 7-169974, 7-169975, 7-218932, etc., and the structure shown in the figure is obtained. The gate electrode is coated with a barrier type anodic oxide. Thus, the gate electrode 84a
85a and gate insulating films 83a and 83b. (Fig. 5 (B))
Next, an impurity P (phosphorus) for imparting an N-type conductivity is ion-implanted by an active layer 8.
Doping 2. At this time, the gate electrodes 84a and 85a serve as a mask, and impurity regions 86, 87, and 88 are formed in a self-aligning manner. (Fig. 5 (C))

Next, a Ti (titanium) film is formed. In this example, a T having a thickness of 3000 to 6000 mm.
An i film 89 is formed on the entire surface by sputtering. And by thermal annealing, Ti
And active layer (silicon) are reacted to form silicide layers 90, 91, and 92 in impurity regions 86-88. (Fig. 5 (D))
Thereafter, the Ti film is selectively etched. The etching conditions for Ti are the same as in Example 1. As a result of the above steps, wirings 93 and 94 are obtained. (Fig. 5 (E))
Further, similarly to the first embodiment, an interlayer insulator 95 is deposited by a multilayer wiring technique, contact holes are formed therein, and wirings 96 and 97 are provided. (Fig. 5 (F))

FIG. 8 shows a schematic manufacturing process of the TFT of this embodiment. In this embodiment, a glass substrate coated with a silicon oxide film (not shown) having a thickness of 2000 mm is used as the substrate 101. An island-like crystalline silicon film (active layer) 102 having a source 106 and a drain 107, a gate insulating film 103a, and a gate electrode 104 are formed on the substrate by using the technique disclosed in the fourth embodiment. At the same time, a gate wiring 105 having a gate insulating film 103b is formed (FIG. 8A).
))

Next, a Ti (titanium) film is formed. In this example, a T having a thickness of 3000 to 6000 mm.
An i film 109 is formed on the entire surface by sputtering. And by thermal annealing, T
i and the active layer (silicon) are reacted to form silicide layers 110 and 111 on the source 106 and the drain 107. (Fig. 8 (B))

Thereafter, the Ti film is selectively etched. The etching conditions for Ti are the same as in Example 1. As a result of the above steps, a wiring 112 bonded to the source 106 (silicide 110) through the contact 114a and a wiring 113 bonded to the drain 107 (silicide 111) through the contact 114b are obtained. Although the wiring 113 overlaps with the gate wiring 105, the gate wiring 10
No. 5 is coated with a barrier type highly insulating anodic oxide, so no junction is formed.
This portion 115 is effective as a capacity. Such a capacitor is used as an auxiliary capacitor in an active matrix liquid crystal display device. (Fig. 8 (C))

FIG. 9 shows a schematic manufacturing process of the TFT of this example. In this embodiment, a glass substrate coated with a silicon oxide film (not shown) having a thickness of 2000 mm is used as the substrate 101. An island-like crystalline silicon film (active layer) 122 is formed on the substrate, and a silicon oxide film 123 serving as a gate insulating layer is formed to a thickness of 1200 mm so as to cover it. Further, gate electrodes 124 and 125 are formed of an aluminum film. Next, an impurity P (phosphorus) for imparting an N-type conductivity is doped into the active layer 122 by ion implantation. At this time, the gate electrodes 124 and 12
5 serves as a mask, and impurity regions 126, 127, and 128 are formed in a self-aligning manner. However, the impurity concentration at this time is a low concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ .
(Fig. 9 (A))

Next, the gate insulating layer 123 is etched by a known photolithography method to expose a part of the impurity regions 126 to 128 as shown in the figure. Thus, the gate insulating film 123a
123b are obtained.
Further, a Ti (titanium) film is formed. In this embodiment, a Ti film 129 having a thickness of 3000 to 6000 mm is formed on the entire surface by a sputtering method. (Fig. 9 (B))

Then, Ti and the active layer (silicon) are reacted by thermal annealing, and the silicide layer 130,
131 and 132 are formed in the impurity regions 126 to 128.
Thereafter, the Ti film is selectively etched to obtain wirings 133 and 134. (Figure 9 (C))
Next, part of the gate insulating films 123a and 123b (as shown in FIG.
The portion overlapping (27) is etched. (Figure 9 (D))

Further, the impurity P is doped again by an ion implantation method. At this time, the impurity concentration is set to a high concentration of 2 × 10 ^{19 to} 5 × 10 ²¹ atoms / cm ³ . Thus, a high concentration impurity region 135 is obtained. (Fig. 9 (E))
In particular, this embodiment is characterized in that the series resistance is reduced by lowering the resistivity of the central impurity region by doping with a high concentration impurity. In addition, although it is not clear in FIG. 9, as shown in an enlarged view in FIG. 10, a high concentration impurity region 136 remains between the silicide layers 130 and 132 at both ends of the TFT and the low concentration impurity fishing seasons 126 and 128. To do. Such a structure is effective in reducing the electric field strength in the vicinity of the source and drain. (Fig. 10)

1. Glass substrate 2. Silicon semiconductor film (active layer)
3. Silicon oxide film (gate insulating layer)
3a, 3b, gate insulating film 4 ... gate electrode 5 ... gate wiring 6 ... source 7 ... drain 8 ... sidewall 9 ... Ti film 10, 11, ... Silicide layer 12, 13, ... Wiring 14 ... Contact part 15 ... Contact hole 16 ... Interlayer insulator 17, 18 ... Upper layer wiring

Claims (7)

A method of manufacturing a thin film transistor provided in a pixel or a peripheral circuit of a liquid crystal display device,
Forming a crystalline silicon film on a glass substrate on which a silicon oxide film is formed;
Forming a gate insulating layer on the crystalline silicon film;
Forming a gate electrode on the gate insulating layer;
An impurity element imparting N-type or P-type conductivity is added to the crystalline silicon film using the gate electrode as a mask,
Forming a side wall on the side surface of the gate electrode;
Etching the gate insulating layer that does not overlap the gate electrode and the side wall to expose the crystalline silicon film;
Forming a first metal film in contact with the exposed crystalline silicon film and the gate electrode;
Reacting the first metal film and the crystalline silicon film by thermal annealing to form a silicide layer and silicidize the upper portion of the gate electrode;
After the thermal annealing, forming a second metal film on the first metal film,
A method for manufacturing a thin film transistor, wherein the second metal film and the first metal film are selectively etched to form a metal wiring bonded to the silicide layer. A method of manufacturing a thin film transistor provided in a pixel or a peripheral circuit of a liquid crystal display device,
Forming a crystalline silicon film on a glass substrate on which a silicon oxide film is formed;
Forming a gate insulating layer on the crystalline silicon film;
Forming a gate electrode on the gate insulating layer;
Adding a first impurity element imparting N-type or P-type conductivity to the crystalline silicon film using the gate electrode as a mask;
Forming a side wall on the side surface of the gate electrode;
Etching the gate insulating layer that does not overlap the gate electrode and the side wall to expose the crystalline silicon film;
A second impurity element having the same conductivity type as the first impurity element and having a higher concentration than the first impurity element is added to the crystalline silicon film exposed using the gate electrode and the side wall as a mask. ,
Forming a first metal film in contact with the exposed crystalline silicon film and the gate electrode;
Reacting the first metal film and the crystalline silicon film by thermal annealing to form a silicide layer and silicidize the upper portion of the gate electrode;
After the thermal annealing, forming a second metal film on the first metal film,
A method for manufacturing a thin film transistor, wherein the second metal film and the first metal film are selectively etched to form a metal wiring bonded to the silicide layer. A method of manufacturing a thin film transistor provided in a pixel or a peripheral circuit of a liquid crystal display device,
Forming a crystalline silicon film on a glass substrate on which a silicon oxide film is formed;
Forming a gate insulating layer on the crystalline silicon film;
Forming a gate electrode on the gate insulating layer;
Adding a first impurity element imparting N-type or P-type conductivity to the crystalline silicon film using the gate electrode as a mask;
Forming a side wall on the side surface of the gate electrode;
Etching the gate insulating layer that does not overlap the gate electrode and the side wall to expose the crystalline silicon film;
Forming a first metal film in contact with the exposed crystalline silicon film and the gate electrode;
Reacting the first metal film and the crystalline silicon film by thermal annealing to form a silicide layer and silicidize the upper portion of the gate electrode;
After the thermal annealing, forming a second metal film on the first metal film,
Selectively etching the second metal film and the first metal film to form a metal wiring bonded to the silicide layer;
A second impurity element having the same conductivity type as the first impurity element and having a higher concentration than the first impurity element is added to the crystalline silicon film exposed using the gate electrode and the side wall as a mask. A method for manufacturing a thin film transistor. In any one of Claims 1 thru | or 3,
A method for manufacturing a thin film transistor, wherein a wiring connected to the metal wiring is formed in a region which does not overlap with the silicide layer. In any one of Claims 1 thru | or 4,
After the second metal film is selectively etched in the metal wiring, the first metal film is selectively etched using the etched second metal film as a mask, and then the second metal film is etched. A method for manufacturing a thin film transistor, characterized in that the thin film transistor is formed by etching side surfaces of the metal film. In any one of Claims 1 thru | or 5,
The method for manufacturing a thin film transistor, wherein the first metal film contains an element selected from titanium, molybdenum, tungsten, platinum, chromium, and cobalt as a main component. In any one of Claims 1 thru | or 5,
The method for manufacturing a thin film transistor, wherein the first metal film is a titanium film, and the second metal film is an aluminum film.

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