JP4298676B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The invention disclosed in this specification relates to a structure of an active matrix display device, for example, an active matrix liquid crystal display device.

  An active matrix liquid crystal display device has a structure in which thin film transistors are integrated on a quartz substrate or a glass substrate. In recent years, there has been a demand for increasing the degree of integration. On the other hand, since the liquid crystal display device is required to display a large screen, it is required to increase the area. This is a significant difference from LSI circuits that are more integrated and at the same time miniaturized.

  While an increase in area is achieved in this way, it is required to make the wiring width as thin as possible for the purpose of increasing the aperture ratio. However, when a narrow wiring is arranged in a pixel area having a large area, the influence of the resistance becomes a problem.

  Further, in an active matrix type liquid crystal display device, means for shielding a thin film transistor disposed in each pixel and shielding means called a black matrix for covering an edge of each pixel electrode are required. Generally, the thin film transistor shielding means and the black matrix are arranged separately from the wiring. Such a configuration is not preferable because it complicates the manufacturing process.

  Further, it is considered that aluminum is used as a wiring material as a means for reducing wiring resistance. However, aluminum has a problem that its electrical contact with a semiconductor or a transparent conductive film (generally an oxide conductive film such as ITO) tends to become unstable, and its reliability is low.

  An object of the invention disclosed in this specification is to obtain a structure with a high aperture ratio by a method with few manufacturing steps. It is another object of the present invention to provide a configuration in which contact instability caused by a wiring material is removed.

One of the inventions disclosed in this specification is:
A wiring connecting the semiconductor and the oxide conductive film;
The wiring has a laminated structure of a titanium film, an aluminum film, and a titanium film,
One of the titanium films is in contact with the semiconductor,
The other of the titanium films is in contact with the oxide conductive film.

  An example of the above structure is shown in FIG. FIG. 2C shows a configuration in which the drain region 110 of the thin film transistor and the pixel electrode 114 made of ITO are connected by a wiring 119 made of a laminated film of a titanium film, an aluminum film, and a titanium film.

  With such a configuration, the drain region 110 that is a semiconductor is in contact with the titanium film, and the ITO electrode 114 that is an oxide is in contact with the titanium film. The semiconductor and the titanium film can make good electrical contact. There is a problem that the contact between aluminum and the semiconductor tends to be unstable. However, such a configuration can solve the problem.

  Further, the contact between the ITO and the titanium film can be made good. In general, the contact between aluminum and ITO (generally an oxide conductive film) also becomes unstable, but this problem can also be solved by adopting such a configuration. Moreover, in addition to the above effects, the effect of using low resistance aluminum can be obtained at the same time.

Other aspects of the invention are:
An oxide conductive film constituting a pixel electrode;
A wiring connecting the oxide conductive film and a drain region of the thin film transistor;
A light shielding film for shielding the thin film transistor made of the same material as the wiring;
A light shielding film formed to cover an edge of the pixel electrode made of the same material as the wiring;
Have
The wiring has a laminated structure of a titanium film, an aluminum film, and a titanium film.

  A specific example of the above structure is shown in FIG. 2C shows a pixel electrode 114 made of ITO, a wiring 119 made of a laminated film of a titanium film, an aluminum film, and a titanium film connecting the pixel electrode 114 and the drain region 110 of the thin film transistor, and the wiring 119. The shielding film 118 which shields the thin film transistor comprised with the material which comprises is shown.

  Further, as shown in FIG. 2C from above, FIG. 3 shows a shielding film (black matrix) 301 formed by covering the edge of the ITO electrode 114 with the material constituting the wiring 119.

  What is important in the above configuration is that the wiring 119, the shielding film 118, and the black matrix 301 are obtained by patterning the same multilayer film. In other words, with such a structure, a manufacturing process can be simplified, manufacturing yield can be improved, and manufacturing cost can be reduced.

  In the invention disclosed in this specification, it is most preferable to use a titanium film in view of electrical characteristics. However, when an optical role such as a shielding film or a black matrix is considered, it is useful to use a chromium film instead of the titanium film.

  Further, an appropriate impurity of several weight percent or less may be included in the titanium film or the chromium film to control its optical characteristics and electrical characteristics.

Other aspects of the invention are:
An oxide conductive film constituting a pixel electrode;
A first wiring connecting the oxide conductive film and a drain region of the thin film transistor;
A light shielding film for shielding the thin film transistor made of the same material as the first wiring;
A light shielding film formed to cover an edge of the pixel electrode made of the same material as the first wiring;
A second wiring connected to the source region of the thin film transistor;
A lead wire made of the same material as the first wire connected to the second wire;
Have
The first wiring has a laminated structure of a titanium film, an aluminum film, and a titanium film.

  A specific example of the above structure is shown in FIG. In the structure shown in FIG. 2C, a laminated wiring of a titanium film, an aluminum film, and a titanium film indicated by 119 is shown as the first wiring. In addition, a laminated wiring of a titanium film and an aluminum film indicated by 112 is shown as the second wiring.

  As shown in FIG. 2C, by forming the wiring 119 with a laminated film of a titanium film, an aluminum film, and a titanium film, the utility of using the aluminum film having low resistance can be obtained, and at the same time, the semiconductor and titanium Good electrical contact property of the film, and further good electrical contact property between the oxide transparent conductive film and the titanium film can be utilized, and a highly reliable structure can be obtained.

  In addition, by using the three-layer film forming the wiring 119, a black matrix covering the light-shielding film 118 of the thin film transistor and the edge of the pixel electrode and a lead-out wiring from the source wiring 112 can be formed. Such a configuration is useful for improving the production yield and reducing the production cost.

  By utilizing the invention disclosed in this specification, a configuration in which contact instability caused by the wiring material is removed can be obtained.

For example, the following effects can be obtained by using the configuration shown in FIG.
(1) By making the source line 112 a laminated film of an aluminum film and a titanium film, a voltage drop in the source wiring can be suppressed. This effect is particularly useful in a large-area liquid crystal display device.
(2) By making the source line 112 a laminated film of an aluminum film and a titanium film, electrical connection between the source wiring 112 and the source region 107 can be ensured.
(3) The light shielding film 118 can be formed using a multilayer film for forming a wiring for connecting the drain region 110 and the pixel electrode 114 indicated by 119. In particular, this light shielding film can be obtained without adding a new process.
(4) The wiring 117 used for connection with the peripheral circuit can be formed simultaneously with the wiring 119. Further, the contact of the wiring 117 with the source wiring 112 and the contact of the peripheral circuit can be ensured.
(5) In the wiring 119, the contact between the drain region 110 and the ITO electrode 114 can be ensured.
(6) A black matrix can be formed simultaneously with the formation of the wiring 119.

  In this manner, a structure having multiple roles can be formed at the same time without particularly increasing the number of manufacturing steps. An active matrix liquid crystal display device having high characteristics can be obtained at low cost.

  1 and 2 show an outline of a manufacturing process of the active matrix liquid crystal display device shown in this embodiment. First, a silicon oxide film 101 is formed as a base film 102 to a thickness of 3000 mm on a glass substrate or a quartz substrate as the substrate 101. As a method for forming the base film, a plasma CVD method or a sputtering method may be used.

  This silicon oxide film has a function of suppressing diffusion of impurities from the substrate and relaxing stress acting between the substrate and the semiconductor film. When a quartz substrate is used as the substrate, it is preferable to increase the thickness of the anodic oxide film serving as the base film. This is because during heating, the quartz substrate hardly shrinks compared to the silicon thin film, and stress is easily generated between the semiconductor substrate and the semiconductor film.

  After the base film is formed, an amorphous silicon film is formed as a starting film for later forming an active layer of the thin film transistor. The thickness of this amorphous silicon film is, for example, 500 mm. As a method for forming this amorphous silicon film, a plasma CVD method or a low pressure thermal CVD method may be used.

  If the characteristics of the obtained thin film transistor may be low, the thin film transistor is formed using the amorphous silicon film as it is. In order to obtain a high-quality display, the amorphous silicon film is crystallized and transformed into a crystalline silicon film. In the following, an example of a process for transforming into a crystalline silicon film is shown.

  Here, a method for obtaining a crystalline silicon film having high crystallinity using a metal element that promotes crystallization of silicon will be described. First, a nickel acetate solution adjusted to a predetermined concentration is applied to the surface of the obtained amorphous silicon film. Then, the excess solution is blown off using a spinner. In this way, the nickel element is held in contact with the surface of the amorphous silicon film. A crystalline silicon film is obtained by performing a heat treatment at 620 ° C. for 4 hours.

  In addition to the crystallization method described above, a method using laser light irradiation, a method based on simple heating, a method based on irradiation with strong light such as infrared light, or a method combining these methods can be used.

  Then, by patterning the obtained crystalline silicon film, as shown in FIG. 1A, a base film 102 is formed on the glass substrate 101, and an active layer 103 (island-like semiconductor layer) of the thin film transistor is further formed. Get the formed state. Here, the following description will be made assuming that the active layer 103 is formed of a crystalline silicon film.

  After obtaining the state shown in FIG. 1A, a silicon oxide film 102 functioning as the gate insulating film 104 is formed to a thickness of 1000 mm by plasma CVD or sputtering. Further, an aluminum film containing 0.2 wt% scandium is formed to a thickness of 6000 mm. Further, this is patterned to form the gate electrode 105. This gate electrode 105 becomes the first layer wiring.

  It is important that the gate electrode is made of aluminum. As shown in FIG. 3, the gate electrode 105 extends from gate lines arranged in a matrix. Therefore, when the wiring resistance cannot be ignored, signal delay and malfunction occur. This problem becomes apparent particularly in a liquid crystal display device having a large area. Therefore, as shown in this embodiment, it is useful to form the gate electrode and the gate line formed simultaneously with aluminum which is a low resistance material.

  After the gate electrode 105 is formed, anodization is performed using an ethylene glycol solution of PH≈7 containing 3 to 10% tartaric acid as an electrolytic solution. By performing this anodic oxidation, an anodic oxide film 106 having a dense film quality is formed to a thickness of 2500 mm. This anodized film has a function of preventing abnormal growth of aluminum and generation of cracks. The anodic oxide film functions as a mask for forming an offset gate region in a subsequent impurity ion implantation step.

  After obtaining the state shown in FIG. 1B, impurity ions are implanted to form the source and drain regions. Here, P (phosphorus) ions are implanted by plasma doping in order to form an N-channel thin film transistor.

  By implanting P ions, the source region 107 and the drain region 110 are formed in a self-aligned manner. At the same time, the channel formation region 109 and the offset gate region 108 are also formed in a self-aligned manner. (Figure 1 (C))

  When the impurity ion implantation shown in FIG. 1C is completed, laser light irradiation is performed to anneal the source / drain regions. That is, the activated P ions are activated and the crystallinity of the region damaged by the P ion implantation is recovered.

  Then, a silicon oxide film is formed as the first interlayer insulating film 111 to a thickness of 5000 mm by plasma CVD. Then, a contact hole reaching the source region 107 is formed. Note that when a silicon oxide film is used as an interlayer insulating film, a titanium film and a silicon oxide film of a wiring to be formed later may react to form titanium oxide. In such a case, it is preferable to use a silicon nitride film instead of the silicon oxide film. A silicon oxide film and a silicon nitride film are preferably used. (Figure 1 (D))

  Next, as shown in FIG. 2A, a source wiring in contact with the source region is formed. The wiring source 112 is composed of a laminate of a titanium film and an aluminum film. Here, the thickness of the titanium film is 500 mm, and the thickness of the aluminum film is 4000 mm. A sputtering method is used as a film forming method. The source wiring 112 is the second layer wiring.

  The reason why the titanium film is provided is that when aluminum and silicon are brought into contact with each other, both of them react with each other to cause poor contact or change in contact resistance with time. As shown in FIG. 3, a contact is made to the source region of the thin film transistor extending from the wiring source 112 and arranged in each pixel.

  Next, as shown in FIG. 2B, a second interlayer insulating film 113 is formed to a thickness of 4000 mm. This second interlayer insulating film is constituted by a silicon oxide film formed by plasma CVD. Further, a silicon nitride film may be used in place of the silicon oxide film in order to prevent the titanium film from being transformed into a titanium oxide film later. Alternatively, a stacked film of a silicon oxide film and a silicon nitride film may be used. Alternatively, a stacked film of a silicon nitride film, a silicon oxide film, and a silicon nitride film may be used.

Next, an ITO electrode 114 to be a pixel electrode is formed. Besides ITO electrodes may be utilized S _n O _2. What is important here is that it is necessary to use a transparent conductive film as the pixel electrode.

  Then, contact holes 115 and 116 are formed. Reference numeral 115 denotes an extraction electrode for a source line, which is an opening for forming a wiring to be connected to a peripheral circuit. Reference numeral 116 denotes an opening for making contact between the drain region and the pixel electrode. (Fig. 2 (B))

Then, a three-layer film serving as a third-layer wiring is formed. This three-layer film is composed of a titanium film, an aluminum film, and a titanium film. As a film forming method, a sputtering method or a vapor deposition method is used. And pattern this third layer,
(1) Wiring 117 for making contact with a peripheral circuit and contact with an external circuit
(2) Light shielding film 118 for shielding the thin film transistor
(3) Wiring 119 for connecting the output (drain region 110) of the thin film transistor to the pixel electrode 114
(4) Black matrix not shown in FIG. 2 (shown as 301 in FIG. 3)
Form.

By making a three-layer structure with an aluminum film sandwiched between titanium films,
-The contact with the drain region 110 is made good.
-The contact with the second-layer wiring 112 is made good.
-The contact with the ITO electrode 114 is made good.
Such effects can be obtained.

  FIG. 3 shows the state shown in FIG. 2 as viewed from above. FIG. 3 shows one pixel as a center. A cross section taken along line A-A 'in FIG. 3 corresponds to the structure shown in FIG. FIG. 3 shows a black matrix 301 arranged so as to cover the edge of the pixel electrode 114. As is apparent from FIG. 3, in the present embodiment, the black matrix 301 and the light shielding film 118 of the thin film transistor are constituted by a connected film. However, the black matrix 301 and the light shielding film 118 may be separated separately. Note that it is not preferable to connect the light-shielding film 118 and the wiring 119 because unnecessary capacitance is formed.

  Note that FIG. 3 does not show the wiring indicated by 117 in FIG. The wiring indicated by 117 is actually in contact with the end of the source line 112 at the end of the pixel region.

  The present embodiment relates to an example in which the structure of the gate electrode is devised in the configuration shown in the first embodiment. This embodiment is characterized in that the gate electrode is composed of a laminate of a titanium film, an aluminum film, and a titanium film.

  FIG. 4 mainly shows the manufacturing process of the gate electrode. FIG. 4A shows that a titanium film is formed to a thickness of about 100 mm on a gate electrode 401 made of a silicon oxide film, and an aluminum film containing a small amount of scandium is 5000 mm thick. Further, a state is shown in which a titanium film is further formed to a thickness of about 100 mm, and a laminated film of the titanium film, the aluminum film, and the titanium film is patterned into the shape of a gate electrode.

  In FIG. 4A, a gate electrode composed of a titanium film 402, an aluminum film 403, and a titanium film 404 is shown.

  After obtaining the state shown in FIG. 4A, anodic oxidation is performed to form a dense anodic oxide film 405 around the gate electrode. The thickness of the anodic oxide film is 200 mm. Here, since an anodic oxide film of titanium and aluminum is formed, it is difficult to form the anodic oxide film with a thickness of several hundreds of angstroms or more. (Fig. 4 (B))

  Next, a silicon nitride film 406 is formed as a first interlayer insulating film to a thickness of 4000 mm by plasma CVD. (Fig. 4 (C))

  Further, a contact hole for forming an aluminum wiring 407 for contacting the gate electrode is formed, and an aluminum wiring 407 is formed in the titanium film 404 constituting the gate electrode. The aluminum wiring is formed in a peripheral circuit portion away from the portion where the thin film transistor is formed.

  With such a configuration, since the gate insulating film and the aluminum film are not in direct contact with each other, it is possible to prevent the above-grown portion of aluminum from entering the gate insulating film. And the interface characteristic between a gate electrode and a gate insulating film can be made favorable. As a result, the operation of the thin film transistor can be improved.

  Further, in the formation of the contact hole for forming the wiring 407, the etching process to the anodic oxide film on the upper surface of the gate electrode is facilitated. That is, in the state where the anodic oxide film is formed on the aluminum, it is difficult to selectively remove only the anodic oxide film. However, by adopting the configuration as shown in this embodiment, this problem is solved. Can be solved.

  By combining the structure shown in this embodiment with the structure shown in Embodiment 1, it is possible to reduce the manufacturing yield and manufacturing cost of the obtained device. In addition, the reliability of the apparatus can be increased.

A manufacturing process of an active matrix circuit will be described. A manufacturing process of an active matrix circuit will be described. An outline of the pixel region is shown. The outline | summary of the gate electrode of an Example is shown.

Explanation of symbols

101 glass substrate 102 base film (silicon oxide film)
103 Active layer (island semiconductor region)
104 Gate insulating film (silicon oxide film)
105 Gate electrode (aluminum electrode)
106 Anodized film 107 Source region 108 Offset gate region 109 Channel forming region 110 Drain region 111 Interlayer insulating film (first interlayer insulating film)
112 Source wiring (laminated film of titanium film and aluminum film)
113 Interlayer insulating film (second interlayer insulating film)
114 Pixel electrode (ITO electrode)
115 Contact opening to source wiring
116 Contour opening to drain region 117 Wiring to peripheral circuit 118 Shielding film 119 Wiring for connecting drain region and pixel electrode 301 Black matrix

Claims (8)

Form a base film on the substrate,
Forming a crystalline semiconductor film on the base film;
Forming a gate insulating film on the crystalline semiconductor film;
Forming a gate electrode on the crystalline semiconductor film through the gate insulating film;
By implanting impurity ions into the crystalline semiconductor film, a source region, a drain region, and a channel formation region are formed in a self-aligned manner,
Forming a first interlayer insulating film on the gate electrode;
Forming a source wiring electrically connected to the source region on the first interlayer insulating film;
Forming a second interlayer insulating film on the source wiring and the first interlayer insulating film;
Forming a pixel electrode on the second interlayer insulating film;
Forming a multilayer film with an aluminum film sandwiched between a first titanium film and a second titanium film on the second interlayer insulating film;
By patterning the multilayer film, a wiring electrically connected to the drain region and the pixel electrode and a black matrix that overlaps the crystalline semiconductor film and covers an edge of the pixel electrode are formed.
A method for manufacturing a semiconductor device. Form a base film on the substrate,
Forming a crystalline semiconductor film on the base film;
Forming a gate insulating film on the crystalline semiconductor film;
Forming a gate electrode on the crystalline semiconductor film through the gate insulating film;
By implanting impurity ions into the crystalline semiconductor film, a source region, a drain region, and a channel formation region are formed in a self-aligned manner,
Forming a first interlayer insulating film on the gate electrode;
Forming a source wiring electrically connected to the source region on the first interlayer insulating film;
Forming a second interlayer insulating film on the source wiring and the first interlayer insulating film;
Forming a pixel electrode on the second interlayer insulating film;
On the second interlayer insulating film, a multilayer film in which an aluminum film is sandwiched between a first chromium film and a second chromium film is formed,
By patterning the multilayer film, a wiring electrically connected to the drain region and the pixel electrode and a black matrix that overlaps the crystalline semiconductor film and covers an edge of the pixel electrode are formed.
A method for manufacturing a semiconductor device. Form a base film on the substrate,
Forming a crystalline semiconductor film on the base film;
Forming a gate insulating film on the crystalline semiconductor film;
Forming a gate electrode on the crystalline semiconductor film through the gate insulating film;
By implanting impurity ions into the crystalline semiconductor film, a source region, a drain region, and a channel formation region are formed in a self-aligned manner,
Forming a first interlayer insulating film on the gate electrode;
Forming a source wiring electrically connected to the source region on the first interlayer insulating film;
Forming a second interlayer insulating film on the source wiring and the first interlayer insulating film;
Forming a pixel electrode on the second interlayer insulating film;
Forming a multilayer film in which an aluminum film is sandwiched between a first titanium film and a second titanium film on the second interlayer insulating film;
By patterning the multilayer film, a wiring electrically connected to the drain region and the pixel electrode, a black matrix that overlaps the crystalline semiconductor film and covers an edge of the pixel electrode, and an electrical connection to the source wiring And lead-out wiring connected to the
A method for manufacturing a semiconductor device. Form a base film on the substrate,
Forming a crystalline semiconductor film on the base film;
Forming a gate insulating film on the crystalline semiconductor film;
Forming a gate electrode on the crystalline semiconductor film through the gate insulating film;
By implanting impurity ions into the crystalline semiconductor film, a source region, a drain region, and a channel formation region are formed in a self-aligned manner,
Forming a first interlayer insulating film on the gate electrode;
Forming a source wiring electrically connected to the source region on the first interlayer insulating film;
Forming a second interlayer insulating film on the source wiring and the first interlayer insulating film;
Forming a pixel electrode on the second interlayer insulating film;
Forming a multilayer film in which an aluminum film is sandwiched between a first chromium film and a second chromium film on the second interlayer insulating film;
By patterning the multilayer film, a wiring electrically connected to the drain region and the pixel electrode, a black matrix that overlaps the crystalline semiconductor film and covers an edge of the pixel electrode, and an electrical connection to the source wiring And lead-out wiring connected to the
A method for manufacturing a semiconductor device. In any one of Claims 1 thru | or 4,
A method for manufacturing a semiconductor device, wherein a silicon oxide film is formed as the base film. In any one of Claims 1 thru | or 5,
A method for manufacturing a semiconductor device, wherein a silicon oxide film, a silicon nitride film, or a stacked film of a silicon oxide film and a silicon nitride film is formed as the first interlayer insulating film. In any one of Claims 1 thru | or 6,
A method for manufacturing a semiconductor device, wherein a silicon oxide film, a silicon nitride film, or a stacked film of a silicon oxide film and a silicon nitride film is formed as the second interlayer insulating film. In any one of Claims 1 thru | or 7,
A method for manufacturing a semiconductor device, wherein a glass substrate or a quartz substrate is used as the substrate.

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