JP3060806B2 - Liquid crystal display device and method of manufacturing the same - Google Patents
Liquid crystal display device and method of manufacturing the sameInfo
- Publication number
- JP3060806B2 JP3060806B2 JP31628793A JP31628793A JP3060806B2 JP 3060806 B2 JP3060806 B2 JP 3060806B2 JP 31628793 A JP31628793 A JP 31628793A JP 31628793 A JP31628793 A JP 31628793A JP 3060806 B2 JP3060806 B2 JP 3060806B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- display device
- layer
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、液晶表示装置およびそ
の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a method for manufacturing the same.
【0002】[0002]
【従来の技術】従来のTFTアレイ構成について、図6
(a)〜(d)を用い以下に説明する。2. Description of the Related Art FIG.
This will be described below using (a) to (d).
【0003】まず第1の工程では絶縁性透明基板として
ガラス基板1上にアンダーコート膜としてSiO2膜2
を全面形成する。次に第2の工程では前記基板上にゲー
ト電極3となる第1の金属膜として、例えばAl膜もし
くはAl合金膜をパターン形成する。この時信号入力用
引出し電極となる、ゲート側のTAB実装用電極3aは
前記ゲート配線の延長端部に引き出され同ゲート材で配
置される(図6(a)参照)。In a first step, an SiO2 film 2 is formed as an undercoat film on a glass substrate 1 as an insulating transparent substrate.
Is formed over the entire surface. Next, in a second step, an Al film or an Al alloy film, for example, is pattern-formed on the substrate as a first metal film to be the gate electrode 3. At this time, the gate-side TAB mounting electrode 3a serving as a signal input lead electrode is led out to the extended end of the gate wiring and is arranged with the same gate material (see FIG. 6A).
【0004】次に第3の工程では、ゲート絶縁膜4、シ
リコン半導体層5、及びチャネル保護膜6を成膜する。
第4の工程では、ゲ−ト電極3上のチャネル保護膜6を
パタ−ニングする。次に第5の工程では、n+:シリコ
ン膜(図示せず)を形成し、将来TFTが形成されるよ
うに該n+:シリコン膜及びシリコン半導体層5をパタ
ーニングする(図6b参照)。Next, in a third step, a gate insulating film 4, a silicon semiconductor layer 5, and a channel protective film 6 are formed.
In the fourth step, the channel protective film 6 on the gate electrode 3 is patterned. Next, in a fifth step, an n +: silicon film (not shown) is formed, and the n +: silicon film and the silicon semiconductor layer 5 are patterned so as to form a TFT in the future (see FIG. 6B).
【0005】第6の工程では、画素電極7として透明導
電膜ITOを成膜しパタ−ン形成する(図6(c)参
照)。In a sixth step, a transparent conductive film ITO is formed as a pixel electrode 7 to form a pattern (see FIG. 6C).
【0006】第7の工程ではソース・ドレイン電極8と
なる第2の金属膜として例えばTi/Alをパターン形
成する。この時信号入力用引出し電極として、ソース側
のTAB実装用電極は前記ソース配線の延長端部に引き
出され同ソース材で配置される。In a seventh step, a pattern of, for example, Ti / Al is formed as a second metal film to be the source / drain electrodes 8. At this time, the TAB mounting electrode on the source side as a signal input extraction electrode is extended to the extended end of the source wiring and is arranged with the same source material.
【0007】そして第8の工程では絶縁保護膜9となる
SiNx膜を形成することで、前記ゲート側のTAB実
装用電極上3aには層間絶縁膜4及び絶縁保護膜9とし
てのSiNx膜が載置され、ソース側のTAB実装用電
極上には絶縁保護膜9としてのSiNx膜が載置され
る。In an eighth step, an SiNx film serving as an insulating protection film 9 is formed, so that an interlayer insulating film 4 and a SiNx film serving as an insulating protection film 9 are mounted on the TAB mounting electrode 3a on the gate side. The SiNx film as the insulating protection film 9 is mounted on the TAB mounting electrode on the source side.
【0008】最後に第9の工程として、該絶縁保護膜9
をパターン形成する。この時、前記層間絶縁膜4及び絶
縁保護膜9としてのSiNx膜は、例えばSF6ガスに
よるドライエッチングにてエッチ除去されることで個々
の電極材が露出され、TFTアレイ基板10が完成する
(図6(d)参照)。Finally, as a ninth step, the insulating protective film 9 is formed.
Is patterned. At this time, the SiNx film serving as the interlayer insulating film 4 and the insulating protective film 9 is etched and removed by, for example, dry etching with SF 6 gas to expose individual electrode materials, thereby completing the TFT array substrate 10 ( FIG. 6D).
【0009】そして、ゲートおよびソースの実装電極部
にTAB実装を施し、信号入力用電極を引き出す。Then, TAB mounting is performed on the mounting electrode portions of the gate and the source, and a signal input electrode is drawn out.
【0010】TAB実装構成を図7(a)および図7
(b)に示す。TABは有機フィルム11に印刷された
TAB電極12とTFTアレイ基板側の前記実装電極3
aとを接着性異方膜13中に含有させた導電粒子14を
介して電気的接続をするものである。そしてその後、保
護用として例えばシリコン樹脂15をTAB実装周囲に
塗布、硬化させて完成する。FIGS. 7A and 7B show a TAB mounting structure.
(B). TAB is a TAB electrode 12 printed on an organic film 11 and the mounting electrode 3 on the TFT array substrate side.
a are electrically connected through conductive particles 14 contained in the adhesive anisotropic film 13. After that, for protection, for example, a silicone resin 15 is applied around the TAB mounting and cured to complete.
【0011】[0011]
【発明が解決しようとする課題】液晶表示装置のアンダ
ーコート膜はガラス基板と以降のプロセスで形成される
トランジスタ層との層間にあって、ガラス基板からトラ
ンジスタへの汚染防止膜として多く一般に用いられてい
る。また、液晶表示装置のゲート、ソース引出し電極が
AlあるいはAlの合金膜で直接的に引き出されると、
湿中環境試験においてAlが腐食されやすいという問題
点があった。An undercoat film of a liquid crystal display device is located between a glass substrate and a transistor layer formed in a subsequent process, and is generally used as a film for preventing contamination from a glass substrate to a transistor. I have. Also, when the gate and source extraction electrodes of the liquid crystal display device are directly extracted with Al or an Al alloy film,
There was a problem that Al was easily corroded in a wet environment test.
【0012】[0012]
【課題を解決するための手段】前記問題点を解決するた
め、ゲート電極およびソース電極が直接外部に引き出さ
れてなる本発明の液晶表示装置は、ゲート電極となる金
属膜とソース・ドレイン電極となる金属膜がTiとAl
の積層膜で構成される構成とする。In order to solve the above-mentioned problems, a liquid crystal display device according to the present invention, in which a gate electrode and a source electrode are directly drawn to the outside, comprises a metal film serving as a gate electrode and a source / drain electrode. Metal film is Ti and Al
And a laminated film of
【0013】[0013]
【作用】前記本発明の構成によれば、ゲート電極をTi
/Alで構成することで、1層目のTiによりAlとガ
ラスとの密着性を向上させる。また、ゲート電極のTi
/Alをドライエッチングで加工し、レジストは専用剥
離剤を用いることでゲート電極加工時のガラスのエッチ
ングを回避し、ガラス基板からトランジスタ部への汚染
を防止するバッファ層となり得る。ゲート及びソース・
ドレイン電極のTAB実装用引出し電極材をTi/Al
或はTi/Al合金膜の積層膜で構成することでTAB
側電極材との電位差を確保してAl腐食を制御でき得る
等の作用を有する。According to the structure of the present invention, the gate electrode is made of Ti.
By using / Al, the adhesion between Al and glass is improved by the first layer of Ti. The gate electrode Ti
/ Al is processed by dry etching, and the resist can be used as a buffer layer that avoids etching of the glass at the time of processing the gate electrode and prevents contamination of the transistor portion from the glass substrate by using a dedicated release agent. Gate and source
The lead electrode material for TAB mounting of the drain electrode is Ti / Al
Alternatively, it is possible to form TAB by forming a laminated film of Ti / Al alloy film.
It has an effect such that the potential difference from the side electrode material can be secured to control Al corrosion.
【0014】さらには、ゲート電極およびソース電極の
外部引き出しを他の金属膜を介して変換せずに直接外部
へ引き出さすことで、コンタクトウィンドウ形成工程を
不要とし、工程削減を図ることができる。また、TAB
実装用電極材をゲート及びソース・ドレイン電極をTi
/Al或はTi/Al合金膜の積層膜で成ることにより
TAB実装用電極パターンの縮小化、実装抵抗の低減を
図ることができる。Further, by directly drawing out the gate electrode and the source electrode to the outside without conversion through another metal film, the contact window forming step becomes unnecessary and the number of steps can be reduced. Also, TAB
The mounting electrode material is Ti and the source and drain electrodes are Ti
By using a laminated film of / Al or Ti / Al alloy film, it is possible to reduce the size of the TAB mounting electrode pattern and the mounting resistance.
【0015】[0015]
【実施例】本発明の第1の実施例について図1(a)〜
(d)を用い、以下に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIGS.
This will be described below using (d).
【0016】先ず第1の工程として絶縁性透明基板とし
て例えばガラス基板1上に、ゲート電極3となる第1の
金属膜としてTi/AlやTi/Al合金膜もしくはT
i/Al/TiやTi/Al合金膜/Tiの積層膜を製
膜する。この時絶縁性透明基板上にTiが既に製膜され
たガラス基板を用いて、ゲート電極としてAlもしくは
Al/Tiを製膜する(図示せず)。First, as a first step, a Ti / Al or Ti / Al alloy film or a T / Al alloy film as a first metal film to be a gate electrode 3 is formed on, for example, a glass substrate 1 as an insulating transparent substrate.
A laminated film of i / Al / Ti or Ti / Al alloy film / Ti is formed. At this time, Al or Al / Ti is formed as a gate electrode using a glass substrate on which Ti is already formed on an insulating transparent substrate (not shown).
【0017】次にレジストパターンを形成し、二層膜の
場合にはCl2やBCl3などのガスを用いたドライエッ
チングにてパターン加工し、三層膜の場合にはSF6と
Cl2またはBCl3、CHCl3のガスを用いたドライ
エッチングによってパターン加工する。その後、レジス
ト専用剥離剤でレジスト除去する。この時、ゲート側の
TAB実装用電極3aは前記ゲート配線の延長端部に引
き出され同ゲート材で配置される(図1(a)参照)。Next, a resist pattern is formed, and in the case of a two-layer film, pattern processing is performed by dry etching using a gas such as Cl 2 or BCl 3, and in the case of a three-layer film, SF 6 and Cl 2 or Pattern processing is performed by dry etching using a gas of BCl 3 or CHCl 3 . After that, the resist is removed with a resist-specific release agent. At this time, the gate-side TAB mounting electrode 3a is led out to the extended end of the gate wiring and is arranged with the same gate material (see FIG. 1A).
【0018】次に第2の工程として、前記従来例同様に
ゲート絶縁膜4、シリコン半導体層5、及びチャネル保
護膜6を製膜する。第3の工程として、ゲ−ト電極3上
のチャネル保護膜6をパタ−ニングする。次に第4の工
程として、n+:シリコン膜6を形成し、将来TFTが
形成されるようにn+:シリコン膜6及びシリコン半導
体層5をパターニングする(図1(b)参照)。Next, as a second step, a gate insulating film 4, a silicon semiconductor layer 5, and a channel protective film 6 are formed as in the conventional example. As a third step, the channel protective film 6 on the gate electrode 3 is patterned. Next, as a fourth step, an n +: silicon film 6 is formed, and the n +: silicon film 6 and the silicon semiconductor layer 5 are patterned so as to form a TFT in the future (see FIG. 1B).
【0019】第5の工程として、画素電極7として透明
導電膜ITOを成膜しパタ−ン形成する(図1(c)参
照)。As a fifth step, a transparent conductive film ITO is formed as a pixel electrode 7 to form a pattern (see FIG. 1C).
【0020】第6の工程としてソース・ドレイン電極8
となる第2の金属膜としてTi/AlやTi/Al合金
膜もしくはTi/Al/TiやTi/Al合金膜/Ti
の積層膜を製膜する。次にレジストパターンを形成し、
前記同様二層膜の場合にはCl2やBCl3などのガス
を、三層膜の場合にはSF6とCl2またはBCl3、C
HCl3のガスを用いたドライエッチングによってパタ
ーン加工する。この時ソース側のTAB実装用電極8a
は前記ソース配線の延長端部に引き出され同ソース材で
配置される。As a sixth step, source / drain electrodes 8
Ti / Al or Ti / Al alloy film or Ti / Al / Ti or Ti / Al alloy film / Ti
Is formed. Next, a resist pattern is formed,
As described above, a gas such as Cl 2 or BCl 3 is used for a two-layer film, and SF 6 and Cl 2 or BCl 3 , C
Pattern processing is performed by dry etching using HCl 3 gas. At this time, the TAB mounting electrode 8a on the source side is used.
Is drawn out to the extended end of the source wiring and is arranged with the same source material.
【0021】そして第8の工程として絶縁保護膜9とし
てSiNx膜を形成することで、前記ゲート側のTAB
実装用電極上には層間絶縁膜4及び絶縁保護膜9として
のSiNx膜が載置され、ソース側のTAB実装用電極
上には絶縁保護膜9としてのSiNx膜が載置される。Then, as an eighth step, a SiNx film is formed as the insulating protection film 9 to thereby form the TAB on the gate side.
The SiNx film as the interlayer insulating film 4 and the insulating protection film 9 is mounted on the mounting electrode, and the SiNx film as the insulating protection film 9 is mounted on the TAB mounting electrode on the source side.
【0022】最後に第9の工程として、前記絶縁保護膜
9をパターン形成する。この時、前記層間絶縁膜4及び
絶縁保護膜9としてのSiNx膜は、例えばSF6ガス
によるドライエッチングにてエッチ除去されることで個
々の電極材が露出され、薄膜トランジスタアレイ基板1
0が完成する(図1(d)参照)。Finally, as a ninth step, the insulating protective film 9 is patterned. At this time, the SiNx film as the interlayer insulating film 4 and the insulating protective film 9 is etched and removed by, for example, dry etching with SF 6 gas to expose individual electrode materials, and the thin film transistor array substrate 1
0 is completed (see FIG. 1D).
【0023】このようなTFTアレイのTAB実装にお
けるTAB側メタルとアレイ電極メタルとの相関を電気
化学法により評価した。まず、ポテンシオガルバノスタ
ットを用いた評価系を図2に示す。Ag・AgClを参
照電極、対極にPt、電解液にKCl水溶液やNa2S
O4水溶液を用いて各種金属膜に電圧を印加し、電極電
位を測定した。TAB電極のメッキ材であるAu、S
n、アレイ電極材であるAl、Ti/Alそれら金属の
分極曲線を図3、図4に示す。その結果、Au、Snは
50mv/secでカソード分極すると、AuはSnよ
り低電圧印加で還元電流が流れ出す。一方、Alの平衡
電位はAgに対して−0.62v程度である。50mv
/secでアノード分極すると、Alの溶出に伴う酸化
電流が流れる。これに対してTi\Alは、どの電解液
でもAlよりさらにアノード側で酸化電流が流れ始め
る。そしてそれは、TABメッキ材との相関において電
位差を大きく保持しており、酸化電流値も小さく溶解し
にくい状況にあることが証明された。The correlation between the TAB side metal and the array electrode metal in such a TAB mounting of the TFT array was evaluated by an electrochemical method. First, FIG. 2 shows an evaluation system using a potentiogalvanostat. Ag / AgCl as reference electrode, Pt as counter electrode, KCl aqueous solution or Na 2 S as electrolyte
A voltage was applied to various metal films using an O 4 aqueous solution, and the electrode potential was measured. Au, S which is the plating material of the TAB electrode
n, Al and Ti / Al, which are array electrode materials, and polarization curves of these metals are shown in FIGS. As a result, when Au and Sn are cathode-polarized at 50 mv / sec, a reduction current starts flowing when Au is applied with a lower voltage than Sn. On the other hand, the equilibrium potential of Al is about -0.62 V with respect to Ag. 50mv
When anodic polarization is performed at / sec, an oxidation current flows with the elution of Al. On the other hand, in any case of Ti\Al, an oxidation current starts to flow further on the anode side than Al in any electrolytic solution. And it proved that the potential difference was kept large in correlation with the TAB plating material, the oxidation current value was small, and it was difficult to dissolve.
【0024】本発明の第2の実施例について図5(a)
〜図5(d)を用い、以下に説明する。FIG. 5A shows a second embodiment of the present invention.
This will be described below with reference to FIG.
【0025】前記第1の実施例ではゲート、ソース、ド
レイン電極材料にTi/Alの二層構造を用いたが第2
の実施例ではTi/Al/Tiの三層構造にし、最終工
程の絶縁保護膜パターン形成において層間絶縁膜6及び
絶縁保護膜9としてのSiNx膜とともに、上層Ti層
を例えばSF6ガスによるドライエッチングにてエッチ
除去する。これによって個々の電極面にAl材が露出さ
れ、薄膜トランジスタアレイ基板10が完成する(図5
(d)参照)。In the first embodiment, a gate / source / drain electrode material has a two-layer structure of Ti / Al.
In this embodiment, the upper layer Ti layer is dry-etched by, for example, SF 6 gas together with the SiNx film as the interlayer insulating film 6 and the insulating protection film 9 in the final step of forming the insulating protection film pattern in the three-layer structure of Ti / Al / Ti. Remove by etching. As a result, the Al material is exposed on the individual electrode surfaces, and the thin film transistor array substrate 10 is completed.
(D)).
【0026】前記三層構造の上層Tiは、ゲート電極の
場合熱工程によるAlヒロック制御膜として、またソー
ス、ドレイン電極場合には透明電極後付け構成すなわち
ITO/ソース・ドレイン構成におけるフォトプロセス
での現像液による電食防止膜として有効である。なお、
前記TiとAlの積層膜から成る電極構造は、連続製膜
に限らない。The upper layer Ti of the three-layer structure is used as an Al hillock control film by a thermal process in the case of a gate electrode, and is developed by a photo process in a post-transparent electrode structure, ie, an ITO / source / drain structure in the case of source and drain electrodes. It is effective as an electrolytic corrosion prevention film by liquid. In addition,
The electrode structure composed of the laminated film of Ti and Al is not limited to the continuous film formation.
【0027】さらに、上記第1、第2の実施例では電極
構造を二層構造と三層構造に区分しているが、必要に応
じてゲート電極とソース、ドレイン電極の構造を選択す
ればよい。Further, in the first and second embodiments, the electrode structure is divided into a two-layer structure and a three-layer structure. However, the structure of the gate electrode, the source and the drain electrode may be selected as required. .
【0028】本実施例ではアンダーコート膜形成工程を
削除しているが、絶縁性透明基板に予めSiO2膜が形
成されて成るガラス基板を用いても、何等支障のないこ
とは言うまでもない。Although the undercoat film forming step is omitted in this embodiment, it goes without saying that there is no problem even if a glass substrate in which an SiO2 film is formed in advance on an insulating transparent substrate is used.
【0029】[0029]
【発明の効果】本発明の構成によれば、ゲート電極を一
層目をTiで構成することで、TiとAlとガラスとの
密着性を向上できる。また、ゲート電極のTi・Alの
積層膜をドライエッチングで加工し、レジストは専用剥
離剤を用いることでゲート電極加工時のガラスのエッチ
ングを回避し、前記Tiはガラス基板からトランジスタ
部への汚染を防止するバッファ層となり得る。従って、
従来必須となっていたアンダーコート膜が不要となり工
程削減が図られる。また、ゲート及びソース・ドレイン
電極のTAB実装用引出し電極材をTi/Al或はTi
/Al合金膜もしくはTi/Al/Tiの積層膜で構成
することで、TAB側電極材との電位差を確保してAl
腐食を抑制できる。Al腐食についてはAuメッキされ
たTAB電極との相関において特に有効であり信頼性の
高い液晶表示装置を得ることができる。According to the constitution of the present invention, the adhesion between Ti, Al and glass can be improved by forming the first layer of the gate electrode with Ti. In addition, the laminated film of Ti / Al of the gate electrode is processed by dry etching, and the resist uses a special release agent to avoid etching of the glass at the time of processing the gate electrode. Can be a buffer layer for preventing Therefore,
The undercoat film, which is conventionally required, is not required, and the number of steps can be reduced. Also, the lead electrode material for TAB mounting of the gate and source / drain electrodes is made of Ti / Al or Ti.
/ Al alloy film or a laminated film of Ti / Al / Ti to secure the potential difference from the TAB side electrode material
Corrosion can be suppressed. Al corrosion is particularly effective in correlation with an Au-plated TAB electrode, and a highly reliable liquid crystal display device can be obtained.
【0030】さらには、ゲート電極およびソース電極の
外部引き出しを他の金属膜を介して変換せずに直接外部
へ引き出さすことで、コンタクトウィンドウ形成工程を
不要とし、さらなる工程削減を図ることができる。ま
た、TAB実装用電極材をゲート及びソース・ドレイン
電極とも同一の金属膜、Ti/Al或はTi/Al合金
膜もしくはTi/Al/Tiの積層膜で構成することに
より実装抵抗の低減、TAB実装用電極パターンの縮小
化ができる。Furthermore, the external extraction of the gate electrode and the source electrode is directly extracted to the outside without conversion through another metal film, so that the step of forming a contact window becomes unnecessary, and the number of steps can be further reduced. . Also, by forming the TAB mounting electrode material with the same metal film as the gate and source / drain electrodes, a Ti / Al or Ti / Al alloy film or a laminated film of Ti / Al / Ti, the mounting resistance is reduced, and the TAB is reduced. The mounting electrode pattern can be reduced in size.
【図1】本発明の実施例第1のアレイ工程断面図FIG. 1 is a sectional view of a first array process according to an embodiment of the present invention.
【図2】電気化学評価系FIG. 2 Electrochemical evaluation system
【図3】分極曲線結果Fig. 3 Polarization curve results
【図4】分極曲線結果FIG. 4 Polarization curve results
【図5】本発明の実施例第2のアレイ工程断面図FIG. 5 is a sectional view of a second array process according to the embodiment of the present invention.
【図6】従来のアレイ工程断面図FIG. 6 is a sectional view of a conventional array process.
【図7】従来アレイのTAB実装構成断面図FIG. 7 is a cross-sectional view of a conventional array in a TAB mounting configuration.
1 ガラス基板 2 アンダーコート膜 3 ゲート電極 4 ゲート絶縁膜 7 画素電極 8 ソース・ドレイン電極 9 絶縁保護膜 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Undercoat film 3 Gate electrode 4 Gate insulating film 7 Pixel electrode 8 Source / drain electrode 9 Insulation protective film
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 29/786 G02F 1/1365 ──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 29/786 G02F 1/1365
Claims (5)
表示装置において、薄膜トランジスタのゲート電極の信
号入力用外部引出し電極が直接外部へ引き出されて成
り、他の金属膜を介さずに、実装用電極と電気的に接続
され、前記ゲート電極の電極構成が下層Tiと上層Al
の積層膜または下層Tiと上層Al合金の積層膜のいず
れかの積層膜で構成されることを特徴とする液晶表示装
置。In a liquid crystal display device forming a thin film transistor array, a signal of a gate electrode of the thin film transistor is provided.
The external extraction electrode for signal input is directly
And electrically connected to the mounting electrodes without intervening other metal films
The electrode configuration of the gate electrode is a lower layer Ti and an upper layer Al
Laminated film or laminated film of lower Ti and upper Al alloy
A liquid crystal display device comprising a laminated film .
表示装置において、薄膜トランジスタのゲート電極の信
号入力用外部引出し電極が直接外部へ引き出されて成
り、他の金属膜を介さずに、実装用電極と電気的に接続
され、前記ゲート電極の電極構成が下層Tiと中層Al
と上層Tiの積層膜または下層Tiと中層Al合金と上
層Tiの積層膜のいずれかの積層膜で構成されることを
特徴とする液晶表示装置。2. A liquid crystal forming a thin film transistor array.
In a display device, a signal of a gate electrode of a thin film transistor is used.
The external extraction electrode for signal input is directly
And electrically connected to the mounting electrodes without intervening other metal films
The electrode configuration of the gate electrode is a lower layer Ti and a middle layer Al
And upper layer Ti or laminated layer of lower layer Ti and middle layer Al alloy and upper layer
That any one of the stacked films of the layer Ti
Characteristic liquid crystal display device .
表示装置において、薄膜トランジスタのソース電極の信
号入力用外部引出し電極が直接外部へ引き出されて成
り、実装用電極と電気的に接続され、前記ソース電極の
電極構成が下層Tiと中層Alと上層Tiの積層膜また
は下層Tiと中層Al合金と上層Tiの積層膜のいずれ
かの積層膜で構成されることを特徴とする液晶表示装
置。3. A liquid crystal forming a thin film transistor array.
In the display device, the signal of the source electrode of the thin film transistor is used.
The external extraction electrode for signal input is directly
Is electrically connected to the mounting electrode, and is electrically connected to the source electrode.
The electrode configuration is a laminated film of lower Ti, middle Al and upper Ti
Is any of the stacked films of lower Ti, middle Al alloy and upper Ti
Liquid crystal display device characterized by comprising a multilayer film
Place .
表示装置において、薄膜トランジスタのゲート電極の信
号入力用外部引出し電極が直接外部へ引き出されて成
り、前記外部引き出し電極が他の金属膜を介さずに、T
AB電極と導電性粒子により電気的に接続され、前記ゲ
ート電極の電極構成が下層Tiと上層Alの積層膜また
は下層Tiと上層Al合金の積層膜のいずれかの積層膜
で構成されることを特徴とする液晶表示装置。 4. A liquid crystal forming a thin film transistor array.
In a display device, a signal of a gate electrode of a thin film transistor is used.
The external extraction electrode for signal input is directly
In this case, the external lead-out electrode does not pass through another metal film,
The electrode is electrically connected to the AB electrode by conductive particles.
The electrode configuration of the gate electrode is a laminated film of lower Ti and upper Al or
Is a laminated film of the lower Ti and the upper Al alloy
A liquid crystal display device comprising:
表示装置において、薄膜トランジスタのゲート電極の信
号入力用外部引出し電極が直接外部へ引き出されて成
り、前記外部引き出し電極が他の金属膜を介さずに、T
AB電極と導電性粒子により電気的に接続され、前記ゲ
ート電極の電極構成が下層Tiと中層Alと上層Tiの
積層膜または下層Tiと中層Al合金と上層Tiの積層
膜のいずれかの積層膜で構成されることを特徴とする液
晶表示装置。 5. A liquid crystal forming a thin film transistor array.
In a display device, a signal of a gate electrode of a thin film transistor is used.
The external extraction electrode for signal input is directly
In this case, the external lead-out electrode does not pass through another metal film,
The electrode is electrically connected to the AB electrode by conductive particles.
The electrode configuration of the lower electrode is the lower layer Ti, the middle layer Al, and the upper layer Ti.
Laminated film or lamination of lower layer Ti, middle layer Al alloy and upper layer Ti
Liquid characterized by being composed of any one of laminated films of a film
Crystal display device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31628793A JP3060806B2 (en) | 1993-12-16 | 1993-12-16 | Liquid crystal display device and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31628793A JP3060806B2 (en) | 1993-12-16 | 1993-12-16 | Liquid crystal display device and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07169967A JPH07169967A (en) | 1995-07-04 |
JP3060806B2 true JP3060806B2 (en) | 2000-07-10 |
Family
ID=18075433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31628793A Expired - Fee Related JP3060806B2 (en) | 1993-12-16 | 1993-12-16 | Liquid crystal display device and method of manufacturing the same |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3060806B2 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3744980B2 (en) | 1995-07-27 | 2006-02-15 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JPH10198292A (en) | 1996-12-30 | 1998-07-31 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
US5994156A (en) * | 1997-09-12 | 1999-11-30 | Sharp Laboratories Of America, Inc. | Method of making gate and source lines in TFT LCD panels using pure aluminum metal |
JP3362008B2 (en) | 1999-02-23 | 2003-01-07 | シャープ株式会社 | Liquid crystal display device and manufacturing method thereof |
KR100331887B1 (en) * | 1999-09-14 | 2002-04-09 | 구본준, 론 위라하디락사 | A gate pattern of thin film transistor and a method of fabricating the same |
JP5408829B2 (en) * | 1999-12-28 | 2014-02-05 | ゲットナー・ファンデーション・エルエルシー | Method for manufacturing active matrix substrate |
JP2001257350A (en) | 2000-03-08 | 2001-09-21 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its preparation method |
SG160191A1 (en) * | 2001-02-28 | 2010-04-29 | Semiconductor Energy Lab | Semiconductor device and manufacturing method thereof |
JP2002328396A (en) * | 2001-04-26 | 2002-11-15 | Nec Corp | Liquid crystal display device and its manufacturing method |
TWI242671B (en) | 2003-03-29 | 2005-11-01 | Lg Philips Lcd Co Ltd | Liquid crystal display of horizontal electronic field applying type and fabricating method thereof |
KR100538328B1 (en) | 2003-06-20 | 2005-12-22 | 엘지.필립스 엘시디 주식회사 | Liquid Crystal Display Device And Fabricating Method Thereof |
JP4298676B2 (en) * | 2005-05-16 | 2009-07-22 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
JP2008209931A (en) * | 2008-03-12 | 2008-09-11 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device |
JP2012053467A (en) * | 2011-09-14 | 2012-03-15 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device |
JP2012168567A (en) * | 2012-06-14 | 2012-09-06 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device, personal computer, display, and electronic book |
CN110649153B (en) * | 2019-09-26 | 2022-09-30 | 中电科技集团重庆声光电有限公司 | Multilayer metal film bonding layer structure and preparation method thereof |
-
1993
- 1993-12-16 JP JP31628793A patent/JP3060806B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH07169967A (en) | 1995-07-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3060806B2 (en) | Liquid crystal display device and method of manufacturing the same | |
JPH055898A (en) | Thin-film element forming panel | |
TW594357B (en) | Manufacturing method of active matrix substrate | |
JP2786628B2 (en) | Liquid crystal panel electrode structure | |
KR950008931B1 (en) | Manufacturing method of display pannel | |
TW200939177A (en) | Gate driver-on-array and method of making the same | |
KR20070053472A (en) | Display substrate and method of fabricating the same | |
JP3106786B2 (en) | Semiconductor device and manufacturing method thereof | |
JP3318652B2 (en) | Liquid crystal display device and method of manufacturing TFT array substrate used therein | |
JP2988159B2 (en) | Liquid crystal display | |
JP3094610B2 (en) | Method for manufacturing thin film transistor | |
JP3670580B2 (en) | Liquid crystal display device and manufacturing method thereof | |
JP3195837B2 (en) | Liquid crystal display device and manufacturing method thereof | |
JP3249284B2 (en) | Manufacturing method of liquid crystal display device | |
KR100623820B1 (en) | Lcd and method for manufacturing lcd | |
JPH07142533A (en) | Semiconductor device | |
JP3599174B2 (en) | Thin film transistor panel and method of manufacturing the same | |
JP3197942B2 (en) | Method for manufacturing electronic device having transparent conductive film | |
JP3406292B2 (en) | Liquid crystal display | |
KR100537879B1 (en) | manufacturing method of thin film transistor and substrate for liquid crystal display having the same | |
JPH10268345A (en) | Liquid crystal display device and its manufacture | |
JPH10307303A (en) | Liquid crystal display substrate, its production and liquid crystal display device | |
JP3104356B2 (en) | Thin film transistor panel and method of manufacturing the same | |
JPH0629206A (en) | Method and apparatus for manufacture semiconductor device | |
JP2980803B2 (en) | Method of forming metal wiring |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080428 Year of fee payment: 8 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090428 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100428 Year of fee payment: 10 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100428 Year of fee payment: 10 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |