CN110047848B - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
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- CN110047848B CN110047848B CN201910260551.4A CN201910260551A CN110047848B CN 110047848 B CN110047848 B CN 110047848B CN 201910260551 A CN201910260551 A CN 201910260551A CN 110047848 B CN110047848 B CN 110047848B
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- 239000000758 substrate Substances 0.000 title claims abstract description 74
- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 22
- 230000003647 oxidation Effects 0.000 claims abstract description 14
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 14
- 150000001875 compounds Chemical class 0.000 abstract description 7
- 150000002736 metal compounds Chemical class 0.000 abstract description 6
- 239000011810 insulating material Substances 0.000 abstract description 5
- 239000007788 liquid Substances 0.000 abstract description 5
- 238000000151 deposition Methods 0.000 description 7
- 239000002131 composite material Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides an array substrate and a preparation method thereof, wherein a source drain electrode layer is formed on a grid electrode insulating layer firstly, and metal in a channel region on the source drain electrode layer is processed into a corresponding metal compound or an insulating material of a compound through ion doping treatment, so that a source electrode region, a drain electrode region and a channel region which are arranged on the same layer are formed; and forming an active layer on the source drain layer. The method does not relate to an etching process, and solves the problems that the electric property of the array substrate is influenced and the reliability is even generated due to the fact that the active layer is damaged by etching liquid when the source electrode and the drain electrode are etched. Meanwhile, smaller channels can be formed through oxidation treatment, and a smaller array substrate is manufactured, so that the performance of the array substrate is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
The performance of the array substrate, which is a main driving element in the current liquid crystal display device and active matrix organic light emitting diode display device, is directly related to the development direction of the display device.
However, in the conventional array substrate with the back channel etching structure, the active layer is formed first, then the source drain layer is formed, and then the source drain layer is etched to form the source and the drain, so that the active layer is easily damaged by the etching solution during the etching of the source drain, thereby affecting the electrical property of the array substrate and even causing the problem of reliability.
Therefore, the existing array substrate preparation technology has the technical problem that the active layer is etched by the etching liquid, and needs to be improved.
Disclosure of Invention
The invention provides an array substrate and a preparation method thereof, which solve the technical problem that an active layer is etched by etching liquid in the existing array preparation technology.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides an array substrate, which comprises:
a substrate;
a gate layer formed on the substrate;
a gate insulating layer formed on the gate layer;
a source drain layer formed on the gate insulating layer;
an active layer formed on the source drain layer;
the source and drain layers comprise a source region, a drain region and a channel region, the source region, the drain region and the channel region are arranged in the same layer, and the channel region is formed by doping the source and drain layers.
In the array substrate provided by the invention, the source drain layer is made of metal.
In the array substrate provided by the invention, the metal material of the source region and the drain region is aluminum, and the material of the channel region is aluminum oxide.
In the array substrate provided by the invention, the active layer is made of semiconductor materials.
In the array substrate provided by the invention, the material of the active layer is polysilicon.
Further, the present invention also provides a method for preparing an array substrate, which comprises:
providing a substrate;
forming a gate layer on the substrate;
forming a gate insulating layer on the gate layer;
forming a source drain layer on the gate insulating layer;
processing the source drain layer to form a source region, a drain region and a channel region;
forming an active layer on the source drain layer;
a passivation layer is formed on the active layer.
In the array substrate preparation method provided by the invention, the step of processing the source and drain layers to form a source region, a drain region and a channel region comprises the following steps:
patterning the source drain layer to form a circuit region;
and doping the circuit region to form a source region, a drain region and a channel region.
In the preparation method of the array substrate provided by the invention, the step of doping the circuit region to form the source region, the drain region and the channel region comprises the following steps:
determining a doped region;
and doping the doped region to form the channel region, and further determining the source region and the drain region.
In the array substrate manufacturing method provided by the invention, the step of determining the doped region comprises the following steps:
and forming a patterned light resistance layer on the source drain metal layer, wherein the patterned light resistance layer surrounds a doped region on the source drain metal layer.
In the array substrate manufacturing method provided by the invention, the doping region includes:
and oxidizing the metal in the doped region by means of heating oxidation or plasma oxidation to oxidize the metal in the doped region into an insulated metal oxide.
The invention has the beneficial effects that: the invention provides an array substrate and a preparation method thereof, wherein a source drain electrode layer is formed on a grid electrode insulating layer firstly, and metal in a channel region on the source drain electrode layer is processed into a corresponding metal compound or an insulating material of a compound through ion doping treatment, so that a source electrode region, a drain electrode region and a channel region which are arranged on the same layer are formed; and forming an active layer on the source drain layer. The method does not relate to an etching process, and solves the problems that the electric property of the array substrate is influenced and the reliability is even generated due to the fact that the active layer is damaged by etching liquid when the source electrode and the drain electrode are etched. Meanwhile, smaller channels can be formed through oxidation treatment, and a smaller array substrate is manufactured, so that the performance of the array substrate is improved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a conventional array substrate;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
Detailed Description
While the embodiments and/or examples of the present invention will be described in detail and fully with reference to the specific embodiments thereof, it should be understood that the embodiments and/or examples described below are only a part of the embodiments and/or examples of the present invention and are not intended to limit the scope of the invention. All other embodiments and/or examples, which can be obtained by a person skilled in the art without making any inventive step, based on the embodiments and/or examples of the present invention, belong to the scope of protection of the present invention.
The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
Fig. 1 is a schematic structural diagram of a conventional array substrate, and as shown in the figure, the conventional array substrate is obtained by sequentially forming a gate electrode layer 2, a gate insulating layer 3, an active layer 4, and a source drain layer 5 on a substrate 1. In the process of forming the source and drain electrodes, a source and drain electrode metal layer is formed, and then a predetermined portion of the source and drain electrode metal layer is etched by a channel etching technique to form a source region 51, a drain region 52, and a channel region 53 as shown in the figure.
However, in the etching technique, the etching solution may cause damage to the active layer located below the source/drain layer, which may affect the electrical property of the array substrate and even cause a reliability problem.
In order to solve the above technical problems, the present invention provides an array substrate.
In one embodiment, as shown in fig. 2, the array substrate provided by the present invention includes: the transistor comprises a substrate 1, a grid electrode layer 2 formed on the substrate 1, a grid electrode insulating layer 3 formed on the substrate 1 and the grid electrode layer 2, a source drain electrode layer 5 formed on the grid electrode insulating layer 3, and an active layer 4 formed on the source drain electrode layer 5.
The source/drain layer 5 includes a source region 51, a drain region 52, and a channel region 53, the source region 51, the drain region 52, and the channel region 53 are disposed in the same layer, and the channel region 53 is formed by doping the source/drain layer.
The source drain layer is made of metal, the metal in the preset drain region is doped, the material in the preset drain region is changed into a compound or a compound of the metal, and the compound or the compound of the metal is an insulating material. The source-drain layer 5 is defined as the source region 51, the drain region 52, and the channel region 53.
In one embodiment, the metal material of the source region 51 and the drain region 52 is aluminum, and the material of the channel region 53 is aluminum oxide formed by oxygen doping of aluminum metal through an oxidation process.
The active layer 4 is a semiconductor material.
In one embodiment, the material of the active layer 4 is polysilicon.
The gate insulating layer 3 is made of silicon oxide, silicon nitride, or a composite material formed by overlapping silicon oxide and silicon nitride.
In summary, in the array substrate provided by the present invention, the source/drain layer 5 is formed first, the material of the source/drain layer 5 is doped to form the source region 51, the drain region 52, and the channel region 53, and then the active layer 4 is formed on the source/drain layer 5, so that the influence on the active layer 4 in the process of forming the source/drain layer 5 is not involved.
Based on the array substrate, the invention also provides a preparation method of the array substrate.
In one embodiment, as shown in fig. 3, the method for manufacturing the array substrate includes:
s301, providing the substrate 1.
The substrate 1 is a glass substrate.
And S302, forming a gate layer 2 on the substrate 1.
The material of the gate layer 2 comprises one or more of molybdenum, aluminum, copper, titanium and chromium.
In one embodiment, the material of the gate layer 2 is copper.
In one embodiment, the step of forming the gate 2 on the substrate 1 includes: depositing a first metal film on the substrate 1, and patterning the first metal film by a photoetching process to obtain the gate layer 2.
And S303, forming a gate insulating layer 3 on the gate electrode layer 2.
The gate insulating layer 3 is made of silicon oxide, silicon nitride, or a composite material formed by overlapping silicon oxide and silicon nitride.
In one embodiment, the step of forming the gate insulating layer 3 on the gate layer 2 includes: and depositing a gate insulating layer 3 on the gate electrode layer 2 by adopting a chemical vapor deposition method.
And S304, forming a source drain layer 5 on the gate insulating layer 3.
The source drain layer 5 is made of metal.
In one embodiment, the source/drain layer 5 is made of aluminum metal.
In one embodiment, the step of forming the source/drain layer 5 on the gate insulating layer 3 includes:
a second metal film is deposited on the gate insulating layer 3.
S305, processing the source/drain layer 5 to form a source region 51, a drain region 52, and a channel region 53;
the source and drain layer 5 includes a source region 51, a drain region 52, and a channel region 53, the source region 51, the drain region 52, and the channel region 53 are disposed in the same layer, and the channel region 53 is formed by doping the source and drain layer.
The source region 51 and the drain region 52 are made of a metal, the channel region 53 is made of a metal compound or a composite formed by doping the metal, and the metal compound or the composite is an insulating material.
In one embodiment, the metal material of the source region 51 and the drain region 52 is aluminum, and the material of the channel region 53 is aluminum oxide formed by oxygen doping of aluminum metal through an oxidation process.
In one embodiment, the step of processing the source/drain layer 5 to form the source region 51, the drain region 52, and the channel region 53 includes:
patterning the source drain layer 5 to form a circuit region;
the circuit region is doped to form a source region 51, a drain region 52, and a channel region 53.
In one embodiment, the doping the circuit region to form the source region 51, the drain region 52, and the channel region 53 includes:
determining a doped region;
the doped region is doped to form the channel region 53, thereby defining the source region 51 and the drain region 52.
In one embodiment, the step of determining the doped region includes:
and forming a patterned light resistance layer on the source drain metal layer, wherein the patterned light resistance layer surrounds a doped region on the source drain metal layer.
In one embodiment, the doping the doped region comprises:
the metal of the doped region is subjected to oxidation doping treatment by means of thermal oxidation or plasma doping, and the metal of the doped region is treated into a corresponding metal compound or composite, thereby forming an insulator.
And S306, forming an active layer 4 on the source drain layer 5.
The active layer 4 is a semiconductor material.
In one embodiment, the material of the active layer 4 is polysilicon.
In one embodiment, the step of forming the active layer 4 on the source drain layer 5 includes:
and depositing a polysilicon material on the source drain layer 5 to form the active layer 4.
And S307, forming a passivation layer on the active layer 4.
The array substrate and the method for fabricating the same according to the present invention will be further explained with reference to the embodiments.
Providing a substrate 1, sequentially depositing a gate layer 2 on the substrate 1, depositing a gate insulating layer 3 on the substrate 1 and the gate layer 2, and depositing a source drain layer 5 on the gate insulating layer 3, wherein the source drain layer 5 is a metal aluminum layer; forming a patterned light resistance layer on the source drain electrode layer 5, wherein the patterned light resistance layer surrounds a doped region on the source drain electrode metal layer; performing oxidation doping treatment on the metal aluminum in the doped region by means of thermal oxidation or plasma oxidation, etc., so as to oxidize the metal aluminum in the doped region into an insulator of the metal aluminum, thereby forming the channel region 53 and further defining the source region 51 and the drain region 52; depositing a polysilicon material on the source drain layer 5 to form the active layer 4; a passivation layer is formed on the active layer 4.
According to the above embodiments: the invention provides an array substrate and a preparation method thereof, wherein a source drain electrode layer is formed on a grid electrode insulating layer firstly, and metal in a channel region on the source drain electrode layer is processed into a corresponding metal compound or an insulating material of a compound through ion doping treatment, so that a source electrode region, a drain electrode region and a channel region which are arranged on the same layer are formed; and forming an active layer on the source drain layer. The method does not relate to an etching process, and solves the problems that the electric property of the array substrate is influenced and the reliability is even generated due to the fact that the active layer is damaged by etching liquid when the source electrode and the drain electrode are etched. Meanwhile, smaller channels can be formed through oxidation treatment, and a smaller array substrate is manufactured, so that the performance of the array substrate is improved.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. An array substrate, comprising
A substrate;
a gate layer formed on the substrate;
a gate insulating layer formed on the gate layer;
a source drain layer formed on the gate insulating layer;
an active layer formed on the source drain layer;
the source and drain layers comprise a source region, a drain region and a channel region, the source region, the drain region and the channel region are arranged in the same layer, and the channel region is positioned between the source region and the drain region; the channel region is formed by doping the source drain layer and is insulated.
2. The array substrate of claim 1, wherein the source drain layer is made of metal.
3. The array substrate of claim 2, wherein the metal material of the source region and the drain region is aluminum, and the material of the channel region is aluminum oxide.
4. The array substrate of claim 1, wherein the active layer is a semiconductor material.
5. The array substrate of claim 4, wherein the material of the active layer is polysilicon.
6. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate;
forming a gate layer on the substrate;
forming a gate insulating layer on the gate layer;
forming a source drain layer on the gate insulating layer;
processing the source and drain layers to form a source region, a drain region and a channel region which are arranged in the same layer, wherein the channel region is positioned between the source region and the drain region, and is formed by doping the source and drain layers and is insulated;
forming an active layer on the source drain layer;
a passivation layer is formed on the active layer.
7. The method for manufacturing the array substrate according to claim 6, wherein the step of processing the source and drain layers to form a source region, a drain region, and a channel region comprises:
patterning the source drain layer to form a circuit region;
and doping the circuit region to form a source region, a drain region and a channel region.
8. The method for manufacturing the array substrate according to claim 7, wherein the step of doping the circuit region to form a source region, a drain region and a channel region comprises:
determining a doped region;
and doping the doped region to form the channel region, and further determining the source region and the drain region.
9. The method for manufacturing an array substrate of claim 8, wherein the step of determining the doping region comprises:
and forming a patterned light resistance layer on the source drain electrode layer, wherein the patterned light resistance layer surrounds a doped region on the source drain electrode layer.
10. The method for manufacturing an array substrate according to claim 8, wherein the doping the doped region comprises:
and oxidizing the metal in the doped region by means of heating oxidation or plasma oxidation to oxidize the metal in the doped region into an insulated metal oxide.
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| CN104701264A (en) * | 2015-03-25 | 2015-06-10 | 京东方科技集团股份有限公司 | Organic light emitting diode display panel and manufacturing method thereof and display device |
| CN105390551A (en) * | 2015-10-28 | 2016-03-09 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate, and display device |
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| CN103199114B (en) * | 2013-03-25 | 2016-11-16 | 合肥京东方光电科技有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and display device |
| US10763451B2 (en) * | 2016-09-01 | 2020-09-01 | Innolux Corporation | Display device |
| CN107425075B (en) * | 2017-05-17 | 2020-05-29 | 厦门天马微电子有限公司 | Thin film transistor device, manufacturing method thereof, array substrate and display device |
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| CN104701264A (en) * | 2015-03-25 | 2015-06-10 | 京东方科技集团股份有限公司 | Organic light emitting diode display panel and manufacturing method thereof and display device |
| CN105390551A (en) * | 2015-10-28 | 2016-03-09 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, array substrate, and display device |
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