CN110047848A - A kind of array substrate and preparation method thereof - Google Patents
A kind of array substrate and preparation method thereof Download PDFInfo
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- CN110047848A CN110047848A CN201910260551.4A CN201910260551A CN110047848A CN 110047848 A CN110047848 A CN 110047848A CN 201910260551 A CN201910260551 A CN 201910260551A CN 110047848 A CN110047848 A CN 110047848A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The present invention provides a kind of array substrate and preparation method thereof, the preparation method on gate insulating layer by being initially formed source-drain electrode layer, it is handled by ion doping, metal processing on source-drain electrode layer in channel region is the insulating materials of corresponding metallic compound or compound, to form source region, drain region and the channel region of same layer setting；Active layer is formed on source-drain electrode layer again.It is not related to etching technics, when solving source-drain electrode etching, active layer is etched liquid damage, to influence the electrical property of array substrate, or even leads to the problem of reliability.Meanwhile smaller channel can be formed by oxidation processes, smaller array substrate is made, to improve the performance of array substrate.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of array substrate and preparation method thereof.
Background technique
Array substrate is as the master in current liquid crystal display device and active matrix type organic light emitting diode display device
Driving element is wanted, performance is directly related to the developing direction of display device.
However the array substrate of existing back channel etch structures, it is initially formed active layer, it is rear to form source-drain electrode layer, then to source
Drain electrode layer performs etching to form source electrode, drain electrode, in source-drain electrode etching, easily causes active layer to be etched liquid damage, to influence
The electrical property of array substrate, or even lead to the problem of reliability.
Therefore, existing array substrate technology of preparing there is technical issues that active layer is etched liquid, needs to improve.
Summary of the invention
The present invention provides a kind of array substrate and preparation method thereof, and solving existing array technology of preparing, there are active layers to be carved
The technical issues of losing liquid etching.
To solve the above problems, technical solution provided by the invention is as follows:
The present invention provides a kind of array substrate comprising:
Substrate；
The grid layer being formed on the substrate；
The gate insulating layer being formed on the grid layer；
The source-drain electrode layer being formed on the gate insulating layer；
The active layer being formed on the source-drain electrode layer；
Wherein, the source-drain electrode layer includes source region, drain region and channel region, the source region, described
Drain region and channel region same layer setting, the channel region are adulterated by the source-drain electrode layer and are formed.
In array substrate provided by the invention, the material of the source-drain electrode layer is metal.
In array substrate provided by the invention, the metal material of the source region and the drain region is aluminium, institute
The material for stating channel region is aluminium oxide.
In array substrate provided by the invention, the active layer is semiconductor material.
In array substrate provided by the invention, the material of the active layer is polysilicon.
Further, the present invention also provides a kind of preparation methods of array substrate comprising:
Substrate is provided；
Grid layer is formed on the substrate；
Gate insulating layer is formed on the grid layer；
Source-drain electrode layer is formed on the gate insulating layer；
The source-drain electrode layer is handled, source region, drain region and channel region are formed；
Active layer is formed on the source-drain electrode layer；
Passivation layer is formed on the active layer.
In array substrate preparation method provided by the invention, the processing source-drain electrode layer forms source region, leakage
The step of polar region domain and channel region includes:
Source-drain electrode layer described in patterned process forms circuit region；
The circuit region is adulterated to form source region, drain region and channel region.
It is described that the circuit region is adulterated to form source region, leakage in array substrate preparation method provided by the invention
The step of polar region domain and channel region includes:
Determine doped region；
The doped region is doped, forms the channel region, and then determine the source region and the drain electrode
Region.
In array substrate preparation method provided by the invention, the step of determining doped region, includes:
Patterned photoresist layer is formed on the source-drain electrode metal layer, the patterned photoresist layer is in the source-drain electrode
Doped region is crossed on metal layer.
In array substrate preparation method provided by the invention, described the step of being doped to the doped region, includes:
By heated oxide or plasma oxidation means, oxidation processes are carried out to the metal of the doped region, it will be described
The metal of doped region is oxidized to the metal oxide of insulation.
The invention has the benefit that the present invention provides a kind of array substrate and preparation method thereof, which passes through
It is initially formed source-drain electrode layer on gate insulating layer, is handled by ion doping, at the metal on source-drain electrode layer in channel region
Reason is the insulating materials of corresponding metallic compound or compound, to form the source region of same layer setting, drain region
Domain and channel region；Active layer is formed on source-drain electrode layer again.It is not related to etching technics, when solving source-drain electrode etching, has
Active layer is etched liquid damage, to influence the electrical property of array substrate, or even leads to the problem of reliability.Meanwhile by oxidation at
Reason can form smaller channel, smaller array substrate be made, to improve the performance of array substrate.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the structural schematic diagram of existing array substrate；
Fig. 2 is the structural schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 3 is the flow chart of the preparation method of array substrate provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with specific embodiments of the present invention, to the technical side in embodiment of the present invention and/or embodiment
Case carries out clear, complete description, it is clear that, embodiment and/or embodiment disclosed below is only the present invention
A part of embodiment and/or embodiment, rather than whole embodiments and/or embodiment.Based on the implementation in the present invention
Scheme and/or embodiment, those of ordinary skill in the art are not making the front lower every other reality obtained of creative work
Scheme and/or embodiment are applied, the scope of the present invention is belonged to.
The direction term that the present invention is previously mentioned, for example, [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer],
[side] etc. is only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, and
It is non-to limit the present invention.The similar unit of structure is with being given the same reference numerals in the figure.
Fig. 1 is the structural schematic diagram of existing array substrate, as shown, existing array substrate is successively shape on substrate 1
It is obtained at grid layer 2, gate insulating layer 3, active layer 4 and source-drain electrode layer 5.During forming source-drain electrode, source need to be initially formed
Drain metal layer, then by channel etching technology, position preset in source-drain electrode metal layer is etched away, is formed as shown in the figure
Source region 51, drain region 52 and channel region 53.
However, etching liquid will cause the damage of the active layer below source-drain electrode layer, Jin Erying in the lithographic technique
The electrical property for arriving array substrate is rung, or even leads to the problem of reliability.
In order to solve the above technical problems, the present invention proposes a kind of array substrate.
In one embodiment, as shown in Fig. 2, array substrate provided by the invention includes: substrate 1, is formed in the base
Grid layer 2 on plate 1, is formed in the gate insulating layer 3 at the gate insulating layer 3 being formed on the substrate 1 and grid layer 2
On source-drain electrode layer 5 and the active layer 4 that is formed on the source-drain electrode layer 5.
Wherein, the source-drain electrode layer 5 includes source region 51, drain region 52 and channel region 53, the source area
Domain 51, the drain region 52 and the setting of 53 same layer of the channel region, the channel region 53 are mixed by the source-drain electrode layer
Miscellaneous formation.
The material of the source-drain electrode layer is metal, after being doped by the metal to predetermined drain region, makes a reservation for drain electrode
The material in region changes into the compound or compound of the metal, and the compound or compound of the metal are insulating materials.
The source-drain electrode layer 5 is defined as the source region 51, the drain region 52 and the channel region 53.
In one embodiment, the metal material of the source region 51 and the drain region 52 is aluminium, the channel
The material in region 53 is the aluminium oxide for carrying out oxygen doping formation to metallic aluminium by oxidation processes.
The active layer 5 is semiconductor material.
In one embodiment, the material of the active layer 5 is polysilicon.
The material of the gate insulating layer 3 is answering of being formed of silica, silicon nitride or be superimposed by silica with silicon nitride
Condensation material.
In conclusion array substrate provided by the invention, by being initially formed source-drain electrode layer 5, and to the material of source-drain electrode layer 5
It is doped processing and forms source region 51, drain region 52 and channel region 53, then formed on the source-drain electrode layer 5
Active layer 4, therefore will not relate to the influence in 5 forming process of source-drain electrode layer to the active layer 4.
Based on above-mentioned array substrate, the present invention also provides a kind of preparation methods of array substrate.
In one embodiment, as shown in figure 3, the step of preparation method of the array substrate includes:
S301, substrate 1 is provided.
The substrate 1 is glass substrate.
S302, grid layer 2 is formed on the substrate 1.
The material of the grid layer 2 includes one of molybdenum, aluminium, copper, titanium, chromium or a variety of.
In one embodiment, the material of the grid layer 2 is copper.
In one embodiment, described includes: to deposit on the substrate 1 the step of forming grid 2 on the substrate 1
First metallic film obtains grid layer 2 after carrying out patterned process to first metallic film using lithographic process.
S303, gate insulating layer 3 is formed on the grid layer 2.
The material of the gate insulating layer 3 be silica, silicon nitride or silica and silicon nitride be superimposed to be formed it is compound
Material.
In one embodiment, described includes: using chemistry the step of forming gate insulating layer 3 on the grid layer 2
Vapor deposition method, deposition obtains gate insulating layer 3 on the grid layer 2.
S304, source-drain electrode layer 5 is formed on the gate insulating layer 3.
The material of the source-drain electrode layer 5 is metal.
In one embodiment, the material of the source-drain electrode layer 5 is metallic aluminium.
In one embodiment, described to include: the step of forming source-drain electrode layer 5 on the gate insulating layer 3
The second metallic film is deposited on gate insulating layer 3.
S305, the processing source-drain electrode layer 5, form source region 51, drain region 52 and channel region 53；
The source-drain electrode layer 5 include source region 51, drain region 52 and channel region 53, the source region 51,
The drain region 52 and the setting of 53 same layer of the channel region, the channel region 53 adulterate shape by the source-drain electrode layer
At.
The material of the source region 51 and the drain region 52 is metal, and the material of the channel region 53 is described
The metallic compound or compound of metal-doped formation, and the metallic compound or compound are insulating materials.
In one embodiment, the metal material of the source region 51 and the drain region 52 is aluminium, the channel
The material in region 53 is the aluminium oxide for carrying out oxygen doping formation to metallic aluminium by oxidation processes.
In one embodiment, the processing source-drain electrode layer 5, forms source region 51, drain region 52 and ditch
The step of road region 53 includes:
Source-drain electrode layer 5 described in patterned process forms circuit region；
The circuit region is adulterated to form source region 51, drain region 52 and channel region 53.
In one embodiment, described that the circuit region is adulterated to form source region 51, drain region 52 and channel
The step of region 53 includes:
Determine doped region；
The doped region is doped, forms the channel region 53, and then determines the source region 51 and described
Drain region 52.
In one embodiment, the step of determining doped region includes:
Patterned photoresist layer is formed on the source-drain electrode metal layer, the patterned photoresist layer is in the source-drain electrode
Doped region is crossed on metal layer.
In one embodiment, described the step of being doped to the doped region, includes:
By means such as heated oxide or plasma dopings, Oxidation Doping processing is carried out to the metal of the doped region,
The metal of the doped region is handled into the corresponding metallic compound or compound for phase, to form insulator.
S306, active layer 4 is formed on the source-drain electrode layer 5.
The active layer 5 is semiconductor material.
In one embodiment, the material of the active layer 5 is polysilicon.
In one embodiment, described to include: the step of forming active layer 4 on the source-drain electrode layer 5
The depositing polysilicon material on the source-drain electrode layer 5 forms the active layer 4.
S307, passivation layer is formed on the active layer 4.
Further annotation explanation is done to array substrate and preparation method thereof of the invention now in conjunction with specific embodiment.
Substrate 1 is provided, successively the depositing layers 2 on the substrate 1, deposit on the substrate 1 and the grid layer 2
Gate insulating layer 3, the sedimentary origin drain electrode layer 5 on the gate insulating layer 3, the source-drain electrode layer 5 are metallic aluminum；In the source
Patterned photoresist layer is formed on drain electrode layer 5, the patterned photoresist layer crosses doped region on the source-drain electrode metal layer；
By means such as heated oxide or plasma oxidations, Oxidation Doping processing is carried out to the metallic aluminium of the doped region, it will be described
The metallic aluminium of doped region is oxidized to the insulator of metallic aluminium, to form the channel region 53, and then determines the source area
Domain 51 and the drain region 52；The depositing polysilicon material on the source-drain electrode layer 5 forms the active layer 4；Have described
Passivation layer is formed in active layer 4.
According to above-described embodiment: the present invention provides a kind of array substrate and preparation method thereof, which passes through
It is initially formed source-drain electrode layer on gate insulating layer, is handled by ion doping, at the metal on source-drain electrode layer in channel region
Reason is the insulating materials of corresponding metallic compound or compound, to form the source region of same layer setting, drain region
Domain and channel region；Active layer is formed on source-drain electrode layer again.It is not related to etching technics, when solving source-drain electrode etching, has
Active layer is etched liquid damage, to influence the electrical property of array substrate, or even leads to the problem of reliability.Meanwhile by oxidation at
Reason can form smaller channel, smaller array substrate be made, to improve the performance of array substrate.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
1. a kind of array substrate, which is characterized in that including
Substrate；
The grid layer being formed on the substrate；
The gate insulating layer being formed on the grid layer；
The source-drain electrode layer being formed on the gate insulating layer；
The active layer being formed on the source-drain electrode layer；
Wherein, the source-drain electrode layer includes source region, drain region and channel region, the source region, the drain electrode
Region and channel region same layer setting, the channel region are adulterated by the source-drain electrode layer and are formed.
2. array substrate as described in claim 1, which is characterized in that the material of the source-drain electrode layer is metal.
3. array substrate as claimed in claim 2, which is characterized in that the metal material of the source region and the drain region
Material is aluminium, and the material of the channel region is aluminium oxide.
4. array substrate as described in claim 1, which is characterized in that the active layer is semiconductor material.
5. array substrate as claimed in claim 4, which is characterized in that the material of the active layer is polysilicon.
6. a kind of preparation method of array substrate characterized by comprising
Substrate is provided；
Grid layer is formed on the substrate；
Gate insulating layer is formed on the grid layer；
Source-drain electrode layer is formed on the gate insulating layer；
The source-drain electrode layer is handled, source region, drain region and channel region are formed；
Active layer is formed on the source-drain electrode layer；
Passivation layer is formed on the active layer.
7. the preparation method of array substrate as claimed in claim 6, which is characterized in that the processing source-drain electrode layer, shape
Include: at the step of source region, drain region and channel region
Source-drain electrode layer described in patterned process forms circuit region；
The circuit region is adulterated to form source region, drain region and channel region.
8. the preparation method of array substrate as claimed in claim 7, which is characterized in that described to adulterate to be formed to the circuit region
The step of source region, drain region and channel region includes:
Determine doped region；
The doped region is doped, forms the channel region, and then determine the source region and the drain region.
9. the preparation method of array substrate as claimed in claim 8, which is characterized in that the step of determining doped region wraps
It includes:
Patterned photoresist layer is formed on the source-drain electrode metal layer, the patterned photoresist layer is in the source-drain electrode metal
Doped region is crossed on layer.
10. the preparation method of array substrate as claimed in claim 8, which is characterized in that described to mix the doped region
Miscellaneous step includes:
By heated oxide or plasma oxidation means, oxidation processes are carried out to the metal of the doped region, by the doping
The metal in area is oxidized to the metal oxide of insulation.
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| CN201910260551.4A CN110047848B (en) | 2019-04-02 | 2019-04-02 | Array substrate and preparation method thereof |
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| CN201910260551.4A CN110047848B (en) | 2019-04-02 | 2019-04-02 | Array substrate and preparation method thereof |
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| CN110047848A true CN110047848A (en) | 2019-07-23 |
| CN110047848B CN110047848B (en) | 2021-07-06 |
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| CN107425075A (en) * | 2017-05-17 | 2017-12-01 | 厦门天马微电子有限公司 | Film transistor device and its manufacture method, array base palte and display device |
| US20180062105A1 (en) * | 2016-09-01 | 2018-03-01 | Innolux Corporation | Display device |
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2019
- 2019-04-02 CN CN201910260551.4A patent/CN110047848B/en active Active
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| US20140183453A1 (en) * | 2012-12-27 | 2014-07-03 | Samsung Electronics Co., Ltd. | Field effect transistor having double transition metal dichalcogenide channels |
| CN103199114A (en) * | 2013-03-25 | 2013-07-10 | 合肥京东方光电科技有限公司 | Thin film transistor and manufacturing method thereof and array substrate and display device |
| CN104701264A (en) * | 2015-03-25 | 2015-06-10 | 京东方科技集团股份有限公司 | Organic light emitting diode display panel and manufacturing method thereof and display device |
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