JPH0394471A - Semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit a kink effect, or to increase breakdown strength between a source and a drain by connecting a source region in a semiconductor layer to a channel region in high concentration on the source side and connecting a drain electrode to a drain region. CONSTITUTION:A film as a conductor layer such as a polycrystalline silicon film is formed in specified film thickness and patterned on the whole surface on an inter-layer insulating film 9 so as to fill a first contact hole 25 and a second contact hole 26. A first source region 23, a second channel region 22 and a source electrode 27 joined with an insulator layer 2 are shaped through the first contact hole 25, and a drain electrode 28 joined with a drain electrode 24 is formed. The second channel region 22 is shaped for acquiring the ohmic electrical junction of the source electrode 27 and a first channel region 21. Accordingly, a kink effect and the lowering of breakdown strength between a source and a drain are avoided.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides an M O formed in a semiconductor layer on an insulating substrate.
8 rMetal Ocide 8 emiaonduc
tor) type field effect transistor c, below, “SO-M
(abbreviated as O8FE'l'J), in particular, the source
This invention relates to improving the breakdown voltage between drains.

[Conventional technology]

FIG. 8 is a sectional view showing a conventional SOI-MOSFE'['. An insulator layer (2) is formed on a silicon substrate (1), and a silicon layer (3) is formed on the insulator layer (2). Type impurity concentration (e.g. 1016-1017 atoms
/ am ) V head M (6) is formed with a high n-type impurity concentration (e.g. 10 1
A source head (7) and a drain region (3) having 9-10'' atoms, /am3) are arranged in contact with one side and the other side of the channel/l' head area (6), respectively.

Channel/L/@ * (6) A gate dielectric thin film (hereinafter referred to as gate insulating film) (4) is formed on the
, a gate electrode (5) is formed on the gate insulating film (4). The silicon layer (3) and the gate electrode (5) are covered with an interlayer insulating film (9).Interlayer insulating film (9)
Contact holes ILt (10a) and (lob) are opened, and each contact hole yv (xoa)
, (xob), in this case, a source electrode (6) and a drain electrode (6) are formed on the SOI-MO8FE'I'K constructed as above.
When applying a positive voltage to the gate electrode (5),
N conductivity type carriers (Ml particles) are attracted to the upper layer part of the p type channel region (6), and the upper m part thereof is the source region (
7) 0 which is inverted to the same n conductivity type as the hexagram and the drain fiN M (8). Therefore, the source [ * (7)
Current can flow between the drain region (8) and the drain region (8).

Furthermore, since the concentration of n-type carriers attracted to the upper layer of the channel/L/@ region (6) changes depending on the gate voltage, the amount of current flowing through the channel lv region: lIE (6) can be controlled by the gate voltage. I can do it. This is MOS
This is the operating principle of FET.

[llKM that the invention attempts to solve]

The conventional SOA MOSFET is constructed as described above, and when the silicon W (3) is relatively thick (for example, about 5,000 mm thick), the SOA MOSFET is operated by applying a gate voltage.
When the MOSFET is put into operation, the drain region (3
) into the channel region* (6) may reach the source region (7). When the depletion layer reaches the source region [(7), the electrical barrier between the source region * (7) and the channel @ * (6) decreases, causing a relatively large electrical barrier that cannot be controlled by the enclosed gate electrode (5). The potency ρ of the deep head relation increases, which causes a phenomenon in which the channel current rapidly increases, the so-called bunches phenomenon. This punch-through phenomenon lowers the withstand voltage between the source and drain.

Further, when the voltage applied between the source and the drain is high, carriers are accelerated within the channel N @ M (6) at high speed. The carriers accelerated in the channel /l/head [(6) generate electron and hole bears by impact ionization near the drain region (8). This generated electron is n
It flows into the + type drain region (3). However, holes accumulate in the channel region (6) and increase the potential, increasing the channel p current and causing an undesirable kink effect on the electrical characteristics representing the relationship between drain voltage and drain current. let

This King effect is, for example, an engineering EEE Electr
onDevice Letter. Vol. 9, N
o. 2, pp. 97-99, 198B.

On the other hand, very thin (e.g. 500A N1500A
Thin film SOA MOS with V recon layer (3)
The FET is an ordinary S with a thick silicon layer (3)
It has superior characteristics compared to OI-MO8FET.

For example, the thin channel/L/@ region (0) is entirely depleted by applying a voltage to the gate electrode (5), and the potential is also controlled by the gate electrode (5), as described above. The bunch-through phenomenon and kink effect disappear.

Furthermore, the short channel p effect, in which the gate threshold voltage becomes abnormally low when the gate length is short, is also reduced.

However, when the entire channel iv@K(6) is completely depleted, the voltage inside the channel 1v@K(6) becomes higher than that in the normal MO81i'ETK&.

Sitting down, Sauce Fan Rin (7) and Channel Nore 11X Rin (6)? In addition to lowering the electrical barrier between the channels, the holes generated by the aforementioned impact ionization are transferred to the channel region M. (6)
If it is temporarily accumulated in the channel A/IP area (6)
The potential p in the channel increases further, and electrons are rapidly injected from the source slope [(7) into the channel /L/[[(6). In other words, the thin film SOI-MOSFET K > IT also has the problem that the withstand voltage between source and train tends to be low.

In view of the above problems, the purpose of the present invention is to
It is possible to provide an 80I-M08FET with improved breakdown voltage between drains.

[Means to solve the problem]

A semiconductor device according to the present invention includes an insulating base and a semiconductor layer provided on the insulating base, and a gate 1! formed on the semiconductor layer with a gate dielectric thin film interposed therebetween. a channel node of the 138th conductivity type formed in the semiconductor node d; and a source of the second conductivity type formed on one side of the gate electrode and in contact with at least one side of the channel region. a drain region of the second conductivity type formed in contact with at least the other side of the channel region on the other side of the gate electrode; and at least the source region of the source region and the drain region. The channel head of the channel/I/@ region of the high concentration impurity layer formed under and in contact with the channel/I/@ region is connected to the source region and the channel head of the high concentration impurity layer. and a drain electrode connected to the drain region.

[Effect]

The source electrode according to the present invention has a high concentration channel/l in the source region and the semiconductor layer formed in contact therewith.
/m region, this source electrode also serves as a substrate electrode. Therefore, surplus carriers generated by impact ionization in the semiconductor layer can be easily extracted to the source electrode. This has the effect of avoiding the King effect and deterioration of the source-drain breakdown voltage.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In other cases, the explanation of parts that overlap with the explanation of the prior art will be omitted as appropriate. FIG. 1 is a sectional view showing the structure of SOA MOSFE 'I' according to the first embodiment of the present invention.

In the figure, (1), (2), (4), (
5) and (9) are the same as the conventional one. (d) is the first silicon layer on the insulator layer (2), and the gate 'k is placed on the upper side of this first silicon, ll1gJ.
A first source head *W, a first drain region (c) having a high n-type impurity concentration formed on both sides of the quadrupole (5), and a drain region of these l-th source region *W, aX ( c) a second channel /L/rai*@@ having a high p-type impurity concentration formed on the outer side divided into the lower part of the
These first source nod area @, first drain @ area (ha)
A first channel hole with a low p-type impurity concentration is formed in the inner center of the second channel lv head*@h.
It consists of the area Qυ. (D) is an insulator (2) that exposes a part of the interlayer insulating film (9) on the source@region g3 side.
) A contact hole is made in the straw 1 through a part of the main surface of the interlayer insulating film (9), and a part of the main surface of the first drain region (material) of the interlayer insulating film (9) is exposed in (e). The first hole was drilled like this? This is the contact hole. @ is the head area of the l-th source Vtn and the second channel lv through the first contact hole.
In this case, b1 is a source electrode that serves as one of the conductors and is also connected to the insulator layer [2]. In this case, it has both the functions of the l-th source electrode @ and the substrate electrode. @
is connected to the first drain head M (
This is the drain electrode that becomes the other conductor connected to the other conductor.

The SOA MOSFET thus constructed is formed as follows. This will be explained based on FIG. 2.

First, an insulating layer (2) is formed to a predetermined thickness on the main surface of the silicon substrate (1), and then a layer (d) that will become the first silicon layer is formed thereon. A p-type impurity, in this case boron, is ion-implanted 61) into the layer (self) that will become the silicon layer 1. In this way, an @ region to become the first channel region is formed. This area is, for example, 10
It is formed at an impurity concentration of 16 to 10 17 atcms/am (FIG. 2(a)).

Next, silicon ?
After forming an oxide film on the entire surface, resist ■ is applied on top of this.
form. The b1 resin (b) is patterned using photo-ring-off technology, and then, using this as a mask, the silicon oxide film is etched and selectively removed. After this, ptM is applied to NI (d), which becomes the first silicon layer.
An impurity, in this case boron, is ion-implanted to form a p-type impurity region (7) (FIG. 2(b)).

Next, after removing the resist hooks by an ashing method or the like,
A silicon substrate (1) is heat-treated at a predetermined temperature.

Like this, p-type impurity @w:. The impurity (d) is activated, and its boundary surface penetrates inward from the end surface of the silicon oxide film (d), forming an expansion layer. This diffusion layer is connected to the second channel head V. ．． The impurity concentration that would be @ is
For example, it is formed at 10'9 to 1020 atoms/cm3 (Fig. 2(C)).

Next, using the silicon oxide film ■ as a mask, the layer ■■■ which will become the first silicon layer is selectively removed by reactive ion etching (hereinafter referred to as R etching) having anisotropic characteristics. (See Figure 2 (d)) Next, after removing the silicon oxide film that served as a mask by etching, a silicon oxide film is formed on the entire surface to cover the NI@, which will become the first silicon layer. Then, for example, a polycrystalline silicon film is formed on the entire surface thereof. Thereafter, the polycrystalline silicon film is patterned using a photo-ring-fiber technique, and then, using this as a mask, the underlying silicon oxide film is selectively etched away using a R process or the like. As a result, a gate insulating film (4) is formed at the inner center of the layer (self) that will become the first silicon layer, and a gate electrode (5) is formed thereon (FIG. 2(e)).

Next, after ion-implanting (b) an n-type impurity, in this case arsenic, above the silicon substrate (1), this is activated to form an n-type diffusion layer. 1 source @ft. eI3, which becomes the first drain region (goods), and the impurity concentration is, for example, 10 to 10 atoms.
s/cm3. Here, the l-th source region R
j 1st drain@ft. By forming (c), the first channel region and the second channel region are defined, and the first silicon layer (e) is formed ( Figure 2(f)).

Next, a gate electrode (5), a silicon layer (1
), an interlayer insulating film (9) is formed to a predetermined thickness over the entire surface of the silicon substrate (1). Subsequently, this is patterned by photolithography to form a first contact hole (d) and a second contact hole (e).

Here, the first contact hole (self) is connected to the source of 'Al@H. Insulator so that the outer end of the wire, the side of the second channel/L/@area, is exposed, i! The contact hole (E) of @2 is opened so that a part of the main surface of the first drain region (C) is exposed. (Figure 2 (g)).

Next, a film to be a conductive layer, in this case a polycrystalline silicon film, is deposited to a predetermined thickness over the entire surface of the interlayer insulating film (9) so as to fill the first contact hole @ and the second contact hole (e). to form. Next, this is patterned using photolithography technology. In addition to this, the first contact hole (d)
A first source head, a second channel/l' region, and a source electrode connected to the insulator layer (2) are formed through the drain electrode. Electrodes are formed.

The second channel yv@fli. @ is provided to obtain an ohmic electrical connection between the source electrode @ and the first channel/I/region QD (FIG. 2(h)).

In this way, the S○ MOSFET is completed. Since the operation of this S○ MOSFET is basically the same as that shown in the prior art, its explanation will be omitted. In the operation of applying this structure, re-1 channel/l
The holes generated by impact ionization in the /L/region 0 are immediately transferred to the second channel /L/M. This prevents the king effect that tends to occur when the first silicon layer (e) is pulled out from @ to the source electrode @, and the decrease in source-drain breakdown voltage that tends to occur when the first silicon layer (e) is thin.

FIG. 3 shows a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the structure of ET. In this case, the fourth channel /L/ feed*(6) (6) corresponds to the second channel yv @ area E @ of the one shown in FIG. The third channel /I/@H. It has a structure having (c). child? The second silicon layer of the material is thin, e.g.
In the case of a person, the first source @Vc@ in the case of Figure 1
, the l-th drain region ■■■ is connected to the first silicon layer (1
), the third channel region (6) with a high impurity concentration is connected to the second source region vj. (Foundation), Second Drain Territory M. By forming substantially the entire lower part of the first silicon ring, a channel /L/liquid of the opposite conductivity type can be extended to the end of the second silicon Nj ring.

FIG. 4 shows the SOA MOSFET of the third embodiment of the present invention.
FIG. This includes a fourth source region (55) and a fourth drain region (55), which are bonded to a third source region (53) and a third drain region (54), respectively, on the third silicon layer ω. having a region (56);
A side wall yv (Ffl) (57) is formed on the gate electrode (5) and the side wall on the drain side of the third silicon layer diagram.
It has a structure that has

This product is formed according to the process shown in Figure WJ5.

First, an insulator layer (2) is formed to a predetermined thickness on the main surface of a silicon substrate (1), and then a layer (61) that will become a third silicon layer is formed thereon. A p-type impurity, in this case, boron, is ion-implanted into the silicon layer (6l) (not shown), thereby forming a region to become the fifth channel region (51). This region is formed to have an impurity concentration of, for example, 10 to 10 atoms/cm3.Next, # (61), which will become the M3 silicon layer, is patterned by photolithography technology. Layer (61) that becomes the silicon layer of
A silicon oxide film, a polycrystalline silicon film, and a silicon nitride film are formed thereon to predetermined thicknesses, and a resist is further formed thereon.

A patterned resist (63) is formed by photolithography technology, and then this resist pattern (
Using 63) as a mask, the underlying silicon nitride film, polycrystalline silicon film, and silicon oxide film are sequentially selectively etched away by, for example, RIE. ) with a gate electrode (
5), the gate insulating film (4) is formed (Fig. 5(a)
) Next, Dp-type impurities, in this case, poron, and n-type impurities, in this case, arsenic, are sequentially ion-implanted (not shown) under predetermined conditions from above the silicon substrate (1). At this time, the n-type impurity region is formed to be shallow and the p-type impurity region is deep. After this, the resist (
63) is removed by an ashing method etc., and the silicon substrate (
1) is heat-treated at a predetermined temperature to form p-type and n-type diffusion layers, respectively. This n-type diffusion layer becomes the third source @Vc (
53), which will become the third drain region (54), is formed at an impurity concentration of 10 to 10 atoms/am3. Below these, a sixth channel head* (52) is formed having a high p-type impurity concentration, for example 10 to 1020 atoms/cm3. Also, the third source region M. (53), third drain@region (
54), 6th channel/L/@relative (52) A 5th channel/1/space area (51) is formed in the head area sandwiched by (52). 3 silicon layer■
(Figure 5(b)).

Next, a b1 silicon oxide film is formed to a predetermined thickness by CVD or the like so as to cover the gate electrode Wi(5) and the exposed portion of the third silicon layer. After this, R with anisotropic properties
In Step E, the entire silicon oxide film is etched.

When the main surfaces of the silicon nitride film (62) and the third silicon oxide film are exposed by etching, the gate electrode (5) and the gate insulating film (4) are removed due to the difference in thickness of the silicon oxide film. ) and the side wall of the third silicon layer ω are formed with sidewalls /l/(5n) (57) (FIG. 5(C)).

Next, the silicon substrate (1) is selectively treated with epitaxy. As a result, the epitaxial layer is selectively elongated on the main surfaces of the third source region (53) and the third drain region (54) where silicon is exposed, and the fourth source region (53) and the third drain region (54) are selectively elongated. (55) #4th drain @ area (56
) are formed 0 these heads H. (55) (5a) is
If the impurity concentration is, for example, 10'' to 10'' atoms
/cm3. After this, the silicon nitride film (62) that served as an oxidation-resistant film on the main surface of the gate electrode (5) during the selective eviction process is removed (Fig. ag5 (d).
)).

Next, a layer gap m (9) is formed with a predetermined thickness so as to cover the gate electrode (5) and the third silicon layer, and this is selectively removed by photolithography. and a third contact hole (58) and a fourth contact hole (59).
form. This third contact hole (58) is connected to the fourth contact hole (58).
The outer end of the source @relative (55), the third source head w.
(s3) O m surface part, yJc6 (D f Yang * yv head * (52) (D (II1 surface part} and a part of the main surface of the insulator layer (2)) are opened to expose the casing. , the fourth contact hole (59) is opened so that a part of the main surface of the fourth drain @H. (5B) is exposed.After this, the third contact hole (5s), Fourth
An interlayer insulating film (
9) A film to be a conductive layer, for example, a polycrystalline silicon film, is formed on a predetermined film, and this is patterned and selectively removed to form a conductive layer, in this case a source electrode,
A drain electrode is formed. This source electrode (b) is connected to the fourth source region jtc (55), the third source head M. (53), the sixth channel lv head* (52) and the insulator layer (2)
, the drain electrode @ is connected to the fourth drain head R (5e) (FIG. 5(e)).

By using the SOA MO8FET with such a structure, it becomes easier to extract excess carriers from the b1 Saone electrode (b), where channels are easily formed, and the b1 third silicon layer (b), which is thicker. In this case, it is easy to suppress the kink effect, which occurs when the material is thin, or it is possible to improve the withstand voltage between the source and drain, which tends to occur when the material is thin.

FIG. 6 shows the SOI-MOSFET of the fourth embodiment of the present invention.
FIG. This is the second channel fi7 head M which is applied to the first silicon layer shown in FIG.
．． The fourth silicon layer (60) is formed under the first source region (c) but not under the first drain region (c).

゛Also, FIG. 1 shows the SOEMO of the fifth embodiment of the present invention
FIG. 3 is a cross-sectional view showing the structure of SLi'ET. In this case, the fourth channel/L/@ region (6) in the second silicon layer shown in FIG. 3 is formed below the second source@ region, but the second drain@ It has a structure in which the fifth silicon m (to) is not formed under region (1).

The structures shown in FIGS. 6 and 7 also have the same effect as described above.

However, in the description of the above embodiment, >W, silicon layer (1),
Is it an n-channel type where the channels formed within (g), (d), (eo), and (yo) are n-channels?
i! Although OSFE'I' has been described, it is not limited to this, and each lead'li1! By changing the type, a Dp channel/L/type MOSFET can be formed, and in this case, the same effect as described above can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, the source electrode is located in the semiconductor layer and the source region is located on the source side. aJ concentration channel/
Since the drain electrode is connected to the L/@ region and the drain electrode is connected to the drain@ region, it is possible to control the shape of the substrate electrode without increasing the device area, when the semiconductor layer is thick. The King effect can be suppressed, and when the semiconductor layer is thin, the withstand voltage between the source and drain can be improved, and a highly reliable semiconductor device can be obtained.

[Brief explanation of drawings]

FIG. 1 shows the S○ MOSFET of the first embodiment of the present invention.
2(a) to (h) are sectional views showing the manufacturing process of the one shown in FIG. 1, and FIG. A sectional view showing the structure, FIG. 4 is a SO-MOS of the third embodiment of the present invention.
5(a) to 5(e) are cross-sectional views showing the manufacturing process of the FET shown in FIG. 4, and FIG. A sectional view showing the structure, FIG. 7 is an SOI-
A cross-sectional view showing the structure of MO8FET, Figure 8 is a conventional SO
FIG. 3 is a cross-sectional view showing the structure of the A MOSFET. In the figure, (2) is the insulator layer, (4) is the gate insulating layer, (5) is the goo} N pole, the wire is the first silicon layer, and c2υ
is the first channel region, @ is the second channel lv top region, g3 is the first source region, ←Φ is the first drain (@
area, @ is the source electrode, @ is the drain electrode, (T) is the second
silicon layer, 0 is the third channel region, (6) is the fourth channel region, the target is the second source region, m is the second drain f8\ region, ■ is the third silicon layer, ( 51
) t′i fifth channel/I/head area, (52) is the sixth channel/I/head area, (53) is the third source area, (5
4) is the third drain@region, (55) is the fourth source region, (56) is the fourth drain@region, (60) is the fourth
('K)) f'i is the fifth silicon layer. The same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] It has an insulating base, a semiconductor layer provided on the insulating base, a gate electrode formed on the semiconductor layer via a gate dielectric thin film, and a first conductivity type formed on the semiconductor layer. a channel region and one side of the gate electrode;
a second conductivity type source region formed in contact with at least one side of the channel; and a second conductivity type source region formed on the other side of the gate electrode.
a drain region of a second conductivity type formed in contact with at least the other side of the channel; and a channel of the first conductivity type formed under and in contact with at least the source region of the source region and the drain region. A semiconductor device comprising: a channel region of a highly doped impurity layer; a source electrode connected to the source region; a source electrode connected to the channel region of the highly doped impurity layer; and a drain electrode connected to the drain region.