KR20030044340A - Method of forming a transistor in a semiconductor device - Google Patents
Method of forming a transistor in a semiconductor device Download PDFInfo
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- KR20030044340A KR20030044340A KR1020010075056A KR20010075056A KR20030044340A KR 20030044340 A KR20030044340 A KR 20030044340A KR 1020010075056 A KR1020010075056 A KR 1020010075056A KR 20010075056 A KR20010075056 A KR 20010075056A KR 20030044340 A KR20030044340 A KR 20030044340A
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- South Korea
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- spacer
- gate oxide
- impurity region
- polysilicon layer
- concentration impurity
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims description 8
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000036039 immunity Effects 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
Description
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 저농도불순물 영역에 게이트 전극에 의한 전위가 전달될 수 있도록 게이트 전극을 하부에서 소정 두께 잔류되도록 캐패시터형으로 형성하여 트랜지스터를 제조함으로써 트랜지스터가 턴온될 때 저농도 불순물 영역에 전자가 축적되어 저농도 불순물 영역의 저항을 낮추어 외부 저항을 효과적으로 감소시킬 수 있는 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device. In particular, the transistor can be turned on by forming a capacitor by forming the gate electrode in a capacitor type such that the gate electrode remains at a predetermined thickness so that a potential of the gate electrode can be transferred to a low concentration impurity region. The present invention relates to a method of manufacturing a transistor of a semiconductor device capable of effectively reducing external resistance by accumulating electrons in a low concentration impurity region to thereby lower the resistance of the low concentration impurity region.
반도체 소자의 집적화가 가속화 될 수록 채널 길이는 점점 짧아지게 된다. 따라서, 저농도 불순물 영역 및 고농도 불순물 영역을 갖는 트랜지스터의 속도를 좌우하는 전류 특성이 채널 저항보다는 외부(external) 저항의 의존도가 커지고 있다. 외부 저항은 게이트 오버랩 지역의 축적 저항(accumulation resistance), 저농도 불순물 영역의 확산 저항(spreading resistance), 소오스 및 드레인 영역의 분로 저항(shunt resistance), 콘택 저항으로 구성되는데, 이중에서 확산 저항의 저항 성분이 가장 커 전류 성능에 큰 영향을 미친다.As the integration of semiconductor devices is accelerated, the channel length becomes shorter. Therefore, the current characteristic that influences the speed of the transistor having the low concentration impurity region and the high concentration impurity region is more dependent on the external resistance than the channel resistance. The external resistor consists of accumulation resistance in the gate overlap region, spreading resistance in the low concentration impurity region, shunt resistance in the source and drain regions, and contact resistance. This is the largest and has a big impact on current performance.
이러한 확산 저항을 낮추기 위한 방법으로 저농도 불순물 영역에 주입되는 불순물의 농도를 짙게하여 이온 주입하는 방법이 널리 쓰이고 있다. 그러나, 이 방법은 숏 채널 이펙트(short channel effect)의 악화, 기생 캐패시턴스의 증가, 핫 캐리어 이뮤니티(hot carrier immunity)의 저하등의 부작용을 유발한다.As a method for lowering the diffusion resistance, a method of ion implantation by increasing the concentration of impurities injected into the low concentration impurity region is widely used. However, this method causes side effects such as deterioration of short channel effects, increase of parasitic capacitance, and decrease of hot carrier immunity.
본 발명의 목적은 외부 저항을 효과적으로 감소시킬 수 있는 반도체 소자의트랜지스터 제조 방법을 제공하는데 있다.An object of the present invention is to provide a transistor manufacturing method of a semiconductor device that can effectively reduce the external resistance.
본 발명의 다른 목적은 저농도 불순물 영역에 주입되는 불순물의 농도를 변화시키지 않으면서도 확산 저항을 감소시킬 수 있는 반도체 소자의 트랜지스터 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a method for fabricating a transistor of a semiconductor device capable of reducing diffusion resistance without changing the concentration of impurities injected into the low concentration impurity region.
본 발명에서는 저농도 불순물 영역에 게이트 전극에 의한 전위가 전달될 수 있도록 게이트 전극을 하부에서 소정 두께 잔류되도록 캐패시터형으로 형성하여 트랜지스터를 제조함으로써 트랜지스터가 턴온될 때 저농도 불순물 영역에 전자가 축적되어 저농도 불순물 영역의 저항을 낮추어 외부 저항을 효과적으로 감소시킨다.According to the present invention, a transistor is manufactured by forming a gate electrode in a capacitor type so that a predetermined thickness remains at a lower portion so that a potential of the gate electrode can be transferred to a low concentration impurity region. Lowering the resistance of the area effectively reduces external resistance.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown in order to explain a transistor manufacturing method of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판12 : 게이트 산화막11: semiconductor substrate 12: gate oxide film
13 : 폴리실리콘막14 : 저농도 불순물 영역13: polysilicon film 14: low concentration impurity region
15 : 절연막15A : 제 1 스페이서15 insulating film 15A first spacer
16A : 제 2 스페이서17 : 고농도 불순물 영역16A: Second spacer 17: High concentration impurity region
본 발명에 따른 반도체 소자의 트랜지스터 제조 방법은 반도체 기판 상부에 게이트 산화막 및 폴리실리콘막을 순차적으로 형성하는 단계와, 상기 폴리실리콘막의 소정 영역을 상기 게이트 산화막 상부에서 소정 두께 잔류하도록 식각하는 단계와, 저농도 불순물 이온 주입 공정을 실시하여 상기 반도체 기판상의 소정 영역에 저농도 불순물 영역을 형성하는 단계와, 상기 폴리실리콘막 측벽에 제 1 스페이서를 형성한 후 상기 폴리실리콘막 및 제 1 스페이서를 마스크로 상기 잔류된 폴리실리콘막 및 게이트 산화막을 식각하여 게이트 전극을 형성하는 단계와, 상기 제 1 스페이서 하부에 상기 잔류된 폴리실리콘막 및 게이트 산화막 측벽에 제 2 스페이서를 형성하는 단계와, 고농도 불순물 이온 주입 공정을 실시하여 상기 반도체 기판상의 소정 영역에 고농도 불순물 영역을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.In the method of manufacturing a transistor of a semiconductor device according to the present invention, the steps of sequentially forming a gate oxide film and a polysilicon film on a semiconductor substrate, etching a predetermined region of the polysilicon film so as to remain a predetermined thickness above the gate oxide film, low concentration Performing an impurity ion implantation process to form a low concentration impurity region in a predetermined region on the semiconductor substrate, forming a first spacer on a sidewall of the polysilicon layer, and then using the polysilicon layer and the first spacer as a mask Etching the polysilicon film and the gate oxide film to form a gate electrode, forming a second spacer on the sidewalls of the remaining polysilicon film and the gate oxide film under the first spacer, and performing a high concentration impurity ion implantation process To a predetermined region on the semiconductor substrate. It characterized in that made in a step of forming a concentration impurity region.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(c)는 본 발명에 따른 반도체 소자의 트랜지스터의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown for explaining a method of manufacturing a transistor of a semiconductor device according to the present invention.
도 1(a)를 참조하면, 반도체 기판(11) 상부에 게이트 산화막(12)을 형성한 후 그 상부에 폴리실리콘막(13)을 형성한다. 게이트 마스크를 이용한 리소그라피 공정 및 식각 공정으로 폴리실리콘막(13)을 식각하되, 폴리실리콘막(13)의 소정 영역이 약 100∼150Å의 두께로 잔류하도록 식각하여 게이트 전극을 패터닝한다. 저농도 불순물 이온 주입 공정을 실시하여 반도체 기판(11)상의 소정 영역에 저농도 불순물 영역(14)을 형성한다. 그리고, 전체 구조 상부에 절연막(15)을 형성한다. 절연막(15)으로는 산화막 또는 질화막을 사용한다.Referring to FIG. 1A, a gate oxide layer 12 is formed on a semiconductor substrate 11, and then a polysilicon layer 13 is formed on the gate oxide layer 12. The polysilicon film 13 is etched by a lithography process and an etching process using a gate mask, and the gate electrode is patterned by etching so that a predetermined region of the polysilicon film 13 remains at a thickness of about 100 to 150 microns. A low concentration impurity ion implantation process is performed to form a low concentration impurity region 14 in a predetermined region on the semiconductor substrate 11. Then, the insulating film 15 is formed over the entire structure. As the insulating film 15, an oxide film or a nitride film is used.
도 1(b)를 참조하면, 제 1 절연막(15)을 식각하여 식각 공정을 게이트 전극 측벽에 제 1 스페이서(15A)를 형성한다. 게이트 전극 및 그 측벽에 형성된 제 1 스페이서(15A)를 마스크로 식각 공정을 실시하여 약 100∼150Å의 두께로 잔류하는 폴리실리콘막(13) 및 게이트 산화막(12)을 제거하여 반도체 기판(11)을 노출시킨다.Referring to FIG. 1B, the first insulating layer 15 is etched to form the first spacer 15A on the sidewall of the gate electrode. The semiconductor substrate 11 is formed by etching the gate electrode and the first spacers 15A formed on the sidewalls thereof using a mask to remove the polysilicon film 13 and the gate oxide film 12 remaining at a thickness of about 100 to 150 Å. Expose
도 1(c)를 참조하면, 전체 구조 상부에 질화막을 형성한 후 전면 식각 공정을 실시하여 제 1 스페이서(15) 측면의 소정 영역에 제 2 스페이서(16A)을 형성한다. 제 2 스페이서(16A)는 후속 셀리사이드 공정으로 실리사이드막을 형성할 때 실리사이드막과 노출되는 폴리실리콘막(13)의 접촉을 방지하기 위해 형성하는 것이다. 고농도 불순물 이온 주입 공정을 실시하여 저농도 불순물 영역(14)와 중첩되는 고농도 불순물 영역(17)을 형성한다.Referring to FIG. 1C, after forming a nitride film over the entire structure, a front surface etching process is performed to form a second spacer 16A on a predetermined region of the side surface of the first spacer 15. The second spacer 16A is formed to prevent contact between the silicide film and the polysilicon film 13 that is exposed when the silicide film is formed by a subsequent cellicide process. A high concentration impurity ion implantation process is performed to form a high concentration impurity region 17 overlapping with the low concentration impurity region 14.
상기와 같이 본 발명에 의한 공정으로 제조된 트랜지스터를 턴온시키면, NMOS 트랜지스터의 경우 채널은 전자가 반전(inversion)되고, 저농도 불순물 영역은 전자가 축적되어 기존의 트랜지스터에 비해 저농도 불순물 영역의 저항이 감소하여 트랜지스터의 성능을 향상시킬 수 있다.As described above, when the transistor manufactured by the process according to the present invention is turned on, in the case of the NMOS transistor, electrons are inverted in the channel, electrons are accumulated in the low concentration impurity region, and the resistance of the low concentration impurity region is reduced compared to the conventional transistor. The performance of the transistor can be improved.
상술한 바와 같이 본 발명에 의하면 저농도 불순물 영역에 게이트 전극에 의한 전위가 전달될 수 있도록 게이트 전극을 하부에서 소정 두께 잔류되도록 형성하여 트랜지스터를 제조함으로써 숏 채널 이펙트의 악화, 기생 캐패시턴스의 증가, 핫 캐리어 이뮤리티의 저하등의 문제점이 발생되지 않으면서 저농도 불순물 영역의 외부 저항을 효과적으로 감소시켜 트랜지스터의 성능을 크게 향상시킬 수 있다.As described above, according to the present invention, the transistor is manufactured by forming the gate electrode at a lower thickness so that the potential of the gate electrode is transferred to the low concentration impurity region, thereby degrading the short channel effect, increasing the parasitic capacitance, and hot carrier. The performance of the transistor can be greatly improved by effectively reducing the external resistance of the low concentration impurity region without causing problems such as deterioration of the immunity.
Claims (4)
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| KR1020010075056A KR20030044340A (en) | 2001-11-29 | 2001-11-29 | Method of forming a transistor in a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7449403B2 (en) | 2004-08-06 | 2008-11-11 | Hynix Semiconductor Inc. | Method for manufacturing semiconductor device |
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| US5182619A (en) * | 1991-09-03 | 1993-01-26 | Motorola, Inc. | Semiconductor device having an MOS transistor with overlapped and elevated source and drain |
| KR930006971A (en) * | 1991-09-30 | 1993-04-22 | 김광호 | Manufacturing method of MOS transistor |
| KR940016961A (en) * | 1992-12-30 | 1994-07-25 | 김주용 | MOS transistor and its manufacturing method |
| KR960015955A (en) * | 1994-10-31 | 1996-05-22 | 김주용 | Manufacturing method of semiconductor device |
| KR0170436B1 (en) * | 1994-11-02 | 1999-02-01 | 김영환 | Method of manufacturing mosfet |
| JPH08316478A (en) * | 1995-05-12 | 1996-11-29 | Lg Semicon Co Ltd | Improved manufacture for inverset type transistor |
| US5986305A (en) * | 1998-03-30 | 1999-11-16 | Texas Instruments - Acer Incorporated | Semiconductor device with an inverse-T gate lightly-doped drain structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7449403B2 (en) | 2004-08-06 | 2008-11-11 | Hynix Semiconductor Inc. | Method for manufacturing semiconductor device |
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