KR920015609A - Method of manufacturing semiconductor device having curved double gate - Google Patents

Method of manufacturing semiconductor device having curved double gate Download PDF

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Publication number
KR920015609A
KR920015609A KR1019910000704A KR910000704A KR920015609A KR 920015609 A KR920015609 A KR 920015609A KR 1019910000704 A KR1019910000704 A KR 1019910000704A KR 910000704 A KR910000704 A KR 910000704A KR 920015609 A KR920015609 A KR 920015609A
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KR
South Korea
Prior art keywords
oxide film
gate
semiconductor device
applying
source
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Application number
KR1019910000704A
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Korean (ko)
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KR940002781B1 (en
Inventor
허진석
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문정환
금성일렉트론 주식회사
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Priority to KR1019910000704A priority Critical patent/KR940002781B1/en
Publication of KR920015609A publication Critical patent/KR920015609A/en
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Publication of KR940002781B1 publication Critical patent/KR940002781B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

내용 없음No content

Description

곡면 이중 게이트를 갖는 반도체 장치의 제조방법Method of manufacturing semiconductor device having curved double gate

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (a)-(e)는 본발명의 1실시예에 따른 제조공정도이다.2 (a)-(e) are manufacturing process diagrams according to one embodiment of the present invention.

Claims (3)

(a)소자분리된 반도체 기판상에 버퍼산화막, 소오스 및 드레인용 폴리실리콘을 도포하고 LDD구조의 고농도 불순물을 이온주입한 후 필드영역 및 게이트 영역상의 상기 소오스 및 드레인용 폴리실리콘, 상기 버퍼산화막을 식각으로 제거하는 공정과, (b)그 측면에 고온산화막과 비도프된 비정질실리콘이 적층구조로된 측벽을 형성하는 공정과, (c)전면에 게이트산화막을 도포하고 문턱전압조절용 불순물을 이온 주입하는 공정과, (d)전면에 게이트용 폴리실리콘, 캡산화막을 차례로 도포하고 게이트 영역으로 한정식각하는 공정과, (e)산화막으로된 게이트 측벽을 형성하고 그위에 커패시터를 형성하는 공정으로 이루어진 곡면이중 게이트를 갖는 반도체 장치의 제조방법.(a) Applying the buffer oxide film, the source and drain polysilicon on the device-separated semiconductor substrate, ion implantation of high concentration impurities of LDD structure, and then the source and drain polysilicon and the buffer oxide film on the field region and the gate region (B) forming a sidewall of a lamination structure of a high temperature oxide film and an undoped amorphous silicon on the side thereof; (c) applying a gate oxide film on the front surface and implanting impurities for controlling the threshold voltage. And (d) applying a gate polysilicon and a cap oxide film on the entire surface in turn, and limiting etching to the gate region, and (e) forming a gate sidewall of the oxide film and forming a capacitor thereon. A method of manufacturing a semiconductor device having a double gate. 제1항에 있어서, 상기 (a)공정중 식각공정은 액티브영역의 상기 반도체 기판이 소정깊이 만큼 식각되는 것을 특징으로 하는 곡면이중게이트를 갖는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device having a curved double gate according to claim 1, wherein in the etching step (a), the semiconductor substrate in the active region is etched by a predetermined depth. 제1항에 있어서, 상기 (d)공정은 상기 소오스 및 드레인용 폴리실리콘이 소정 깊이만큼 식각되는 것을 특징으로 하는 곡면이중게이트를 갖는 반도체 장치의 제조방법.2. The method of claim 1, wherein in the step (d), the source and drain polysilicon is etched by a predetermined depth. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910000704A 1991-01-17 1991-01-17 Manufacturing method for semiconductor device with curved double gate KR940002781B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000704A KR940002781B1 (en) 1991-01-17 1991-01-17 Manufacturing method for semiconductor device with curved double gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000704A KR940002781B1 (en) 1991-01-17 1991-01-17 Manufacturing method for semiconductor device with curved double gate

Publications (2)

Publication Number Publication Date
KR920015609A true KR920015609A (en) 1992-08-27
KR940002781B1 KR940002781B1 (en) 1994-04-02

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Application Number Title Priority Date Filing Date
KR1019910000704A KR940002781B1 (en) 1991-01-17 1991-01-17 Manufacturing method for semiconductor device with curved double gate

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KR (1) KR940002781B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100338930B1 (en) * 1999-10-19 2002-05-30 박종섭 Manufacturing method for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100338930B1 (en) * 1999-10-19 2002-05-30 박종섭 Manufacturing method for semiconductor device

Also Published As

Publication number Publication date
KR940002781B1 (en) 1994-04-02

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