KR940016924A - Method for manufacturing transistor for high speed device - Google Patents

Method for manufacturing transistor for high speed device Download PDF

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Publication number
KR940016924A
KR940016924A KR1019920027082A KR920027082A KR940016924A KR 940016924 A KR940016924 A KR 940016924A KR 1019920027082 A KR1019920027082 A KR 1019920027082A KR 920027082 A KR920027082 A KR 920027082A KR 940016924 A KR940016924 A KR 940016924A
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KR
South Korea
Prior art keywords
forming
gate
ion implantation
mask
speed device
Prior art date
Application number
KR1019920027082A
Other languages
Korean (ko)
Other versions
KR100253562B1 (en
Inventor
윤종섭
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019920027082A priority Critical patent/KR100253562B1/en
Publication of KR940016924A publication Critical patent/KR940016924A/en
Application granted granted Critical
Publication of KR100253562B1 publication Critical patent/KR100253562B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

고속소자용 트랜지스터를 제조하는 공정에서 반도체기판상에 포토레지스트층을 코팅한후, 게이트 형성용 마스크와 반대형의 마스크인 깊은 이온주입 및 문턱전압용 이온주입마스크를 사용하여, 깊이 이온주입 및 문턱전압용 이온주입영역을 형성함으로써, 소오스/드레인이 형성될 부분에는 이온주입이 되지 않도록하여, 웰농도를 유지시키면서, 소오스/드레인의 접합용량을 감소시킬 수 있다.After fabricating a photoresist layer on a semiconductor substrate in the process of manufacturing a transistor for a high-speed device, using a deep ion implantation mask and a threshold voltage ion implantation mask, which are opposite to the gate forming mask, a deep ion implantation and threshold By forming the ion implantation region for voltage, the ion / implantation is prevented from being implanted in the portion where the source / drain is to be formed, and the junction capacity of the source / drain can be reduced while maintaining the well concentration.

Description

고속소자용 트랜지스터 제조방법Method for manufacturing transistor for high speed device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1(a)도 내지 1(f)도는 본 발명에 따른 고속소자용 트랜지스터를 제조하는 공정을 순서적으로 나타낸 반도체소자의 단면도.1 (a) to 1 (f) are cross-sectional views of a semiconductor device sequentially showing a process of manufacturing a high speed device transistor according to the present invention.

Claims (1)

반도체소자의 고속소자용 트랜지스터 제조방법에 있어서, 실리콘기판(1) 상부에 웰영역(2)을 형성하는 단계와, 상기 웰영역(2) 필드산화막(3)을 형성하는 단계와, 전체구조 상부에 포토레지스트층(4)을 코팅한후, 후에 형성될 게이트 형성용 마스크와 반대형의 마스크를 형성한후, 깊은 이온주입 및 문턱 전압용 이온주입영역(5)을 형성하는 단계와, 잔존하는 포토레지스트층(4)을 제거한후 게이트 산화막(6)을 형성하는 단계와, 상기 게이트 산화막(6) 상부에 게이트용 박막을 증착한후, 게이트(7)를 형성하는 단계와, 상기 게이트(7)을 마스크로 하여 웰영역(2)에 LDD영역(8)을 형성하는 단계와, 상기 게이트(7) 측벽에 스페이서 산화막(9)을 형성한후, 웰영역(2)에 소오스/드레인 영역(10)을 형성하는 단계를 포함하는 것을 특징으로 하는 고속소자용 트랜지스터 제조방법.A method of manufacturing a transistor for a high-speed device of a semiconductor device, the method comprising: forming a well region (2) on an upper surface of a silicon substrate (1), forming a field oxide film (3) on the well region (2), and forming an upper structure After coating the photoresist layer 4 on, forming a mask opposite to the gate forming mask to be formed later, forming the ion implantation region 5 for deep ion implantation and threshold voltage, and remaining Removing the photoresist layer 4 to form a gate oxide film 6, depositing a gate thin film on the gate oxide film 6, and then forming a gate 7, and forming the gate 7. ) As a mask to form the LDD region 8 in the well region 2, the spacer oxide film 9 is formed on the sidewall of the gate 7, and then the source / drain regions are formed in the well region 2. 10) forming a transistor for a high-speed device comprising the step of forming Way. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920027082A 1992-12-31 1992-12-31 Manufacturing method of a transistor for high speed devices KR100253562B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920027082A KR100253562B1 (en) 1992-12-31 1992-12-31 Manufacturing method of a transistor for high speed devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920027082A KR100253562B1 (en) 1992-12-31 1992-12-31 Manufacturing method of a transistor for high speed devices

Publications (2)

Publication Number Publication Date
KR940016924A true KR940016924A (en) 1994-07-25
KR100253562B1 KR100253562B1 (en) 2000-04-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920027082A KR100253562B1 (en) 1992-12-31 1992-12-31 Manufacturing method of a transistor for high speed devices

Country Status (1)

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KR (1) KR100253562B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006252A (en) * 1996-06-28 1998-03-30 김주용 Semiconductor device manufacturing method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770715B2 (en) * 1988-01-19 1995-07-31 松下電器産業株式会社 Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR980006252A (en) * 1996-06-28 1998-03-30 김주용 Semiconductor device manufacturing method

Also Published As

Publication number Publication date
KR100253562B1 (en) 2000-04-15

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