KR940016888A - Transistor Formation Method - Google Patents

Transistor Formation Method Download PDF

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Publication number
KR940016888A
KR940016888A KR1019920023082A KR920023082A KR940016888A KR 940016888 A KR940016888 A KR 940016888A KR 1019920023082 A KR1019920023082 A KR 1019920023082A KR 920023082 A KR920023082 A KR 920023082A KR 940016888 A KR940016888 A KR 940016888A
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KR
South Korea
Prior art keywords
film
oxide film
nitride film
semiconductor substrate
impurities
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Application number
KR1019920023082A
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Korean (ko)
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KR960001613B1 (en
Inventor
인성욱
Original Assignee
김주용
현대전자산업 주식회사
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Priority to KR92023082A priority Critical patent/KR960001613B1/en
Publication of KR940016888A publication Critical patent/KR940016888A/en
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Publication of KR960001613B1 publication Critical patent/KR960001613B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Abstract

본 발명은 반도체 기판(1) 상에 패드 산화막(2), 질화막(3)을 차례로 증착하고 감광막(4)을 패턴하여 게이트 전극이 형성된 부위의 상기 질화막(3)과 패드 산화막(2)을 차례로 식각한 후에 노출된 반도체 기판(1)과 질화막(3) 상에 산화막을 증착하는 제 1 단계, 상기 제 1 단계 후에 상기 질화막(3) 측벽에 스페이서 산화막(5)을 형성하는 제 2 단계, 상기 제 2 단계 후에 상기 스페이서 산화막(5) 사이에 노출된 반도체 기판(1)에 문턱 조절을 위한 불순물을 주입하는 제 3 단계, 상기 제 3 단계 후에 전체구조 상부에 게이트 산화막(6)과 폴리실리콘막(7)을 차례로 증착하고 상기 폴리실리콘막(7)을 전면 에치백(etch back) 식각을 하여 게이트 전극을 형성하는 제 4 단계, 및 상기 제 4 단계 후에 잔류되어져 있는 질화막(3)을 제거하고 LDD이온 주입을 한후에 고농도의 불순물을 주입하여 최종적으로 소오스 전극과 드레인 전극을 형성하는 제 5 단계를 포함하여 이루어 지는 것을 특징으로 하는 트랜지스터 형성 방법에 관한 것이다.According to the present invention, the pad oxide film 2 and the nitride film 3 are sequentially deposited on the semiconductor substrate 1, and the photoresist film 4 is patterned to sequentially turn the nitride film 3 and the pad oxide film 2 at the portion where the gate electrode is formed. A first step of depositing an oxide film on the exposed semiconductor substrate 1 and the nitride film 3 after etching, a second step of forming a spacer oxide film 5 on the sidewall of the nitride film 3 after the first step, After the second step, a third step of injecting impurities for adjusting the threshold into the semiconductor substrate 1 exposed between the spacer oxide film 5, and after the third step, the gate oxide film 6 and the polysilicon film on the entire structure (7) are sequentially deposited and the polysilicon film 7 is etched back etched to form a gate electrode, and the nitride film 3 remaining after the fourth step is removed. High concentration of impurities after LDD ion implantation Injection to be finally formed on the transistor characterized in that which comprises a fifth step of forming a source electrode and a drain electrode.

Description

트랜지스터 형성 방법Transistor Formation Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 본 발명에 따른 MOSFET제조 공정도.1 is a MOSFET manufacturing process according to the present invention.

Claims (2)

트랜지스터 형성 방법에 있어서, 반도체 기판(1) 상에 패드 산화막(2), 질화막(3)을 차례로 증착하고 감광막(4)을 패턴하여 게이트 전극이 형성된 부위의 상기 질화막(3)과 패드 산화막(2)을 차례로 식각한 후에 노출된 반도체 기판(1)과 질화막(3) 상에 산화막을 증착하는 제 1 단계, 상기 제 1 단계 후에 상기 질화막(3) 측벽에 스페이서 산화막(5)을 형성하는 제 2 단계, 상기 제 2 단계 후에 상기 스페이서 산화막(5) 사이에 노출된 반도체 기판(1)에 문턱 조절을 위한 불순물을 주입하는 제 3 단계, 상기 제 3 단계 후에 전체구조 상부에 게이트 산화막(6)과 폴리실리콘막(7)을 차례로 증착하고 상기 폴리실리콘막(7)을 전면 에치백(etch back) 식각을 하여 게이트 전극을 형성하는 제 4 단계, 및 상기 제 4 단계 후에 잔류되어져 있는 질화막(3)을 제거하고 LDD이온 주입을 한후에 고농도의 불순물을 주입하여 최종적으로 소오스 전극과 드레인 전극을 형성하는 제 5 단계를 포함하여 이루어 지는 것을 특징으로 하는 트랜지스터 형성 방법.In the transistor forming method, the pad oxide film 2 and the nitride film 3 are sequentially deposited on the semiconductor substrate 1, and the photoresist film 4 is patterned to form the nitride film 3 and the pad oxide film 2 at the gate electrode formed portion. ) Is sequentially etched and then an oxide film is deposited on the exposed semiconductor substrate 1 and the nitride film 3, and after the first step, the second oxide spacer 5 is formed on the sidewall of the nitride film 3. And a third step of injecting impurities for adjusting the threshold into the semiconductor substrate 1 exposed between the spacer oxide film 5 after the second step, and after the third step, the gate oxide film 6 A fourth step of forming the gate electrode by sequentially depositing the polysilicon film 7 and etching the polysilicon film 7 on the entire surface, and the nitride film 3 remaining after the fourth step. Removal and LDD ion implantation And a fifth step of finally injecting a high concentration of impurities to finally form a source electrode and a drain electrode. 제 1 항에 있어서, 상기 제 5 단계의 LDD이온 주입은 상기 게이트 산화막(6) 밑에 위치한 반도체 기판(1)에 불순물 이온이 주입되도록 경사지게 불순물을 주입하는 것을 특징으로 하는 트랜지스터 형성 방법.The method of claim 1, wherein the LDD ion implantation of the fifth step is performed by injecting impurities inclinedly so that impurity ions are implanted into the semiconductor substrate (1) located under the gate oxide film (6). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR92023082A 1992-12-02 1992-12-02 Method of making transistor KR960001613B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92023082A KR960001613B1 (en) 1992-12-02 1992-12-02 Method of making transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92023082A KR960001613B1 (en) 1992-12-02 1992-12-02 Method of making transistor

Publications (2)

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KR940016888A true KR940016888A (en) 1994-07-25
KR960001613B1 KR960001613B1 (en) 1996-02-02

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980052498A (en) * 1996-12-24 1998-09-25 김영환 Transistor manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980052498A (en) * 1996-12-24 1998-09-25 김영환 Transistor manufacturing method

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Publication number Publication date
KR960001613B1 (en) 1996-02-02

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