KR930001485A - GLDD MOSFET Manufacturing Method - Google Patents

GLDD MOSFET Manufacturing Method Download PDF

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Publication number
KR930001485A
KR930001485A KR1019910009735A KR910009735A KR930001485A KR 930001485 A KR930001485 A KR 930001485A KR 1019910009735 A KR1019910009735 A KR 1019910009735A KR 910009735 A KR910009735 A KR 910009735A KR 930001485 A KR930001485 A KR 930001485A
Authority
KR
South Korea
Prior art keywords
polysilicon
gldd
nitride film
injecting
oxide film
Prior art date
Application number
KR1019910009735A
Other languages
Korean (ko)
Other versions
KR940002404B1 (en
Inventor
권호엽
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910009735A priority Critical patent/KR940002404B1/en
Priority to JP17365592A priority patent/JP3194162B2/en
Priority to DE4219342A priority patent/DE4219342A1/en
Publication of KR930001485A publication Critical patent/KR930001485A/en
Priority to US08/206,208 priority patent/US5424234A/en
Application granted granted Critical
Publication of KR940002404B1 publication Critical patent/KR940002404B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음No content

Description

GLDD 모스패트 제조방법GLDD MOSFET Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 종래의 LDD 모스패트 제조공정을 나타낸 단면도.1 is a cross-sectional view showing a conventional LDD MOSFET manufacturing process.

제 2도는 본 발명의 GLDD 모스패트 제조공정을 나타낸 단면도.2 is a sectional view showing a GLDD MOSFET manufacturing process of the present invention.

* 도면의주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : P웰 2 : 게이트산화막1: P well 2: gate oxide film

3 : 게이트폴리실리콘 4 : 산화막3: gate polysilicon 4: oxide film

5 : 질화막 6 : 폴리실리콘5: nitride film 6: polysilicon

Claims (2)

P웰(1)위에 게이트 산화막(2)과 폴리실리콘(3) 그리고 산화막(4)을 증착하는 공정과, 상기 폴리실리콘(3)과 산화막(4)을 마스킹 공정에 의해 선택적 식각하여 게이트를 정의하는 공정과, 질화막(5)과 폴리실리콘(6)을 차례로 증착하는 공정과, 비등방성 식각에 의해 상기 폴리실리콘(6)과 질화막(5)을 제거하여 측벽을 형성한후 고농도의 N+이온을 주입하는 공정과, 상기 폴리실리콘(6)에 의한 측벽을 제거하고 N-이온을 주입하는 공정과, 상기 질화막(5)에 의한 측벽을 제거하고 N--이온을 주입하는 공정을 차례로 실시하여서 된 GLDD 모스패트 제조방법.A process of depositing a gate oxide film 2, a polysilicon 3, and an oxide film 4 on the P well 1, and selectively etching the polysilicon 3 and oxide film 4 by a masking process to define a gate And the step of depositing the nitride film 5 and the polysilicon 6 in sequence, and removing the polysilicon 6 and the nitride film 5 by anisotropic etching to form sidewalls and then forming a high concentration of N + ions. The step of injecting N, the step of removing the sidewall by the polysilicon 6 and injecting N-ion, and the step of removing the sidewall by the nitride film 5 and injecting N - ion, Method of manufacturing GLDD MOSFET. 제 1 항에 있어서, 측벽을 형성하기 위한 질화막(5)의 두께를 조절하여서 N-영역의 접합깊이를 정할 수 있는 GLDD 모스패트 제조방법.A method according to claim 1, wherein the junction depth of the N − region can be determined by adjusting the thickness of the nitride film (5) for forming the sidewalls. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910009735A 1991-06-13 1991-06-13 Manufacturing method of gldd mosfet KR940002404B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019910009735A KR940002404B1 (en) 1991-06-13 1991-06-13 Manufacturing method of gldd mosfet
JP17365592A JP3194162B2 (en) 1991-06-13 1992-06-09 MOS FET manufacturing method
DE4219342A DE4219342A1 (en) 1991-06-13 1992-06-12 MOS transistor with reduced short channel effect and series resistance - uses three implant levels for drain-source which are self-aligned using a double layer spacer
US08/206,208 US5424234A (en) 1991-06-13 1994-03-03 Method of making oxide semiconductor field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910009735A KR940002404B1 (en) 1991-06-13 1991-06-13 Manufacturing method of gldd mosfet

Publications (2)

Publication Number Publication Date
KR930001485A true KR930001485A (en) 1993-01-16
KR940002404B1 KR940002404B1 (en) 1994-03-24

Family

ID=19315724

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910009735A KR940002404B1 (en) 1991-06-13 1991-06-13 Manufacturing method of gldd mosfet

Country Status (3)

Country Link
JP (1) JP3194162B2 (en)
KR (1) KR940002404B1 (en)
DE (1) DE4219342A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5262664A (en) * 1990-06-30 1993-11-16 Goldstar Electron Co., Ltd. Process for formation of LDD transistor, and structure thereof
US5512506A (en) * 1995-04-06 1996-04-30 Advanced Micro Devices, Inc. Lightly doped drain profile optimization with high energy implants
KR0166850B1 (en) * 1995-09-25 1999-01-15 문정환 Method for fabricating transistor
JP2002509649A (en) 1997-07-11 2002-03-26 テレフオンアクチーボラゲツト エル エム エリクソン Process for manufacturing IC components used at high frequencies
EP1202341A1 (en) * 2000-10-31 2002-05-02 Infineon Technologies AG Method for forming a CMOS device on a semiconductor
DE10146933B4 (en) * 2001-09-24 2007-07-19 Infineon Technologies Ag Integrated spacer-array semiconductor device and method of making the same

Also Published As

Publication number Publication date
JP3194162B2 (en) 2001-07-30
JPH06177146A (en) 1994-06-24
KR940002404B1 (en) 1994-03-24
DE4219342A1 (en) 1992-12-24

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