KR920018980A - P-channel MOSFET manufacturing method - Google Patents

P-channel MOSFET manufacturing method Download PDF

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Publication number
KR920018980A
KR920018980A KR1019910004140A KR910004140A KR920018980A KR 920018980 A KR920018980 A KR 920018980A KR 1019910004140 A KR1019910004140 A KR 1019910004140A KR 910004140 A KR910004140 A KR 910004140A KR 920018980 A KR920018980 A KR 920018980A
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KR
South Korea
Prior art keywords
forming
gate
type
oxide film
film
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Application number
KR1019910004140A
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Korean (ko)
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KR940004271B1 (en
Inventor
하용안
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문정환
금성일렉트론 주식회사
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Priority to KR1019910004140A priority Critical patent/KR940004271B1/en
Publication of KR920018980A publication Critical patent/KR920018980A/en
Application granted granted Critical
Publication of KR940004271B1 publication Critical patent/KR940004271B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음No content

Description

P형 채널 MOSFET 제조방법P-channel MOSFET manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 제조공정 단면도.2 is a cross-sectional view of the manufacturing process of the present invention.

Claims (1)

P형 기판에 N형 웰을 형성하고 이 N형 웰상에 부분격리산화막을 형성하여 액티브영역을 한정하는 공정, 상기 액티브영역의 N형 웰상에 화이트 리본을 제거하기 위한 1차 열산화막을 형성하고 제거하는 공정, 게이트용 2차 열산화막과 오염방지를 위한 게이트용 1차 폴리실리콘막을 차례로 증착한 후 문턱전압 조절용 P형 이온을 주입하는 공정, IN-SITU 도핑공정을 수반하여 게이트용 2차 폴리실리콘막을 형성하고 포토/체치 공정을 거쳐 게이트용 산화막과 게이트 폴리 실리콘막을 형성하는 공정, P형 이온을 주입하는 저농도 소오스/드레인 영역을 형성하고 게이트측벽 산화막을 형성한 다음 P형 이온을 주입하여 고농도 소오스/드레인 영역을 형성하는 공정이 차례로 포함됨을 특징으로 하는 P형 채널 MOSFET 제조방법.Forming an N type well on a P type substrate and forming a partially isolated oxide film on the N type well to define an active region, and forming and removing a primary thermal oxide film for removing a white ribbon on the N type well of the active region Process, depositing the secondary thermal oxide film for gate and the primary polysilicon film for gate prevention, and then injecting P-type ion for threshold voltage control, and the secondary polysilicon for gate with IN-SITU doping process Forming a film, forming a gate oxide film and a gate polysilicon film through a photo / etch process, forming a low concentration source / drain region into which P-type ions are implanted, forming a gate sidewall oxide film, and then implanting a P-type ion A method of manufacturing a P-type MOSFET comprising a step of forming a drain / drain region in sequence. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910004140A 1991-03-15 1991-03-15 Manufacturing method of p-channel mos fet KR940004271B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910004140A KR940004271B1 (en) 1991-03-15 1991-03-15 Manufacturing method of p-channel mos fet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910004140A KR940004271B1 (en) 1991-03-15 1991-03-15 Manufacturing method of p-channel mos fet

Publications (2)

Publication Number Publication Date
KR920018980A true KR920018980A (en) 1992-10-22
KR940004271B1 KR940004271B1 (en) 1994-05-19

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910004140A KR940004271B1 (en) 1991-03-15 1991-03-15 Manufacturing method of p-channel mos fet

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KR (1) KR940004271B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100445058B1 (en) * 1997-06-30 2004-11-16 주식회사 하이닉스반도체 Method for forming gate oxide in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100445058B1 (en) * 1997-06-30 2004-11-16 주식회사 하이닉스반도체 Method for forming gate oxide in semiconductor device

Also Published As

Publication number Publication date
KR940004271B1 (en) 1994-05-19

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