KR100445058B1 - Method for forming gate oxide in semiconductor device - Google Patents

Method for forming gate oxide in semiconductor device Download PDF

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KR100445058B1
KR100445058B1 KR1019970029050A KR19970029050A KR100445058B1 KR 100445058 B1 KR100445058 B1 KR 100445058B1 KR 1019970029050 A KR1019970029050 A KR 1019970029050A KR 19970029050 A KR19970029050 A KR 19970029050A KR 100445058 B1 KR100445058 B1 KR 100445058B1
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gate oxide
oxide film
gas
oxide layer
semiconductor device
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KR19990004890A (en
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최병대
박동수
홍병섭
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN

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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: A method for forming a gate oxide layer is provided to reduce a thickness of the gate oxide layer and improve a characteristic of a semiconductor device by minimizing a thickness of a thermal oxide layer and providing an CVD(Chemical Vapor Deposition) oxide layer having an excellent barrier characteristic against diffusion of impurities. CONSTITUTION: A first gate oxide layer(12) is formed on a surface of a silicon substrate(11) by using a thermal oxidation method. A second gate oxide layer(13) is formed on the first gate oxide layer by performing a CVD process using N2O gas and SiH4 gas. A thermal process for the second gate oxide layer is performed under the atmosphere of argon gas and the N2O gas.

Description

반도체 장치의 게이트 산화막 형성방법{METHOD FOR FORMING GATE OXIDE IN SEMICONDUCTOR DEVICE}A method of forming a gate oxide film of a semiconductor device {METHOD FOR FORMING GATE OXIDE IN SEMICONDUCTOR DEVICE}

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 장치 제조 공정 중 게이트 산화막 형성 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a gate oxide film forming technology during semiconductor device manufacturing processes.

일반적으로 게이트 산화막 형성 공정은 열산화(고온의 산소 분위기에서 실리콘을 산화시키는 방식) 공정을 통해 실리콘 기판 표면에 실리콘 산화막(SiO2)을 형성한다. 열산화 공정은 막의 두께 조절이 용이하여 고집적 소자에서 적용하고 있는 기본적인 산화 방식이다. 모스 트랜지스터의 게이트 산화막은 통상 100Å 내지 500Å의 두께를 갖는다.In general, the gate oxide film forming process forms a silicon oxide film (SiO 2 ) on the surface of a silicon substrate through a thermal oxidation process. Thermal oxidation process is easy to control the thickness of the film is a basic oxidation method applied in the high-density device. The gate oxide film of the MOS transistor usually has a thickness of 100 kV to 500 kV.

일반적인 모스 트랜지스터의 형성 방법을 간략히 보면, 실리콘 기판 위에 게이트 산화막을 성장시키고, 그 상부에 게이트 전극용 폴리실리콘층을 증착한다. 이후 게이트 전극용 마스크를 사용한 사진 식각 공정을 실시하여 게이트 전극을 패터닝하고, 소스 및 드레인 영역에 불순물 이온주입을 실시하는 과정을 수행한다.In brief, a general method of forming a MOS transistor is formed by growing a gate oxide film on a silicon substrate and depositing a polysilicon layer for a gate electrode thereon. Thereafter, a photolithography process using a mask for a gate electrode is performed to pattern the gate electrode, and a process of implanting impurity ions into the source and drain regions is performed.

한편, 반도체 장치의 고집적화에 따른 디자일 룰의 축소와 고속 동작 요구에 부응하기 위하여 보다 얇은 두께의 게이트 산화막이 요구되고 있다.On the other hand, a thinner gate oxide film is required in order to meet the demand for high speed operation and reduction in design rules due to the high integration of semiconductor devices.

종래의 게이트 산화막 형성 공정은, 우선 확산로(furnace) 내에 실리콘 웨이퍼를 로딩하기 전에 확산로 내의 대기를 퍼지하기 위하여 질소(N2) 가스를 흘려준다.The conventional gate oxide film forming process first flows nitrogen (N 2 ) gas to purge the atmosphere in the diffusion furnace before loading the silicon wafer into the diffusion furnace.

그리고, 웨이퍼를 확산로 내에 로딩할 때에도 역시 질소 가스를 흘려준다.Nitrogen gas is also flown when the wafer is loaded into the diffusion furnace.

이후, O2가스 또는 N2O 가스 등의 산화 가스를 확산로 내에 공급하여 열산화를 수행한다.Thereafter, an oxidizing gas such as O 2 gas or N 2 O gas is supplied into the diffusion furnace to perform thermal oxidation.

상기와 같이 종래의 게이트 산화 공정에서는 열산화 단계 이전에 퍼지 가스로 질소(N2) 가스를 사용하고 있는데, 자연 산화막에 대한 억제력이 떨어져 소자 특성을 열화시키는 문제점이 있었다.As described above, in the conventional gate oxidation process, nitrogen (N 2 ) gas is used as the purge gas before the thermal oxidation step, and there is a problem of deterioration of device characteristics due to the suppression of the natural oxide film.

또한, 상기와 같은 열산화 방식에 따라 형성된 게이트 산화막은 기판으로부터의 불순물 확산에 대한 배리어 특성이 떨어져 소자 특성이 열화되는 문제점이 있었다.In addition, the gate oxide film formed by the thermal oxidation method as described above has a problem in that the barrier property against impurity diffusion from the substrate is degraded and the device properties are deteriorated.

전술한 바와 같은 문제점을 해결하기 위하여 제안된 본 발명은, 소자 특성을 개선할 수 있는 반도체 장치의 게이트 산화막 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention proposed to solve the problems described above has an object to provide a method for forming a gate oxide film of a semiconductor device capable of improving device characteristics.

도 1a 내지 도 1c는 본 발명의 일실시예에 따른 모스 트랜지스터 제조 공정을 나타낸 단면도.1A to 1C are cross-sectional views illustrating a MOS transistor manufacturing process according to an embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

11 : 실리콘 기판 12 : 열산화막11 silicon substrate 12 thermal oxide film

13 : 화학기상증착 산화막 14 : 폴리실리콘막13 chemical vapor deposition oxide film 14 polysilicon film

상기와 같은 목적을 달성하기 위한 본 발명의 일 측면에 따르면, 실리콘 기판 표면에 열산화 방식으로 제1 게이트 산화막을 성장시키는 단계; N2O 가스 및 SiH4가스를 사용하여 상기 제1 게이트 산화막 상에 화학기상증착 방식으로 제2 게이트 산화막을 증착하는 단계; 및 아르곤 가스 및 N2O 가스 분위기에서 상기 제2 게이트 산화막에 대해 열처리를 수행하는 단계를 포함하는 반도체 소자의 게이트 산화막 형성방법이 제공된다.According to an aspect of the present invention for achieving the above object, the step of growing a first gate oxide film on the surface of the silicon substrate by thermal oxidation; Depositing a second gate oxide film on the first gate oxide film by chemical vapor deposition using N 2 O gas and SiH 4 gas; And performing a heat treatment on the second gate oxide film in an argon gas and an N 2 O gas atmosphere.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

먼저, 도 1a 내지 도 1c는 본 발명의 일실시예에 따른 모스 트랜지스터의 제조 공정을 나타낸 단면도이다.First, FIGS. 1A to 1C are cross-sectional views illustrating a manufacturing process of a MOS transistor according to an exemplary embodiment of the present invention.

먼저, 도1a에 도시된 바와 같이, 실리콘 기판(11) 표면에 열산화막(12)을 성장시킨다. 이때, 자연 산화막의 성장을 억제하고자 확산로 내로의 대기 유입을 차단하기 위해 퍼지박스(purge box)를 이용하여 이 박스 내로 아르곤 가스를 흘려주는 공정을 실시하며, 또한 실리콘 기판을 확산로 내로 로딩하는 동안에도 아르곤 가스를 흘려주어 자연 산화막 형성을 막을 수 있다. 한편, 열산화막(12)은 O2혹은 N2O 가스를 산화 가스로 사용하여 성장시키며, 그 두께가 20Å를 넘지 않도록 한다.First, as shown in FIG. 1A, a thermal oxide film 12 is grown on the silicon substrate 11 surface. At this time, in order to suppress the growth of the natural oxide film, in order to block the inflow of the atmosphere into the diffusion furnace, a process of flowing argon gas into the box using a purge box is performed, and the silicon substrate is loaded into the diffusion furnace. Argon gas can also be flowed in to prevent the formation of natural oxides. On the other hand, the thermal oxide film 12 is grown using O 2 or N 2 O gas as the oxidizing gas, so that the thickness thereof does not exceed 20 kPa.

다음으로, 도1b에 도시된 바와 같이, 열산화막(12) 상에 화학기상증착 산화막(13)을 증착한다. 여기서 화학기상증착 산화막(13)은 SiH4가스 및 N2O 가스를 사용한 화학기상증착법으로 증착하고, 이후 아르곤 가스 분위기의 900℃ 이상으로 램프 업한 후 N2O 가스 및 아르곤 가스 분위기에서 어닐링(Annealing)을 수행한다.Next, as shown in FIG. 1B, a chemical vapor deposition oxide film 13 is deposited on the thermal oxide film 12. The chemical vapor deposition oxide film 13 is deposited by chemical vapor deposition using SiH 4 gas and N 2 O gas, and then ramped up to 900 ° C. or higher in an argon gas atmosphere, and then annealed in an N 2 O gas and an argon gas atmosphere. ).

마지막으로, 도 1c에 도시된 바와 같이, 화학기상증착 산화막(13) 상에 게이트 전극용 폴리실리콘막(14)을 증착한다.Finally, as shown in FIG. 1C, the polysilicon film 14 for the gate electrode is deposited on the chemical vapor deposition oxide film 13.

이후, 폴리실리콘막(14)을 패터닝하여 게이트 전극을 형성하고, 소스/드레인 이온주입을 실시하면, 모스 트랜지스터 제조가 완료된다.Thereafter, the polysilicon film 14 is patterned to form a gate electrode, and source / drain ion implantation is performed to complete the manufacture of the MOS transistor.

SiH4가스 및 N2O 가스를 사용하여 증착된 화학기상증착 산화막(13)은 열산화막(12)에 비해 밀도가 조금 낮다. 그러나, 상기와 같은 열처리를 거치면서 막의 밀도가 증가하고 질화작용에 의해 캐패시턴스가 증가하여 얇은 두께를 가지면서도 불순물에 대한 배리어 특성은 오히려 증가하게 된다.The chemical vapor deposition oxide film 13 deposited using SiH 4 gas and N 2 O gas is slightly lower in density than the thermal oxide film 12. However, through the heat treatment as described above, the film density increases and the capacitance increases due to nitriding, so that the barrier property against impurities is increased while having a thin thickness.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명이 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

상기와 같이 이루어지는 본 발명은 열산화막의 두께를 최소화하면서 불순물 확산에 대한 배리어 특성이 우수한 화학기상증착 산화막을 제공함으로써 종래의 기술에 비해 상대적으로 얇은 두께의 게이트 산화막으로도 소자 특성을 확보할 수 있다.According to the present invention made as described above, by providing a chemical vapor deposition oxide film having excellent barrier properties against impurity diffusion while minimizing the thickness of the thermal oxide film, device characteristics can be secured even with a gate oxide film having a relatively thin thickness compared to the conventional technology. .

Claims (5)

실리콘 기판 표면에 열산화 방식으로 제1 게이트 산화막을 성장시키는 단계;Growing a first gate oxide film on the surface of the silicon substrate by thermal oxidation; N2O 가스 및 SiH4가스를 사용하여 상기 제1 게이트 산화막 상에 화학기상증착 방식으로 제2 게이트 산화막을 증착하는 단계; 및Depositing a second gate oxide film on the first gate oxide film by chemical vapor deposition using N 2 O gas and SiH 4 gas; And 아르곤 가스 및 N2O 가스 분위기에서 상기 제2 게이트 산화막에 대해 열처리를 수행하는 단계Performing a heat treatment on the second gate oxide film in an argon gas and an N 2 O gas atmosphere 를 포함하는 반도체 소자의 게이트 산화막 형성방법.Gate oxide film forming method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제1 게이트 산화막의 성장이 이루어지는 퍼니스 내로 상기 실리콘 기판의 로딩이 완료되기 전에 아르곤 가스 퍼지를 수행하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 게이트 산화막 형성방법.And argon gas purging before the silicon substrate is loaded into the furnace where the first gate oxide film is grown. 제1항에 있어서,The method of claim 1, 상기 제1 게이트 산화막의 두께는 20Å을 넘지 않도록 성장시키는 것을 특징으로 하는 반도체 장치의 게이트 산화막 형성방법.And the thickness of the first gate oxide film is not larger than 20 GPa. 제3항에 있어서,The method of claim 3, 상기 제1 게이트 산화막은 O2또는 N2O 가스를 산화 가스로 사용하여 성장시키는 것을 특징으로 하는 반도체 장치의 게이트 산화막 형성방법.And the first gate oxide film is grown using O 2 or N 2 O gas as an oxidizing gas. 제1항에 있어서,The method of claim 1, 상기 열처리를 수행하는 단계는,The step of performing the heat treatment, 아르곤 가스 분위기에서 900℃ 이상의 온도로 램프 업하는 단계와,Ramping up to a temperature of 900 ° C. or higher in an argon gas atmosphere, N2O 가스 및 아르곤 가스 분위기에서 어닐하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 게이트 산화막 형성방법.And annealing in an atmosphere of N 2 O gas and argon gas.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61220451A (en) * 1985-03-27 1986-09-30 Toshiba Corp Manufacture of semiconductor device
JPS62190766A (en) * 1986-02-18 1987-08-20 Oki Electric Ind Co Ltd Manufacture of mos type semiconductor device
KR920018980A (en) * 1991-03-15 1992-10-22 문정환 P-channel MOSFET manufacturing method
KR960002819A (en) * 1994-06-30 1996-01-26 김주용 Transistor Formation Method of Semiconductor Device
KR960011462A (en) * 1994-09-08 1996-04-20 프랭크 에이. 오울플링 Optical connector and its polishing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61220451A (en) * 1985-03-27 1986-09-30 Toshiba Corp Manufacture of semiconductor device
JPS62190766A (en) * 1986-02-18 1987-08-20 Oki Electric Ind Co Ltd Manufacture of mos type semiconductor device
KR920018980A (en) * 1991-03-15 1992-10-22 문정환 P-channel MOSFET manufacturing method
KR960002819A (en) * 1994-06-30 1996-01-26 김주용 Transistor Formation Method of Semiconductor Device
KR960011462A (en) * 1994-09-08 1996-04-20 프랭크 에이. 오울플링 Optical connector and its polishing method

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