KR930003292A - Method for manufacturing transistor of LDD structure with multi channel - Google Patents

Method for manufacturing transistor of LDD structure with multi channel Download PDF

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Publication number
KR930003292A
KR930003292A KR1019910011802A KR910011802A KR930003292A KR 930003292 A KR930003292 A KR 930003292A KR 1019910011802 A KR1019910011802 A KR 1019910011802A KR 910011802 A KR910011802 A KR 910011802A KR 930003292 A KR930003292 A KR 930003292A
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KR
South Korea
Prior art keywords
channel layer
substrate
gate
forming
ldd structure
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Application number
KR1019910011802A
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Korean (ko)
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KR940004412B1 (en
Inventor
황이연
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문정환
금성일렉트론 주식회사
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Priority to KR1019910011802A priority Critical patent/KR940004412B1/en
Publication of KR930003292A publication Critical patent/KR930003292A/en
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Publication of KR940004412B1 publication Critical patent/KR940004412B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

내용 없음.No content.

Description

멀티 채널을 갖는 LDD 구조의 트랜지스터 제조방법LDD structure transistor manufacturing method with multi channel

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 제조 공정단면도.2 is a cross-sectional view of the production process of the present invention.

Claims (2)

기판에 게이트 형성이후 진행되는 공정에 있어서, 게이트를 마스크로 기판과 동형의 이온을 이후에 형성될 LDD층에 적합한 농도로 주입하여 제1채널층을 형성하는 스텝, 게이트를 마스크로 기판과 이형의 저농도 이온을 주입하여 제1채널층 상측에 LDD층을 형성하는 스텝, 게이트 측벽 스페이서를 형성하고 게이트와 측벽스페이서를 마이크로 기판과 이형의 고농도 이온을 주입하여 제1채널층 상측에 소오스/드레인 영역을 형성하기 위한 스텝, 상기 게이트와 측벽스페이서를 마스크로 기판과 동형의 이온을 소오스/드레인영역에 적합한 농도로 주입하여 소오스/드레인 영역 하측에 제2채널층을 형성하기 위한 스텝 이 차례로 포함됨을 특징으로 하늘 멀티 채널을 갖는 LDD구조의 트랜지스터 제조방법.In the process that proceeds after gate formation on the substrate, a step of forming a first channel layer by implanting ions of the same type as the substrate using a gate as a mask at a concentration suitable for an LDD layer to be formed later, and forming a first channel layer using the gate as a mask Forming a LDD layer over the first channel layer by implanting low concentration ions; And forming a second channel layer under the source / drain region by injecting ions of the same type as the substrate with the gate and the sidewall spacer at a concentration suitable for the source / drain region. A transistor manufacturing method of an LDD structure having an empty multi channel. 제1항에 있어서, 기판의 이온 도핑 농도를 Po, 제1채널층의 도핑 농도를 P1, 제2채널층의 도핑 농도를 P2라 할때 Po＜P1＜P2의 부등식이 성립하는 것을 특징으로 하는 멀티채널을갖는 LDD구조의 트랜지스터 제조방법.The inequality of Po <P 1 <P 2 is established when the ion doping concentration of the substrate is Po, the doping concentration of the first channel layer is P 1 , and the doping concentration of the second channel layer is P 2 . A transistor manufacturing method of an LDD structure having a multichannel, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910011802A 1991-07-11 1991-07-11 Making method of ldd structured transistor with multi-channel KR940004412B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910011802A KR940004412B1 (en) 1991-07-11 1991-07-11 Making method of ldd structured transistor with multi-channel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910011802A KR940004412B1 (en) 1991-07-11 1991-07-11 Making method of ldd structured transistor with multi-channel

Publications (2)

Publication Number Publication Date
KR930003292A true KR930003292A (en) 1993-02-24
KR940004412B1 KR940004412B1 (en) 1994-05-25

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910011802A KR940004412B1 (en) 1991-07-11 1991-07-11 Making method of ldd structured transistor with multi-channel

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Also Published As

Publication number Publication date
KR940004412B1 (en) 1994-05-25

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