KR950004561A - Static ram and manufacturing method - Google Patents

Static ram and manufacturing method Download PDF

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Publication number
KR950004561A
KR950004561A KR1019930012578A KR930012578A KR950004561A KR 950004561 A KR950004561 A KR 950004561A KR 1019930012578 A KR1019930012578 A KR 1019930012578A KR 930012578 A KR930012578 A KR 930012578A KR 950004561 A KR950004561 A KR 950004561A
Authority
KR
South Korea
Prior art keywords
ion implantation
concentration ion
forming
sram
static ram
Prior art date
Application number
KR1019930012578A
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Korean (ko)
Inventor
성진모
양종렬
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930012578A priority Critical patent/KR950004561A/en
Publication of KR950004561A publication Critical patent/KR950004561A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices

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  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체 기판(1); 상기 반도체 기판(1) 상에 형성되는 게이트 산화막(5), 상기 게이트 산화막(5) 상에 형성되는 소정 크기의 게이트전극(3′), LDD구조를 갖는 스페이서 절연막(9)과 저농도 이온 주입부(8)와 활성영역을 이루는 고농도 이온 주입부(10)로 이루어지는 억세스 트랜지스터를 갖는 스태틱램(SRAM)에 있어서, 상기 억세스 트랜지스터의 소오스전극을 이루는 저농도 이온 주입부(8)를 둘러쌓는 포켓 이온 주입부(7)를 더 포함하여 이루어지는 것을 특징으로 하는 스태틱램(SRAM) 및 그 제조방법에 관한 것이다.The present invention is a semiconductor substrate (1); A gate oxide film 5 formed on the semiconductor substrate 1, a gate electrode 3 ′ of a predetermined size formed on the gate oxide film 5, a spacer insulating film 9 having an LDD structure, and a low concentration ion implantation portion; In a static RAM (SRAM) having an access transistor comprising a high concentration ion implantation portion 10 forming an active region with (8), pocket ion implantation surrounding the low concentration ion implantation portion 8 forming a source electrode of the access transistor. It relates to a static RAM (SRAM) characterized in that it further comprises a section (7) and a method of manufacturing the same.

Description

스태틱램 및 그 제조방법Static ram and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 3 도는 본 발명에 따른 억세스 트랜지스터의 구조도, 제 4 도는 본 발명에 따른 억세스 트랜지스터의 제조 공정 단면도.3 is a structural diagram of an access transistor according to the present invention, and FIG. 4 is a cross-sectional view of a process of manufacturing an access transistor according to the present invention.

Claims (2)

반도체 기판(1); 상기 반도체 기판(1) 상에 형성되는 게이트 산화막(5), 상기 게이트 산화막(5) 상에 형성되는 소정 크기의 게이트전극(3′), LDD 구조를 갖는 스페이서 절연막(9)과 저농도 이온주입부(8)와 활성영역을 이루는 고농도 이온 주입부(10)로 이루어지는 억세스 트랜지스터를 갖는 스태틱램(SRAM)에 있어서, 상기 억세스 트랜지스터의 소오스전극을 이루는 저농도 이온 주입부(8)를 둘러쌓는 포켓 이온 주입부(7)를 더 포함하여 이루어지는 것을 특징으로 하는 스태틱램(SRAM).Semiconductor substrate 1; A gate oxide film 5 formed on the semiconductor substrate 1, a gate electrode 3 ′ of a predetermined size formed on the gate oxide film 5, a spacer insulating film 9 having an LDD structure, and a low concentration ion implantation portion In a static RAM (SRAM) having an access transistor comprising a high concentration ion implantation portion 10 forming an active region with (8), pocket ion implantation surrounding the low concentration ion implantation portion 8 forming a source electrode of the access transistor. Static RAM (SRAM) characterized in that it further comprises a section (7). 억세스 트랜지스터를 갖는 스태틱램(SRAM) 제조방법에 있어서, 반도체 기판(1) 상에 게이트 산화막(5)과 게이트전극(3′)을 차례로 형성하는 단계와; 소정의 부위를 이온 주입하기 위하여 마스크층(6)을 형성하고 이후에 형성될 활성영역과 반대형의 불순물을 주입하여 포켓 이온 주입부(7)를 형성하는 단계와; LDD형성을 위한 저농도 이온 주입 공정을 실시하여 저농도 이온 주입부(8)를 형성하고 상기 게이트전극(3′) 측벽에 스페이서 절연막(9)을 형성한 다음에 고농도 이온 주입부인 소오스 및 드레인전극(10)을 형성하는 단계를 포함하여 억세스 트랜지스터를 형성하는 것을 특징으로 하는 스태틱램(SRAM) 제조방법.A method of manufacturing a static RAM (SRAM) having an access transistor, comprising: sequentially forming a gate oxide film (5) and a gate electrode (3 ') on a semiconductor substrate (1); Forming a pocket layer (7) by implanting a mask layer (6) to implant a predetermined portion and implanting impurities of a type opposite to an active region to be formed later; A low concentration ion implantation part 8 is formed by performing a low concentration ion implantation process for LDD formation, a spacer insulating film 9 is formed on the sidewall of the gate electrode 3 ', and then a source and drain electrode 10 as a high concentration ion implantation part is formed. (SRAM) manufacturing method comprising the step of forming an access transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930012578A 1993-07-05 1993-07-05 Static ram and manufacturing method KR950004561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930012578A KR950004561A (en) 1993-07-05 1993-07-05 Static ram and manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930012578A KR950004561A (en) 1993-07-05 1993-07-05 Static ram and manufacturing method

Publications (1)

Publication Number Publication Date
KR950004561A true KR950004561A (en) 1995-02-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930012578A KR950004561A (en) 1993-07-05 1993-07-05 Static ram and manufacturing method

Country Status (1)

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KR (1) KR950004561A (en)

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