KR920015442A - Method of manufacturing semiconductor memory device - Google Patents

Method of manufacturing semiconductor memory device Download PDF

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Publication number
KR920015442A
KR920015442A KR1019910000648A KR910000648A KR920015442A KR 920015442 A KR920015442 A KR 920015442A KR 1019910000648 A KR1019910000648 A KR 1019910000648A KR 910000648 A KR910000648 A KR 910000648A KR 920015442 A KR920015442 A KR 920015442A
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KR
South Korea
Prior art keywords
photo
ion implantation
implantation process
memory device
semiconductor memory
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Application number
KR1019910000648A
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Korean (ko)
Other versions
KR100198605B1 (en
Inventor
구자경
김남용
이원기
Original Assignee
문정환
금성일렉트론 주식회사
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910000648A priority Critical patent/KR100198605B1/en
Publication of KR920015442A publication Critical patent/KR920015442A/en
Application granted granted Critical
Publication of KR100198605B1 publication Critical patent/KR100198605B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

반도체 기억소자 제조방법Method of manufacturing semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 제조공정 단면도.2 is a cross-sectional view of the manufacturing process of the present invention.

Claims (1)

기판위에 게이트 산화막을 형성하고 문턱전압조절을 위한 이온주입공정을 실시하는 단계, 포토/이온주입공정을 실시하여 셀이 형성될 영역을 디플리션 영역으로 만드는 단계, 폴리실리콘막을 증착하고 포토/에치공정을 실시하여 게이트 폴리실리콘막을 형성한 다음 포토/이온주입공정을 실시하여 소오스/드레인영역을 형성하는 단계, 코드 포토/이온주입공정을 실시하여 선택한 특정부분을 인헨스먼트 영역으로 형성하는 단계가 차례로 포함됨을 특징으로 하는 반도체 기억소자 제조방법.Forming a gate oxide film on the substrate, performing an ion implantation process for adjusting the threshold voltage, and performing a photo / ion implantation process to make a region where a cell is to be formed as a depletion region; depositing a polysilicon film and depositing a photo / etch Performing a process to form a gate polysilicon film and then performing a photo / ion implantation process to form a source / drain region, and performing a code photo / ion implantation process to form a selected specific portion as an enhancement region. Method of manufacturing a semiconductor memory device, characterized in that included in order. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910000648A 1991-01-16 1991-01-16 Semiconductor memory device fabrication method KR100198605B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000648A KR100198605B1 (en) 1991-01-16 1991-01-16 Semiconductor memory device fabrication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000648A KR100198605B1 (en) 1991-01-16 1991-01-16 Semiconductor memory device fabrication method

Publications (2)

Publication Number Publication Date
KR920015442A true KR920015442A (en) 1992-08-26
KR100198605B1 KR100198605B1 (en) 1999-06-15

Family

ID=19309905

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000648A KR100198605B1 (en) 1991-01-16 1991-01-16 Semiconductor memory device fabrication method

Country Status (1)

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KR (1) KR100198605B1 (en)

Also Published As

Publication number Publication date
KR100198605B1 (en) 1999-06-15

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