DE4219342A1 - MOS transistor with reduced short channel effect and series resistance - uses three implant levels for drain-source which are self-aligned using a double layer spacer - Google Patents

Abstract

The metal-oxide semiconductor (MOS) transistor is made using the following process steps: after formation of the gate dielectric layer, gate-electrode and gate insulator structure an insulating layer (5), pref. Si-nitride, is deposited followed by a semiconductor layer (6), pref. undoped polysilicon, or another insulation layer with a different etch rate, pref. Si-dioxide. This double layer is etched to leave double layer spacers (5a,6a) at the edges of the gate electrode. The etching action is pref. anisotropic, pref. carried out using dry etching, especially using RIE. A first implantation (8) of drain/source dopant is carried out. Then the semiconducting spacer (6a) is removed and a second, pref. lower level, implantation (9) of drain/source dopant carried out. The insulating part of the spacer (5a) is then removed and a third, pref. lowest level, implantation (10) carried out of the drain/source dopant. Also claimed is a first insulation layer (5) which is sufficiently thin to allow diffusion of dopant through it to take place. The gate dielectric and gate insulator layer are pref., SiO2 layers, the gate electrode is pref. doped poly Si. USE/ADVANTAGE - The structure has the advantage of a lower resistance lightly-doped-drain (LDD) structure, which has a lower sideways diffusion, resulting in a longer channel than conventional devices. This is manifested in a higher Vt than conventional devices and a lower leakage current. The substrate current is lower also, e.g. by a factor of about 5, than conventional devices, which shows a reduced carrier generation rate, and so a reduced injection rate into the dielectric. The stability of the Vt is consequently better. The structure is used in the mfr. of 64Mbit DRAMs.

Description

The invention relates to a method for producing a Me tall oxide semiconductor field effect transistor and in particular Process for producing a metal oxide semiconductor field fect transistor with weakly doped drain structure. The he metal oxide semiconductor field effect transistor according to the invention weakly doped drain structure avoids generation hot electrons as a result of one in the edge areas of its gate Electrode resulting strong electric field, whereby its lifespan and reliability can be improved.

In FIGS. 8A to 8C, a conventional method is for the manufacture of a lung metal oxide semiconductor field effect transistor (MOSFET) with lightly doped drain structure (LDD structure) provides Darge.

Field regions 12 are first formed on a p-type semiconductor substrate 11 in order to isolate neighboring cells from one another, as shown in FIG. 8A. Impurity ions for generating an electrical characteristic of the MOSFET to be produced are implanted in a part of the surface of the p-type semiconductor substrate 11 which corresponds to the respective active region between adjacent field regions 12 . Thereafter, a gate insulating layer 13 is formed over the entire surface of the p-type semiconductor substrate 11 including the field regions 12 . A gate electrode 14 having a certain width is formed on the gate insulating layer 13 within each active region. The exposed surface of the gate electrode 14 is subjected to oxidation, whereby a gate cap insulating layer 15 is formed. A semiconductor layer 16 with a certain thickness is formed over the entire exposed surface to form gate side walls.

Then, the semiconductor layer 16 is anisotropically etched using a reactive ion etching (RIE) method, whereby the gate sidewall semiconductor layers 17 are formed on the side walls of the gate electrode 14 , as shown in FIG. 8B. The gate cap insulating layer 15 formed on the upper surface of the gate electrode 14 serves as an etching stopper. Then, using the gate cap insulating layer 15 and the gate sidewall semiconductor layer 17 as a mask, nionen impurity ions (ie, in high concentration) are implanted in a part of the surface of the p-type semiconductor substrate 11 that corresponds to the active region. The n + source and drain regions 18 and 18 a are formed by diffusion of the impurity ions.

Thereafter, the gate sidewall semiconductor layers 17 are removed as shown in FIG. 8C. Using the gate cap insulating layer 15 as a mask, n⁻ impurity ions (ie in low concentration) are then implanted in a part of the surface of the p-type semiconductor substrate 11 that corresponds to the active region. By diffusion of the Störstellenio NEN n-source and drain regions 19 and 19 a arise.

The source / drain regions thus form an LDD structure Areas of high and low concentration.

The operation of a MOSFET will now be described in connection with FIG. 9.

If a gate bias voltage V _G (about 3.3 V) to the gate electrode 14 , a drain voltage V _D (about 3.3 V) to the n⁺-drain region 18 a and the n⁻- Drain region 19 a and a negative substrate voltage V _{S are applied} to the p-type semiconductor substrate 11 , an inversion layer and a depletion layer are formed. In the n⁻-source region 19 electrons are generated, which in turn meet a grid in the n Drain-drain region 19 a and thereby cause the generation of defect electrons and electrons.

The electrons generated are injected into the n⁻ drain region 19 a, at which the positive voltage of approximately 3.3 V is present. However, the generated defect electrons are transported to three areas. That is, the flaws who are not only captured by the gate electrode 14 and the gate insulating layer 13 , but often also transported to the p-type semiconductor substrate 11 . The defect electrons trapped in the gate electrode 14 can influence the overall circuit, but have hardly any effect on the operation of the MOSFET. The defect electrons transported to the p-type semiconductor substrate 11 also have no effect on the operation of the MOSFET, since they disappear in the p-type semiconductor substrate 11 . The defect electrons trapped in the gate insulating layer 13 , however, lead to the switching on of the MOSFET before the prescribed bias voltage V _G of approximately 3.3 V is applied to the gate electrode 14 .

As a result, the operating characteristics of the MOSFET and the reliability of the device finally obtained deteriorate. In trapping holes in the gate insulating layer 13 may further include a defect on the gate insulating layer 13 may occur, whereby the performance of the element ver deteriorated and reduce its life span. Defect electrons of this type are referred to as hot carriers (also called: hot charge carriers), and the phenomenon they cause is referred to as the hot carrier effect.

In the known methods, there is also the problem of a Wi as the source / drain regions from n aus- and n⁻-areas are formed. Besides, you can't Source / drain areas with the desired exact widths hold as the precise control of the thickness of the gate sidewall  semiconductor layers is difficult. This creates a short channel effect.

It is therefore an object of the invention to provide a method for To provide manufacture of a MOSFET in which a source / drain region is divided into three areas, whereby that from the appearance of hot charge carriers and the short channel effectively resulting problem is avoided.

This object is achieved with the features of An spell 1 solved.

Other tasks and considerations are given below of exemplary embodiments and with reference to the drawings he purifies. Show it:

FIGS. 1A to 1F are sectional views illustrating a method according to the invention for manufacturing a MOSFET;

Figs. 2A and 2B surface doping profiles to surfaces of MOSFETs according to the present invention or by known processes;

. 3A and 3B are graphs of drain-induced potential schwellenerniedrigungs- (DIBL) values in MOSFETs according to the known prior lying invention or by methods;

FIGS. 4A and 4B are diagrams of the extrapolated Schwellwertspan voltages in MOSFETs according to the present invention or by known processes;

Fig. 5A and 5B are diagrams of the substrates out-flowing hole in MOSFETs amount according to the present OF INVENTION dung or by known processes;

Fig. 6 is a diagram for explaining the relationship between the gate length and threshold voltage;

7A and 7B are potential profiles to substrate surfaces of MOSFETs according to the present invention or by known processes.

Figs. 8A to 8C are sectional views illustrating a conventional method of manufacturing a MOSFET having the LDD structure; and

Fig. 9 is a view for explaining the operation of a conventional MOSFET.

In Figs. 1A to 1F, an inventive method is for the manufacture of a MOSFET position shown.

First, a gate insulating layer 2 , a gate electrode 3 and a gate cap insulating layer 4 are formed on a p-type semiconductor substrate 1 in this order, as shown in FIG. 1A. The unnecessary parts of these layers are then removed using a known photolithography method and a known dry etching method.

In this case, the gate insulating layer 2 made of silicon dioxide (SiO ₂ ), the gate electrode 3 made of polysilicon, and the gate cap insulating layer 4 made of silicon dioxide.

Then, as shown in FIG. 1C, an insulating layer 5 and a semiconductor layer 6 are formed on the entire exposed surface, using a chemical deposition method from the gas phase (CVD method), which are intended to serve as gate side walls. Thereafter, as shown in FIG. 1D, the insulating layer 5 and the semiconductor layer 6 are anisotropically etched using a reactive ion etching method (RIE method), which is a kind of dry etching method. Due to the anisotropic etching, the insulating layer 5 and the semiconductor layer 6 remain only on the side faces of the gate electrode 3 and the gate cap insulating layer 4 , whereby the gate side walls 7 are formed. During the anisotropic etching, the gate cap insulating layer 4 and the gate insulating layer 2 serve as etch stop layers.

Using the gate cap insulating layer 4 and the gate side walls 7 as a mask, n⁺ impurity ions of high concentration are planted in the surface of the p-type semiconductor substrate 1 . By diffusion of the impurity ions arise the n⁺ source and drain regions 8 and 8 a, as shown in Fig. 1D Darge.

In this case, the insulating layer 5 consists of silicon nitride, while the semiconductor layer 6 consists of undoped polysilicon. Phosphorus (P) ions and arsenic (As) ions are used as n⁺ impurity ions.

Thereafter, the remaining parts of the semiconductor layers 6 a on the upper parts of the gate side walls are removed, as shown in Fig. 1E. Using the remaining insulating layer parts 5 a and the gate cap insulating layer 4 as a mask, n⁻ impurity ions of relatively low concentration (n⁺ <n⁻) are then implanted into the surface of the p-type semiconductor substrate 1 . The n + source and drain regions 9 and 9 a are formed by diffusion of the impurity ions, as shown in FIG. 1E.

Finally, the remaining insulating layer parts 5 a are removed on the lower parts of the gate side walls 7 , as shown in FIG. 1F. Then, n ^- impurity ions of lower concentration are implanted into the surface of the p-type semiconductor substrate 1 and diffused to form the n ^- source and drain regions 10 and 10 a.

Similar to the n⁺ impurity ions, the n⁻ and n ^- impurity ions are P or As ions.

The concentrations of the n⁺, n ^- or n ^- impurity ions can be controlled in a suitable manner depending on the desired characteristic of the MOSFET to be produced. According to the invention, three source / drain regions are formed, the region closer to the gate electrode 3 having the lower concentration. The source / drain areas form a gradually decreasing curve.

In the illustrated embodiment of the invention is as An n-MOSFET has been chosen as an example. However, it is open Obviously, the present invention is also applicable to the manuf p-MOSFET can be applied by the guide Ability types of the substrate and the impurity ions for bil source / drain areas.

In Fig. 2A to 7B, various data are of a union herkömm n-MOSFET and an n-MOSFET of the present invention provides Darge. The samples used were obtained by modeling a 64M DRAM memory with a gate mask length of 0.5 µm.

The superiority of the present invention explained.

Fig. 2A shows a view taken along line aa 'in Fig. 1F aufgenom menes surface doping profile, which is a section through the inventive MOSFET (hereinafter referred to as a new MOSFET). In contrast, Fig. 2B shows a surface profile profile, which was taken along line bb 'in Fig. 8C men and represents a section through the MOSFET produced by known methods (hereinafter referred to as old MOSFET).

In Fig. 2A and 2B by the reference numeral c and c 'denotes a channel length. As shown in FIG. 2A and 2B, the channel length of the new MOSFETs is closer to a pre-given gate mask length than the channel length of the old MOSFETs. In the new MOSFET, the length of an n-channel region defined after the formation of source / drain regions using a side diffusion method was 0.33 μm. In the case of the old MOSFET, the length was 0.23 µm. Accordingly, it can be determined that the n-channel area of the new MOSFET is 0.10 µm (approximately 40%) longer than that of the old MOSFET.

Fig. 3A and 3B show graphs of drain-induced Poten tialschwellenerniedrigungs- (DIBL-) values for the new or the old MOSFET. These DIBL values are briefly described below.

A drain voltage lowers the potential threshold defined between the source and drain regions. As a result, leakage current occurs between the source and drain regions when the gate voltage is lower than the threshold voltage. The DIBL value means such a leakage current, expressed by the voltage value. Fig. 3A and 3B show the difference between the gate voltages at drain voltages of 0.05 V and 3.3 V, respectively, and the same drain current I _D. FIG. 3A applies to the new MOSFET, FIG. 3B to the old MOSFET. The new MOSFET has a DIBL value of around 64 mV, while the DIBL value of the old MOSFET of 126 mV is significantly higher than that of the new MOSFET. This higher DIBL value leads to the earlier switching on of the MOSFET before the prescribed gate voltage is fully applied, as a result of which the operating characteristics of the MOSFET deteriorate. Such deterioration is more apparent with the higher DIBL value, especially with the shorter channel length.

FIG. 4A and 4B show extrapolated threshold values V _text of the new or the old MOSFETs. On the other hand, FIG. 6 shows a diagram for explaining the relationship between gate length and threshold voltage. As can be seen from FIG. 6, a threshold voltage of approximately 0.913 V is maintained at a gate length of not less than 2 μm. With a gate length of less than 2 µm, the threshold voltage decreases in proportion to the gate length. This means that the threshold voltage also decreases as the gate length decreases. This is due to the fact that different short channel effects are caused by the reduction in the gate length. This appearance is more pronounced with a shorter gate length.

However, such a threshold voltage should be independent of change in gate length.

From Fig. 4A and 4B it is seen that with a reduction of the channel length to 0.5 microns, the threshold voltage in the case of n-MOSFETs that microns with a large channel length of more than 0.5 is equal to 0.913 V, the new MOSFET 0.636 V and decreases to 0.533 V for the old MOSFET. Accordingly, the new MOSFET apparently has better threshold voltage characteristics than the old MOSFET.

In Fig. 5A and 5B currents on the other hand shown, NaEM Lich by the substrates of the new and the old MOSFETs flowing hole currents.

When the drain voltage increases, they move out from a source region into a drain region tron due to a strong electric field with very ho speed towards the drain area. The meet Electrons near the drain area on a lattice and cause the generation of defect electrons by impact ionization trons and electrons in the lattice area. In this case, kick the electrons into the drain area. The defect electrons however, are trapped or pas in the gate insulating layer the gate insulation layer. The electrons that pass through pass through the gate insulation layer, enter the gate  Electrode or flow to the substrate. The first of the three The above cases are a cause of the deterioration tion of the MOSFET characteristic. In reality, however, it is impossible to get the amount captured in the gate insulation layer to calculate the defect electrons directly. Instead it will the strength of the current flowing to the substrate is calculated. The means, assuming that the amount of in the gate iso Defect electrons trapped in proportion to Amount of the defect electrons flowing to the substrate is caused by hot charge carriers (i.e. defect electrons) gentle deterioration of the MOSFET from the strength of the Current flowing substrate determined.

This deterioration of the MOSFET caused by hot charge carriers can be reduced by the following three methods:
First, by reducing the generation of defect electrons due to impact ionization;
secondly, by avoiding that the defect electrons produced flow away to the gate insulating layer; and
thirdly, by avoiding that the defect electrons flowing off to the gate insulating layer are trapped in this layer.

According to the present invention, a decrease in De Electron generation achieved by the electric field strength near the drain area is reduced. This The procedure corresponds to the first of the cases mentioned above.

From Fig. 5A and 5B it can be seen that the strength of the current flowing to the sub strat current I _sub in the new MOSFET is lower than in the old MOSFET. The maximum substrate _current I _sub.max in the old MOSFET is 4.93 · 10 ^-6 A / µm at a gate voltage V _G of 2.0 V. On the other hand, the maximum substrate _current I _sub.max in the new MOSFET is 9.13 · 10 ^-7 A / µm at a gate voltage V _G of 1.8 V. This shows that the maximum substrate current in the new MOSFET is only about 20% compared to the old MOSFET.

FIGS. 7A and 7B show potential profiles of substrate surfaces of the new and the old MOSFETs. These potential profiles correspond to drain voltages of the MOSFETs of 0.5 V or 3.3 V. Such a potential profile is related to the DIBL value. With a higher DIBL value, the potential drop widths d and d ′ increase and thereby cause an increase in the leakage current before the MOSFET is switched on. As a result, the MOSFET can turn on early before the prescribed gate bias is applied, so that a malfunction can occur.

From Fig. 7A and 7B it can be seen that the new MOSFET having a ge ringere potential drop width than the old MOSFET.

The four measurements mentioned above can be used to determine that the new MOSFET according to the invention compared to the old one MOSFET gives better results.

Claims (12)

1. A method for producing a metal oxide semiconductor field effect transistor with the following steps:
Forming a gate ( 2 , 3 , 4 ) on a semiconductor substrate ( 1 ) of a first conductivity type;
Formation of a thin insulating layer ( 5 ) and a semiconductor layer ( 6 ) on the entire exposed surface;
Etching the thin insulating layer ( 5 ) and the semiconductor layer ( 6 ) so that they are retained only on the side faces of the gate to form the gate side walls ( 7 );
Implanting impurities of a second conductivity type in the semiconductor substrate ( 1 ) using the gate side walls ( 7 ) and the gate ( 4 ) as a mask to a first source / drain region ( 8 , 8 a) with a predetermined impurity concentration form;
Removing part of the semiconductor layer ( 6 a), which corresponds to the upper part of each gate side wall ( 7 ), and implanting impurities of the second conductivity type in the semiconductor substrate ( 1 ) using the remaining thin insulating layer ( 5 a) and the gate ( 4 ) as a mask to form a second source / drain region ( 9 , 9 a) with a predetermined impurity concentration; and
Removing the remaining thin insulating layer ( 5 a) and Im planting impurities of the second conductivity type in the semiconductor substrate ( 1 ) using the gate ( 4 ) alone as a mask with a third source / drain region ( 10 , 10 a) to form a predetermined impurity concentration. 2. The method according to claim 1 for producing a metal oxide semiconductor field effect transistor, characterized in that the first to third source / drain region ( 8 , 8 a- 10 , 10 a) have different impurity concentrations, such that the first source / drain Region ( 8 , 8 a) or the third source / drain region ( 10 , 10 a) have the largest or the smallest impurity concentration. 3. The method according to claim 1 for producing a metal oxide semiconductor field effect transistor, characterized in that the thin insulating layer ( 5 ) is thin enough to allow the diffusion of impurity ions. 4. The method according to claim 3 for producing a metal oxide semiconductor field effect transistor, characterized in that the thin insulating layer ( 5 ) consists of silicon nitride. 5. The method according to claim 1 for producing a metal oxide semiconductor field effect transistor, characterized in that the semiconductor layer ( 6 ) is made of undoped polysilicon be. 6. The method according to claim 1 for producing a metal oxide semiconductor field effect transistor, characterized in that the semiconductor layer ( 6 ) has a second insulating layer with a different etching selectivity than that of the thin insulating layer ( 5 ). 7. The method according to claim 6 for the production of a metal oxide Semiconductor field effect transistor, characterized in that the second insulating layer consists of silicon dioxide. 8. The method according to claim 1 for producing a metal oxide semiconductor field effect transistor, characterized in that the step of etching the thin insulating layer ( 5 ) and the semiconductor layer ( 6 ) is an anisotropic dry etching. 9. The method according to claim 8 for the production of a metal oxide Semiconductor field effect transistor, characterized in that the anisotropic dry etching process is a reactive ion etching is. 10. The method according to claim 1 for the production of a metal oxide semiconductor field effect transistor, characterized in that the gate ( 2 , 3 , 4 ) a gate insulating layer ( 2 ), a gate electrode ( 3 ) and a gate cap insulating layer ( 4 ) has, which are formed in this order. 11. The method according to claim 10 for producing a metal oxide semiconductor field effect transistor, characterized in that the gate insulating layer ( 2 ) and the gate cap insulating layer ( 4 ) consist of silicon dioxide and the gate electrode ( 3 ) consists of polysilicon, which is doped with impurities of a given conductivity type. 12. Metal oxide semiconductor field effect transistor, can be produced with a method according to one of claims 1 to 11.