KR920018877A - n and p method - Google Patents

n and p method Download PDF

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Publication number
KR920018877A
KR920018877A KR1019910004048A KR910004048A KR920018877A KR 920018877 A KR920018877 A KR 920018877A KR 1019910004048 A KR1019910004048 A KR 1019910004048A KR 910004048 A KR910004048 A KR 910004048A KR 920018877 A KR920018877 A KR 920018877A
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KR
South Korea
Prior art keywords
forming
oxide film
gate
region
ion implantation
Prior art date
Application number
KR1019910004048A
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Korean (ko)
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KR930007973B1 (en
Inventor
이혁재
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019910004048A priority Critical patent/KR930007973B1/en
Publication of KR920018877A publication Critical patent/KR920018877A/en
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Publication of KR930007973B1 publication Critical patent/KR930007973B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

내용 없음No content

Description

n 및 P모스패트 제조방법n and P method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 공정단면도.2 is a cross-sectional view of the process of the present invention.

Claims (2)

p형기판(1)위에 초기산화막(2), 질화막(3)을 형성하여 필드부분의 질화막을 제거하고 이온주입으로 채널스톱영역(4)형성 후 필드산화막(5)을 형성하는 고정과, 상기 질화막(3)과 초기산화막(2) 제거후 게이트 산화막(6), 폴리게이트(7), 캡 LTO(8)를 형성하여 폴리게이트(7)와 캡LTO(8)를 식각함으로 게이트를 형성하는 공정과, 상기 필드 산화막(5)의 소정부분을 식각하여 소오스와 드레인 영역을 형성하고 n-이온주입으로 n-영역(9)을 형성하는 공정과, 상기 게이트에 측벽(10)형성후 n+이온주입으로 n+영역(11)을 형성하는 공정과, 통상의 공정으로 절연막(12)과 메탈(13)을 형성하는 공정을 차례로 실시하여서 이루어짐을 특징으로 하는 n모스패트 제조방법.fixing an initial oxide film 2 and a nitride film 3 on the p-type substrate 1 to remove the nitride film of the field portion and forming the field oxide film 5 after the channel stop region 4 is formed by ion implantation; After removing the nitride film 3 and the initial oxide film 2, the gate oxide film 6, the polygate 7, and the cap LTO 8 are formed to form a gate by etching the polygate 7 and the cap LTO 8. Forming a source and a drain region by etching a predetermined portion of the field oxide film 5 and forming an n − region 9 by n − ion implantation ; A process for forming an n + region (11) by ion implantation, followed by a step of forming an insulating film (12) and a metal (13) in a normal process, in an order. n-웰(14)위에 초기산화막(2), 질화막(3)을 형성하여 필드부분의 질화막을 제거하고 이온주입으로 채널스톱영역(4)형성후 필드산화막(5)을 형성하는 공정과, 상기 질화막(3), 초기산화막(2)제거후 게이트 산화막(6), 폴리게이트(7), 캡LTO(8)를 형성하여 폴리게이트(7)와 캡LTO(8)를 식각함으로 게이트를 형성하는 공정과, 상기 필드산하막(5)의 소정부분을 식각하여 소오스와 드레인 영역을 형성하고 p-이온주입으로 p-영역(15)을 형성하는 공정과, 상기 게이트에 측벽(10)형성후 p+이온주입으로 p+영역(16)을 형성하는 공정과, 통상의 공정으로 절연막(12)과 메탈(13)을 형성하는 공정과 차례로 실시하여서 이루어짐을 특징으로 하는 p모스패트 제조방법.forming an initial oxide film (2) and a nitride film (3) on the n-well (14) to remove the nitride film in the field portion, and forming the field oxide film (5) after the channel stop region (4) is formed by ion implantation; After the nitride film 3 and the initial oxide film 2 are removed, the gate oxide film 6, the poly gate 7, and the cap LTO 8 are formed to form a gate by etching the poly gate 7 and the cap LTO 8. Forming a source and a drain region by etching a predetermined portion of the field underlayer 5, and forming a p − region 15 by p − ion implantation, and after forming the sidewall 10 in the gate, p + Forming a p + region (16) by ion implantation, and forming an insulating film (12) and a metal (13) in a conventional process, and sequentially. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910004048A 1991-03-14 1991-03-14 Manufacturing method of metal-oxide-silicon field effect transistor KR930007973B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910004048A KR930007973B1 (en) 1991-03-14 1991-03-14 Manufacturing method of metal-oxide-silicon field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910004048A KR930007973B1 (en) 1991-03-14 1991-03-14 Manufacturing method of metal-oxide-silicon field effect transistor

Publications (2)

Publication Number Publication Date
KR920018877A true KR920018877A (en) 1992-10-22
KR930007973B1 KR930007973B1 (en) 1993-08-25

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ID=19312077

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910004048A KR930007973B1 (en) 1991-03-14 1991-03-14 Manufacturing method of metal-oxide-silicon field effect transistor

Country Status (1)

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KR (1) KR930007973B1 (en)

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Publication number Publication date
KR930007973B1 (en) 1993-08-25

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