KR940008126A

KR940008126A - Gate manufacturing method of MOS transistor

Info

Publication number: KR940008126A
Application number: KR1019920017447A
Authority: KR
Inventors: 왕성호
Original assignee: 문정환; 금성일렉트론 주식회사
Priority date: 1992-09-24
Filing date: 1992-09-24
Publication date: 1994-04-28

Abstract

본 발명은 게이트 형성시 측벽에 폴리 실리콘의 잔여물을 남게하여 쇼트 채널 효과감소 및 스텝커버리지(STEPCOVERAGE)감소에 적당하도록 한 MOS 트랜지스터의 게이트 제조방법에 관한 것으로서, 기간에 필드 산화막, 게이트 산화막이 형성되는 MOS트랜지스터 게이트 제조 방법에 있어서, 상기 게이트 산화막 위에 게이트 폴리실리콘과 캡 게이트 옥사이드를 차례로 정착하고, 게이트가 형성될 위치에 포토레지스트를 도포하여 게이트를 정의하고, 상기 단계 후 도프드 폴리 실리콘을 소정 두께로 증착 한 다음 그 상태에서 도프드 폴리실리콘을 에치백하여 게이트의 측벽에 폴리실리콘의 잔여물이 남게 한 후 사이드 월용 옥사이드를 증착하고, 상기 사이드 월용 옥사이드를 에치백하여 사이드월을 형성한 다음 N⁺이온을 주입하여 소스/드레인 영역을 형성하는 단계로 이루어진 MOS트랜지스터의 게이트 제조공정으로 되어 쇼트 채널 효과감소 및 스텝커버리지(STEPCOVERAGE)감소할 수있는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate of a MOS transistor in which a residue of polysilicon remains on sidewalls during gate formation, which is suitable for short channel effect reduction and step coverage (STEPCOVERAGE), wherein a field oxide film and a gate oxide film are formed in a period. In the method of manufacturing a MOS transistor gate, a gate polysilicon and a cap gate oxide is fixed on the gate oxide film in sequence, a photoresist is applied to the position where the gate is to be formed to define a gate, and then the doped polysilicon is defined after the step. After deposition in thickness, the doped polysilicon is etched in such a state that a residue of polysilicon remains on the sidewall of the gate, and then the oxide for sidewall is deposited, and the sidewall oxide is etched back to form a sidewall. Implanting N ⁺ ions to form source / drain regions MOS transistor is a gate manufacturing process consisting of a step can reduce the short channel effect and step coverage (STEPCOVERAGE).

Description

Gate manufacturing method of MOS transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 MOS트랜지스터 게이트 제조 공정도.2 is a process diagram of manufacturing a MOS transistor gate according to the present invention.

Claims

In the method of manufacturing a MOS transistor gate in which a field oxide film and a gate oxide film are formed on a substrate, a gate polysilicon and a cap gate oxide are sequentially deposited on the gate oxide film, and a photoresist is applied to a position where the gate is to be formed to define a gate. After the step, the doped polysilicon is deposited to a predetermined thickness, and then in the state, the doped polysilicon is etched back so that a residue of polysilicon remains on the sidewall of the gate, and then the sidewall oxide is deposited, and the sidewall oxide is deposited. A method of manufacturing a gate of a MOS transistor, comprising: forming a sidewall by etching back and implanting N ⁺ ions to form a source / drain region.

※ Note: The disclosure is based on the initial application.