KR930015111A - MOS transistor manufacturing method and structure - Google Patents
MOS transistor manufacturing method and structure Download PDFInfo
- Publication number
- KR930015111A KR930015111A KR1019910022604A KR910022604A KR930015111A KR 930015111 A KR930015111 A KR 930015111A KR 1019910022604 A KR1019910022604 A KR 1019910022604A KR 910022604 A KR910022604 A KR 910022604A KR 930015111 A KR930015111 A KR 930015111A
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- sidewall
- oxide film
- mos transistor
- region
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract 11
- 239000010703 silicon Substances 0.000 claims abstract 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract 10
- 229920005591 polysilicon Polymers 0.000 claims abstract 10
- 238000000407 epitaxy Methods 0.000 claims abstract 8
- 239000000758 substrate Substances 0.000 claims abstract 6
- 238000005530 etching Methods 0.000 claims abstract 4
- 238000000034 method Methods 0.000 claims abstract 3
- 238000000151 deposition Methods 0.000 claims abstract 2
- 238000005468 ion implantation Methods 0.000 claims abstract 2
- 230000000694 effects Effects 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 MOS 트랜지스터 제조방법 및 그 구조에 관한 것으로, 특히 채널영역에서 항복전압을 감소시키며, 핫 캐리어(Hot Carrier) 효과 및 솟 채널(Short-Chanel) 효과를 감소시키는데 적당하도록 LDD(Lightly Doped Drain) 영역을 형성시키는 방법 및 그 구조에 관한 것이다. 이를 위하여 본 발명에서는, MOS 트랜지스터 제조 방법에 있어서, 실리콘 기판에 필드 산화막을 형성하고 게이트산화막, 게이트 폴리 실리콘 및 상기 게이트 폴리실리콘 보호용 CVD 산화막을 차례로 형성하고 게이트를 정의하는 단계(a)와, 게이트 측벽과 후에 형성될 실리콘 에피택시 LDD영역을 격리시키기 위한 게이트 측벽 산화막을 얇게 형성한 후 에치백하여 제1사이드월을 남는 단계(b)와, 실리콘 에피택시에 의해 LDD영역을 형성하는 단계(c)와, 게이트 폴리실리콘의 측벽을 보호하기 위해 산화막을 증착한 다음 에치백하여 제2사이드월을 남기는 단계(d)와, 소스/드레인 영역을 형성하기 위해 소스/드레인 이온 주입 공정을 실시하는 단계(e)를 포함하는 것을 특징으로 하는 MOS트랜지스터 제조방법과, 실리콘 기판의 액티브 영역에 게이트가 형성되고 게이트 측면에는 게이트 폴리실리콘과 나중에 형성될 실리콘 에피택시 LDD 영역을 격리시키기 위한 제1사이드월이 형성되어 있고, 게이트 및 제1사이드월 바깥의 액티브 영역상에는 실리콘 에피택시 LDD영역에 형성되고, 제1사이드월 외부에는 게이트 폴리실리콘 보호용 제2사이드 월이 형성되며, 제2사이드 월 바깥의 기판 밑으로는 소스/드레인 영역이 형성되는 것을 특징으로 하는 MOS트랜지스터 구조.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a MOS transistor and its structure, in particular to reducing the breakdown voltage in the channel region and to suitably reducing the Hot Carrier effect and the Short-Chanel effect. ) And a structure thereof. To this end, in the present invention, in the method of manufacturing a MOS transistor, (a) forming a field oxide film on a silicon substrate, forming a gate oxide film, a gate polysilicon, and a CVD oxide film for protecting the gate polysilicon, and defining a gate; (B) forming a thin gate sidewall oxide film for isolating the sidewalls and the silicon epitaxy LDD region to be formed later and etching back to leave the first sidewall, and forming the LDD region by silicon epitaxy (c) (D) depositing an oxide film to protect the sidewalls of the gate polysilicon and then etching back to leave a second sidewall, and performing a source / drain ion implantation process to form a source / drain region. and a method of manufacturing a MOS transistor, the gate being formed in an active region of a silicon substrate. A first sidewall is formed on the side of the gate to isolate the gate polysilicon and the silicon epitaxy LDD region to be formed later, and is formed in the silicon epitaxy LDD region on the active region outside the gate and the first sidewall. A second side wall for protecting the gate polysilicon is formed outside the sidewall, and a source / drain region is formed under the substrate outside the second sidewall.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2도는 본 발명의 MOS 트랜지스터 제조 공정도.2 is a MOS transistor manufacturing process diagram of the present invention.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910022604A KR100221608B1 (en) | 1991-12-11 | 1991-12-11 | Manufacturing method of mos transistors and the structures thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910022604A KR100221608B1 (en) | 1991-12-11 | 1991-12-11 | Manufacturing method of mos transistors and the structures thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR930015111A true KR930015111A (en) | 1993-07-23 |
| KR100221608B1 KR100221608B1 (en) | 1999-09-15 |
Family
ID=19324513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910022604A KR100221608B1 (en) | 1991-12-11 | 1991-12-11 | Manufacturing method of mos transistors and the structures thereof |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100221608B1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100632465B1 (en) | 2005-07-26 | 2006-10-09 | 삼성전자주식회사 | Semiconductor device and fabrication method thereof |
| KR100834741B1 (en) | 2006-07-26 | 2008-06-05 | 삼성전자주식회사 | Semiconductor device and fabrication method thereof |
-
1991
- 1991-12-11 KR KR1019910022604A patent/KR100221608B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100221608B1 (en) | 1999-09-15 |
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