KR910016099A - Dual gate transistor manufacturing method - Google Patents

Dual gate transistor manufacturing method Download PDF

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Publication number
KR910016099A
KR910016099A KR1019900002344A KR900002344A KR910016099A KR 910016099 A KR910016099 A KR 910016099A KR 1019900002344 A KR1019900002344 A KR 1019900002344A KR 900002344 A KR900002344 A KR 900002344A KR 910016099 A KR910016099 A KR 910016099A
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KR
South Korea
Prior art keywords
source
drain
gate
completion
oxide film
Prior art date
Application number
KR1019900002344A
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Korean (ko)
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KR930008534B1 (en
Inventor
라사균
이영종
김동원
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019900002344A priority Critical patent/KR930008534B1/en
Publication of KR910016099A publication Critical patent/KR910016099A/en
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Publication of KR930008534B1 publication Critical patent/KR930008534B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

Abstract

내용 없음No content

Description

듀얼게이트 트랜지스터 제조방법Dual gate transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도는 본 발명에 따른 듀얼게이트 트랜지스터 제조공정도.FIG. 2 is a process for manufacturing a dual gate transistor according to the present invention. FIG.

Claims (1)

실리콘 기판(1)위에 필드산화막(3)과 게이트산화막(4)을 형성한 다음 게이트 산화막(4)위에 폴리실리콘(다결정 실리콘)(5)을 증착시키고 그위에 묽은 질화물(11)을 증착시키는 공정과, 상기 공정완료후 마스킹 작업 및 에칭작업과 포토레지스트 제거작업을 수행하여 묽은 질화물층(11)을 갖는 게이트(5a)를 형성하는 공정과, 상기 공정완료후 LDD효과를 위한 N_소오스/드레인(7) 이온을 주입하고 LTO증착 및 에칭 작업을 수행하여 사이드올(8)을 형성하는 공정과, 상기 공정 완료후 셀렉티브 산화작업을 수행하므로서 묽은 질화물층(11)을 갖는 게이트는 지역은 산화되지 않고 소오스/드레인 지역에만 산화막(12)을 키워 두께에 차등을 가지는 버퍼층을 형성하는 공정과, N_소오스/드레인 이온주입을 위한 마스킹 작업을 하고 N_소오스/드레인 이온을 주입한 다음 포토레지스트(6)를 제거하는 공정과, 상기 공정 완료후 P+소오스/드레인 이온주입을 위한 마스킹 작업을 하고 P+소오스/드레인 이온을 주입한 다음 포토레지스트(6)를 제거하는 공정과, 상기 공정 완료후 소오스/드레인 정션 및 게이트 폴리실리콘이 전도성을 가지도록 어니얼링 작업을 수행하는 공정을 거쳐 듀얼게이트 트랜지스터를 제조하는 것을 특징으로 하는 듀얼게이트 트랜지스터 제조방법.A process in which a field oxide film 3 and a gate oxide film 4 are formed on a silicon substrate 1 and then a polysilicon film 5 is deposited on the gate oxide film 4 and a dilute nitride film 11 is deposited thereon and, after completion of the process, masking and etching operation the picture by removing the resist to perform the action of dilute nitride layer N _ source / drain for a gate (5a) step and, after completion of the process LDD effective to form a having a 11 (7) ion implantation and LTO deposition and etching to form the side ol 8; and performing a selective oxidation operation after the completion of the process, the gate having the dilute nitride layer 11 is oxidized without the source / a step of forming a buffer layer having a differential drain oxide film 12 only on a raised area and thickness, masking operation for N _ source / drain ion implantation, and the implanted N _ source / drain ion and then Removing the photoresist 6, performing a masking operation for P + source / drain ion implantation after the process, injecting P + source / drain ions and removing the photoresist 6, Wherein the dual gate transistor is fabricated through a process of performing an annealing operation so that the source / drain junction and the gate polysilicon have conductivity after completion of the process. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019900002344A 1990-02-23 1990-02-23 Manufacturing method of dual-gate transistor KR930008534B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900002344A KR930008534B1 (en) 1990-02-23 1990-02-23 Manufacturing method of dual-gate transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900002344A KR930008534B1 (en) 1990-02-23 1990-02-23 Manufacturing method of dual-gate transistor

Publications (2)

Publication Number Publication Date
KR910016099A true KR910016099A (en) 1991-09-30
KR930008534B1 KR930008534B1 (en) 1993-09-09

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Application Number Title Priority Date Filing Date
KR1019900002344A KR930008534B1 (en) 1990-02-23 1990-02-23 Manufacturing method of dual-gate transistor

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Publication number Publication date
KR930008534B1 (en) 1993-09-09

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