KR960002882A - MOS transistor manufacturing method - Google Patents

MOS transistor manufacturing method Download PDF

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Publication number
KR960002882A
KR960002882A KR1019940012860A KR19940012860A KR960002882A KR 960002882 A KR960002882 A KR 960002882A KR 1019940012860 A KR1019940012860 A KR 1019940012860A KR 19940012860 A KR19940012860 A KR 19940012860A KR 960002882 A KR960002882 A KR 960002882A
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KR
South Korea
Prior art keywords
forming
mos transistor
photosensitive agent
substrate
etching
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Application number
KR1019940012860A
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Korean (ko)
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KR0139655B1 (en
Inventor
황이연
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019940012860A priority Critical patent/KR0139655B1/en
Publication of KR960002882A publication Critical patent/KR960002882A/en
Application granted granted Critical
Publication of KR0139655B1 publication Critical patent/KR0139655B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 모스 트랜지스터 제조방법에 관한 것으로, 종래 모스 트랜지스터는 채널의 유효길이가 짧아 펀치스로우가 발생하는 문제점이 있었다. 본 발명은 이러한 문제점을 해결하기 위하여 실리콘기판을 비등방성식각(Anisotropic Etch)하여 게이트모양을 단면(Verticaly)상 샤프(Shape)한 모양이 되도록 함으로써 채널길이를 확대시켜 쇼트 채널 효과를 방지토록 하는 모스 트랜지스터 제조방법을 제공하는 것이다.The present invention relates to a MOS transistor manufacturing method, the conventional MOS transistor has a problem that the punch throw occurs because the effective length of the channel is short. In order to solve this problem, the present invention is an anisotropically etched silicon substrate so that the gate shape becomes a sharp shape on the cross-section, thereby increasing the channel length to prevent short channel effects. It is to provide a transistor manufacturing method.

Description

모스 트랜지스터 제조방법MOS transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도의 (a) 내지 (d)는 종래 모스 트랜지스터의 제조공정도.(A)-(d) of FIG. 1 is a manufacturing process diagram of a conventional MOS transistor.

제2도는 모스 트랜지스터에 있어, 글로브구조(a,b)와 플라나구조(c)의 게이트비교도.2 is a gate comparison diagram of a globe structure (a, b) and a planar structure (c) in a MOS transistor.

제3도는 제2도에 따른 채널길이 대 문턱전압 특성도.3 is a channel length versus threshold voltage characteristic diagram according to FIG. 2;

제4도는 본 발명 모스 트랜지스터의 단면구조도.4 is a cross-sectional view of a MOS transistor of the present invention.

제5도의 (a) 내지 (f)는 본 발명에 모스 트랜지스터의 제조공정도.(A)-(f) of FIG. 5 is a manufacturing process diagram of a MOS transistor in this invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

11:실리콘기판12,15:SiO2층11: Silicon substrate 12, 15: SiO 2 layer

13,17:감광막14:n-영역13:17 photosensitive film 14: n-region

16:게이트전극18:채널스토퍼16: gate electrode 18: channel stopper

19:소오스/드레인19: source / drain

Claims (5)

실리콘기판상에 게이트영역을 정의하는 공정과, 정의된 게이트영역에 제1감광제를 사용하여 제1산화막패턴을 형성하는 공정과, 저농도불순물(n-)을 이온주입하여 상기 실리콘기판내에 n-영역을 형성하는 공정과, 제1감광제를 제거하고 기판을 식각하는 공정과, 제1산화막을 제거하는 공정과, 제1산화막과 폴리실리콘을 연속으로 형성하는 공정과, 제2감광제를 게이트 영역 이외의 부분에 형성하는 공정과, 불순물을 주입하여 펀치스로우 방지를 위한 채널스토퍼를 형성하는 공정과, 제2감광제를 제거하고 게이트 전극을 형성하는 공정과, 고농도불순물(n+)을 주입하여 소오스/드레인을 형성하는 공정으로 이루어지는 것을 특징으로 하는 모스 트랜지스터 제조방법.A process of defining a gate region on a silicon substrate, a process of forming a first oxide film pattern using a first photosensitive agent in a defined gate region, and an n − region in the silicon substrate by ion implantation of low concentration impurity (n − ). Forming a film, removing the first photosensitive agent and etching the substrate, removing the first oxide film, forming the first oxide film and polysilicon continuously, and forming the second photosensitive agent in the non-gate region. Forming a portion of the portion, forming a channel stopper for preventing punch throw by injecting impurities, removing a second photoresist and forming a gate electrode, and injecting a high concentration impurity (n + ) to inject a source / drain A MOS transistor manufacturing method comprising the step of forming a. 제1항에 있어서, 기판을 식각하는 공정은 비등방성 식각(Anisotropic Etch)이 사용됨을 특징으로 하는 모스 트랜지스터 제조방법.The method of claim 1, wherein the etching of the substrate is performed using anisotropic etching. 제1항 또는 제2항에 있어서, 기판의 식각량은 상기 n-영역이 최소한의 정션깊이가 되도록 식각하는 것을 특징으로 하는 모스 트랜지스터 제조방법.The method of claim 1, wherein the etching amount of the substrate is etched so that the n − region has a minimum junction depth. 제1항에 있어서, 제2감광제는 네가티브 감광제(Negative Photo Rssist)가 사용됨을 특징으로 하는 모스 트랜지스터 제조방법.The method of claim 1, wherein the second photosensitive agent is a negative photoresist. 제1항에 있어서, 채널스토퍼 형성을 위한 불순물은 보론(Boron)인 것을 특징으로 하는 모스 트랜지스터 제조방법.The method of claim 1, wherein the impurity for forming the channel stopper is boron. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940012860A 1994-06-08 1994-06-08 Mos transistor KR0139655B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940012860A KR0139655B1 (en) 1994-06-08 1994-06-08 Mos transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940012860A KR0139655B1 (en) 1994-06-08 1994-06-08 Mos transistor

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KR960002882A true KR960002882A (en) 1996-01-26
KR0139655B1 KR0139655B1 (en) 1998-06-01

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KR1019940012860A KR0139655B1 (en) 1994-06-08 1994-06-08 Mos transistor

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476466B1 (en) * 2001-07-24 2005-03-17 주식회사 코오롱 A process of preparing the alkali extractable polyester

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476466B1 (en) * 2001-07-24 2005-03-17 주식회사 코오롱 A process of preparing the alkali extractable polyester

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KR0139655B1 (en) 1998-06-01

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