KR910017667A - How to prevent channeling in LDD - Google Patents

How to prevent channeling in LDD Download PDF

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Publication number
KR910017667A
KR910017667A KR1019900002819A KR900002819A KR910017667A KR 910017667 A KR910017667 A KR 910017667A KR 1019900002819 A KR1019900002819 A KR 1019900002819A KR 900002819 A KR900002819 A KR 900002819A KR 910017667 A KR910017667 A KR 910017667A
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KR
South Korea
Prior art keywords
ldd
oxide film
forming
temperature oxidation
implanted
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KR1019900002819A
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Korean (ko)
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KR930008535B1 (en
Inventor
김기홍
송인일
송한정
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019900002819A priority Critical patent/KR930008535B1/en
Publication of KR910017667A publication Critical patent/KR910017667A/en
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Publication of KR930008535B1 publication Critical patent/KR930008535B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음No content

Description

LDD의 채널링 현상 방지 방법How to prevent channeling in LDD

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 2도 (가)~(라)는 채널링 현상에 관한 참조 설명도, 제 3도 (가)(나)는 제 1 도에서의 채널링 현상 방지 방법에 관한 참조 설명도, 제 4도 (가)(나)는 본 발명에 의한 LDD의 채널링 현상 방지 방법에 과한 제조공정도.2 (a) to (d) are reference explanatory diagrams for the channeling phenomenon, and FIG. 3 (a) (b) are reference explanatory diagrams for the method of preventing channeling phenomenon in FIG. (B) is a manufacturing process drawing over the LDD channeling prevention method by this invention.

Claims (1)

P-서브 스트레이트(1)의 위에 게이트 산화막(2)을 형성한 후 격자 배열이 일정하지 않은 다결정 실리콘(7)을 전면에 증착하고, 액체(POC13)를 이용하여 도우핑을 한후 추가로 무거운 이온(As,Pb등)을 주입하여 선-비정질하고, 게이트를 마스크로 형성한 후 에치하여 포토 레지스터를 형성하고 스트립하여 이온(N-)을 주입하고, 저온산화(LTO)또는 고온산화(HTO)에 의하여 산화막(3)을 형성한후 반응성 이온 식각(RIF)으로 사이드 월 스페이서를 수직식각으로 형성하고, 이온(N+)을 주입한후 불에 달구었다가 서서히 식혀서 강하게 하여 N 형 MOSFET의 소오스/드레인을 형성하여 LDD를 만드는 것을 포함하여 이루어진 것을 특징으로 하는 LDD의 채널링 현상 방지방법.After the gate oxide film 2 is formed on the P-sub-straight 1, polycrystalline silicon 7 having an irregular lattice arrangement is deposited on the front surface, and doped with a liquid POC13. (As, Pb, etc.) is implanted pre-amorphous, the gate is formed as a mask, then etched to form a photoresist and stripped to inject ions (N-), low temperature oxidation (LTO) or high temperature oxidation (HTO) After the oxide film 3 is formed, the sidewall spacers are vertically etched by reactive ion etching (RIF), the ions (N +) are implanted, then heated and slowly cooled to harden the source / type of the N-type MOSFET. Method for preventing the channeling phenomenon of the LDD comprising the step of forming an LDD by forming a drain. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900002819A 1990-03-05 1990-03-05 Method of protecting channeling for ldd KR930008535B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900002819A KR930008535B1 (en) 1990-03-05 1990-03-05 Method of protecting channeling for ldd

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900002819A KR930008535B1 (en) 1990-03-05 1990-03-05 Method of protecting channeling for ldd

Publications (2)

Publication Number Publication Date
KR910017667A true KR910017667A (en) 1991-11-05
KR930008535B1 KR930008535B1 (en) 1993-09-09

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Application Number Title Priority Date Filing Date
KR1019900002819A KR930008535B1 (en) 1990-03-05 1990-03-05 Method of protecting channeling for ldd

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102002991B1 (en) * 2012-08-30 2019-07-23 삼성전자주식회사 Method of forming an opening and method of manufacturing a semiconductor device using the same

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Publication number Publication date
KR930008535B1 (en) 1993-09-09

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