KR940008097A - Semiconductor memory cell manufacturing method with increased capacitor capacity - Google Patents

Semiconductor memory cell manufacturing method with increased capacitor capacity Download PDF

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Publication number
KR940008097A
KR940008097A KR1019920017520A KR920017520A KR940008097A KR 940008097 A KR940008097 A KR 940008097A KR 1019920017520 A KR1019920017520 A KR 1019920017520A KR 920017520 A KR920017520 A KR 920017520A KR 940008097 A KR940008097 A KR 940008097A
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KR
South Korea
Prior art keywords
memory cell
oxide film
cell manufacturing
semiconductor memory
capacitor capacity
Prior art date
Application number
KR1019920017520A
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Korean (ko)
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KR960009113B1 (en
Inventor
구본재
정문모
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR92017520A priority Critical patent/KR960009113B1/en
Publication of KR940008097A publication Critical patent/KR940008097A/en
Application granted granted Critical
Publication of KR960009113B1 publication Critical patent/KR960009113B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 하나의 트랜지스터와 하나의 캐패시터로 구성된 디램 메모리셀에서, 캐피시터의 구성을 개선하여 그용량을 증대시키는 신규의 메모리셀 제조방법을 제공하는데 있다.The present invention provides a novel memory cell manufacturing method for improving the capacity of a capacitor in a DRAM memory cell composed of one transistor and one capacitor, thereby increasing its capacity.

본 발명은 따른 메모리셀 제조방법의 특징을 셀안의 기둥과 셀의 하부를 캐패시터 영역으로 사용할 수 있도록 구성하여 전체적으로 용량을 중대한 것이다.According to the present invention, the capacity of the memory cell manufacturing method is significant so that the pillars in the cell and the lower part of the cell can be used as capacitor regions.

Description

캐패시터 용량을 증대한 반도체 메모리 셀 제조방법Semiconductor memory cell manufacturing method with increased capacitor capacity

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 디램의 제조 공정도.2 is a manufacturing process diagram of the DRAM according to the present invention.

Claims (1)

반도체 기판상에 필드영역(3)을 설정함으로서 한정된 활성영역내에 소오스/드레인 영역이 제공된 디램 메모리셀의 제조방법에 있어서, 상기 기판상에 게이트 영역과 비트라인(1)을 제공하는 단계와 상기 비트라인(1)상에 차례로 산화막(6), 질화막(7), 산화막(14) 및 산화막(10)을 형성하는 단계와 상기 산화막(10)표면에서 기판 표면까지 삭각하여 노드접촉부(15)를 형성하는 단계와 상기 플리실리콘노드(11)을 에치백하고 산화막(10)을 제거하는 단계를 구비한 것을 특징으로하는 디램 메모리셀 제조방법.A method of manufacturing a DRAM memory cell in which source / drain regions are provided in a defined active region by setting a field region 3 on a semiconductor substrate, the method comprising: providing a gate region and a bit line 1 on the substrate and the bit; Forming an oxide film 6, a nitride film 7, an oxide film 14, and an oxide film 10 on the line 1, and cutting the surface of the oxide film 10 from the surface of the oxide film 10 to form a node contact portion 15. And etching the polysilicon node (11) and removing the oxide film (10). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR92017520A 1992-09-25 1992-09-25 Method for forming node electrode of capacitor KR960009113B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR92017520A KR960009113B1 (en) 1992-09-25 1992-09-25 Method for forming node electrode of capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR92017520A KR960009113B1 (en) 1992-09-25 1992-09-25 Method for forming node electrode of capacitor

Publications (2)

Publication Number Publication Date
KR940008097A true KR940008097A (en) 1994-04-28
KR960009113B1 KR960009113B1 (en) 1996-07-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR92017520A KR960009113B1 (en) 1992-09-25 1992-09-25 Method for forming node electrode of capacitor

Country Status (1)

Country Link
KR (1) KR960009113B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100546196B1 (en) * 1998-12-30 2006-04-06 주식회사 하이닉스반도체 Repair device using latch

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3799287B2 (en) 2002-04-03 2006-07-19 Ｎｅｃ液晶テクノロジー株式会社 Evaluation method of liquid crystal display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100546196B1 (en) * 1998-12-30 2006-04-06 주식회사 하이닉스반도체 Repair device using latch

Also Published As

Publication number Publication date
KR960009113B1 (en) 1996-07-10

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