KR950004547A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR950004547A
KR950004547A KR1019930013794A KR930013794A KR950004547A KR 950004547 A KR950004547 A KR 950004547A KR 1019930013794 A KR1019930013794 A KR 1019930013794A KR 930013794 A KR930013794 A KR 930013794A KR 950004547 A KR950004547 A KR 950004547A
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KR
South Korea
Prior art keywords
forming
electrode
region
capacitor
conductive layer
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KR1019930013794A
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Korean (ko)
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KR960015525B1 (en
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곽종석
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문정환
금성일렉트론 주식회사
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Priority to KR1019930013794A priority Critical patent/KR960015525B1/en
Publication of KR950004547A publication Critical patent/KR950004547A/en
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Publication of KR960015525B1 publication Critical patent/KR960015525B1/en

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices

Abstract

본 발명은 반도체 소자의 제조방법에 관한 것으로서, 특히 메모리 소자인 디램(DRAM)에서의 메모리 용량을 증대시키기 위해 제한된 면적내에서 캐패시터 용량을 극대화하도록 한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a capacitor capacity is maximized within a limited area in order to increase a memory capacity of a memory device, a DRAM.

이를 위하여 반도체 기판위에 활성 영역과 격리 영역을 정의하고, 상기 격리 영역에 소자격리용 필드 격리막을 형성하고,상기 활성영역에 게이트 절연막, 게이트 전극, 불순물 영역을 차례로 형성하여 트랜지스터를 형성하는 단계와, 상기 격리 영역과 불순물 영역 사이에 소정 깊이 및 폭을 갖는 트랜치를 형성하는 단계와, 상기 트랜치 영역에 불순물 영역과 접하는 부분을 제외한 나머지 부분에 제 1 절연막을 형성하는 단계와, 상기 제 1 절연막 위에 캐패시터 제 1 전극의 제 1 전도층을 형성하는 단계와, 상기 캐패시터 제 1 전극의 제 1 전도층위에 불순물 영역과 접하는 부분을 제외한 나머지 부분에 제 2 절연막을 형성하는 단계와, 상기 제 2 절연막위에 캐패시터의 제 2 전극을 형성하는 단계와, 상기 캐패시터의 제 2 전극위에 제 3 절연막을 형성하는 단계와, 상기 제 3 절연막과 제 1 전도층위에 제 2 전도층을 형성시켜 제 1 전극을 형성하는 단계로 이루어진 것이다.To this end, defining an active region and an isolation region on a semiconductor substrate, forming a field isolation layer for isolation of the device in the isolation region, and forming a transistor by sequentially forming a gate insulating film, a gate electrode, and an impurity region in the active region; Forming a trench having a predetermined depth and width between the isolation region and the impurity region, forming a first insulating layer in the trench region except for a portion in contact with the impurity region, and forming a capacitor on the first insulating layer Forming a first conductive layer of a first electrode, forming a second insulating film over the first conductive layer of the capacitor first electrode except for a portion contacting the impurity region, and forming a capacitor on the second insulating film Forming a second electrode of the capacitor and forming a third insulating film on the second electrode of the capacitor And forming a first electrode by forming a second conductive layer on the third insulating film and the first conductive layer.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 반도체 소자의 제조 공정도.2 is a manufacturing process diagram of a semiconductor device according to the present invention.

Claims (4)

반도체 기판위에 활성 영역과 격리 영역을 정의하고, 상기 격리 영역에 소자격리용 필드 격리막(12)을 형성하고, 상기 활성 영역에 게이트 절연막(13), 게이트 전극(14), 불순물 영역(15)(15')을 형성하여 트랜지스터를 형성하는 단계, 상기 격리 영역과 불순물 영역(15) 사이에 소정 깊이 및 폭을 갖는 트랜치를 형성하는 단계, 상기 트랜치 영역에 불순물 영역(15)과 접하는 부분을 제외한 나머지 부분에 제1절연막(16)을 형성하는 단계, 상기 제1절연막위에 캐패시터 제1전극의 제1전도층(17)을 형성하는 단계, 상기 캐패시터 제1전극의 제1전도층(17)위에 불순물 영역(15)과 접하는 부분을 제외한 나머지 부분에 제2절연막(18)을 형성하는 단계, 상기 제2절연막(18)위에 캐패시터의 제2전극(19)을 형성하는단계, 상기 캐패시터의 제2전극(19)위에 제3절연막(20)을 형성하는 단계, 상기 제3절연막(20)을 형성하는 단계, 상기 제3절연막(20)과 제1전도층(21)위에 제2전도층을 형성시켜 제1전극(22)을 형성하는 단계를 포함하여 이루어지는 반도체 소자의 제조방법.An active region and an isolation region are defined on the semiconductor substrate, and a field isolation film 12 for isolation of the device is formed in the isolation region, and a gate insulating layer 13, a gate electrode 14, and an impurity region 15 ( 15 ') to form a transistor, forming a trench having a predetermined depth and width between the isolation region and the impurity region 15, except for the portion in contact with the impurity region 15 in the trench region. Forming a first insulating layer 16 on the portion, forming a first conductive layer 17 of the capacitor first electrode on the first insulating layer, and impurity on the first conductive layer 17 of the capacitor first electrode Forming a second insulating film 18 on the remaining portions except for the portion in contact with the region 15, forming a second electrode 19 of a capacitor on the second insulating film 18, and forming a second electrode of the capacitor. To form a third insulating film 20 thereon. And forming the third insulating layer 20, and forming a first electrode 22 by forming a second conductive layer on the third insulating layer 20 and the first conductive layer 21. A method for manufacturing a semiconductor device. 제1항에 있어서, 상기 제1전극(22)은, 제1전도층(17)과 제2전도층(21)이 서로 연결되어 이루어진 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first electrode (22) is formed by connecting a first conductive layer (17) and a second conductive layer (21) to each other. 제1항에 있어서, 상기 제1 내지 제3절연막(16)(18)(20)은, 산화막과 질화막중 하나를 선택하여 형성한 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the first to third insulating films (16, 18, 20) are formed by selecting one of an oxide film and a nitride film. 제1항에 있어서, 상기 제1전극(22)과 제2전극(19)은, 도우프드 폴리실리콘으로 형성한 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the first electrode (22) and the second electrode (19) are formed of doped polysilicon. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930013794A 1993-07-21 1993-07-21 Method for manufacturing semiconductor device KR960015525B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930013794A KR960015525B1 (en) 1993-07-21 1993-07-21 Method for manufacturing semiconductor device

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Application Number Priority Date Filing Date Title
KR1019930013794A KR960015525B1 (en) 1993-07-21 1993-07-21 Method for manufacturing semiconductor device

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KR950004547A true KR950004547A (en) 1995-02-18
KR960015525B1 KR960015525B1 (en) 1996-11-15

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Publication number Priority date Publication date Assignee Title
KR100630667B1 (en) * 2000-08-25 2006-10-02 삼성전자주식회사 Method of manufacturing capacitor for semiconductor device
KR101854005B1 (en) 2014-08-27 2018-05-02 주식회사 엘지화학 Liquid Crystal Composition

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