KR970024205A

KR970024205A - DRAM manufacturing method of semiconductor device

Info

Publication number: KR970024205A
Application number: KR1019950034980A
Authority: KR
Inventors: 문영화
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1995-10-11
Filing date: 1995-10-11
Publication date: 1997-05-30

Abstract

본 발명은 반도체 소자의 디램 형성방법에 관한 것으로, 보다 구체적으로는 디램 소자의 전하 저장 전극 면적을 증대시킴으로써 고집적 대용량을 확보할 수 있는 반도체 소자의 디램 형성방법에 관한 것으로 본 발명은 디램 소자에 구비되는 캐패시터의 전하 저장 전극의 면적을 증대시키기 위하여, 전하 저장 전극을 형성하기 위한 폴리실리콘막을 종래에 비하여 두껍게 형성한다음, 소정 깊이 만큼 선택적으로 식각하여 표면적이 증가된 디램 소자의 캐패시터 전하 저장 전극을 형성하므로써, 고집적 대용량에 적용할 수 있는 드램소자를 형성할 수 있다.The present invention relates to a method of forming a DRAM of a semiconductor device, and more particularly, to a method of forming a DRAM of a semiconductor device capable of securing a high integrated capacity by increasing the area of charge storage electrodes of the DRAM device. In order to increase the area of the charge storage electrode of the capacitor to be formed, a polysilicon film for forming the charge storage electrode is formed thicker than the conventional one, and then selectively etched by a predetermined depth to increase the surface area of the capacitor charge storage electrode of the DRAM element By forming, a DRAM element applicable to a highly integrated large capacity can be formed.

Description

DRAM manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도 (가) 내지 (바)는 본 발명의 일실시예에 따른 반도체 소자의 디램 제조방법을 나타낸 단면도.Figure 2 (a) to (bar) is a cross-sectional view showing a DRAM manufacturing method of a semiconductor device according to an embodiment of the present invention.

Claims

Forming a field oxide film, a gate insulating film, a gate electrode and a source drain electrode on the semiconductor substrate; Forming an interlayer insulating layer on the structure and forming a contact hole to expose a source electrode; Forming a charge storage electrode by forming polysilicon for a charge storage electrode on the contact hole region and the interlayer insulating layer, and etching the predetermined portion to form a charge storage electrode; Forming a dielectric over the entire structure and forming a plate electrode; The forming of the charge storage electrode may include depositing polysilicon for the charge storage electrode of a thick film on the contact hole region and the interlayer insulating layer, and etching the polysilicon in a predetermined pattern except for the contact hole region and the peripheral region thereof. And a second etching step of selectively etching concave regions formed by contact holes in the polysilicon pattern in which the first etching step is performed to a predetermined depth.

The method of claim 1, wherein the thickness of the polysilicon for charge storage electrodes is 4000 to 6000 GPa.

3. The method of claim 1, wherein the polysilicon is etched by 200 to 2500 kPa in the second etching step. 4.

The method of claim 1, further comprising, after the second etching step, performing impurity doping in a chamber to improve conductivity of the formed charge storage electrode.

※ Note: The disclosure is based on the initial application.