KR101008225B1 - Method of forming storage node electrode of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to form a gate electrode on a semiconductor substrate, sequentially stacking a first insulating film and a second insulating film on the semiconductor substrate, and patterning the second insulating film and the first insulating film. Opening a substrate in the region, forming a lower electrode connected to the substrate of the second insulating film and the open portion of the first insulating film and a dielectric film thereon, and forming an upper electrode surrounding the dielectric film on the second insulating film. And etching the second insulating film and the first insulating film to form a spacer on the sidewalls of the gate electrode, simultaneously opening a substrate between the gate electrodes, and forming a source / drain region on the opened substrate. The present invention punches a transistor by forming a source / drain region after an ONO film production process involving a high temperature process. The base is a characteristic deterioration is prevented in advance.

Capacitor, Gate Electrode, Spacer, High Temperature Process, Punch Through

Description

Method of manufacturing semiconductor memory device {Method of forming storage node electrode of semiconductor memory device}             

1A to 1I are flowcharts illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention;

2A to 2K are flowcharts illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention.

Description of the Related Art [0002]

10, 100: semiconductor substrate 12, 102: device isolation film

14, 104: gate electrode 16, 105: LDD region

18, 106: first insulating film 20, 108: second insulating film

22, 112: open area 24, 114: lower electrode

26, 116: dielectric films 28, 118: upper electrode

18a, 20a, 106a, 108a: spacer 30, 120: source / drain regions

32, 122: silicide 110: sacrificial film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a semiconductor memory device, which can be usefully used for a SoC (System on Chip) device having a memory chip and a logic circuit.

At present, in order to achieve high integration of semiconductor devices, research / development has been actively conducted on reduction of cell area and reduction of operating voltage. In addition, as the integration of semiconductor devices increases, the area of the capacitor is rapidly decreasing, and therefore, the charge required for the operation of the memory device, that is, the capacitance secured in the unit area, must be further increased.

On the other hand, as a semiconductor memory device, a SoC device having one-chip DRAM and a logic circuit has the following problems.

 The first is a process problem. The manufacturing process of a DRAM using a stack capacitor is complicated, and there are many parts different from the manufacturing process of a logic circuit, which increases the manufacturing cost by increasing the overall manufacturing process step and lowering the yield.

Second, due to the device problem, there is a high temperature process such as Oxide Nitride Oxide (ONO) in the capacitor manufacturing process of the memory cell, which weakens the punchthrough characteristics of the transistor during the high temperature process.

An object of the present invention is to form an open region by patterning an insulating film for a spacer of the gate electrode, and to fabricate a capacitor consisting of a lower electrode, a dielectric film and an upper electrode in the open region, and then etching the insulating film to form a spacer of the gate electrode. Fabrication of a semiconductor memory device capable of preventing the punch-through characteristics of a transistor caused by a high temperature process accompanying a capacitor manufacturing process of a memory cell from becoming weak by forming a source / drain region on the opened substrate after opening the substrate surface. To provide a method.

In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor memory device having a cell and a capacitor, the method comprising: forming a gate electrode on a semiconductor substrate and sequentially laminating a first insulating film and a second insulating film thereon; Patterning the insulating film and the first insulating film to open the substrate in the capacitor region; forming a lower electrode connected to the substrate of the open portion of the second insulating film and the first insulating film; and forming a dielectric film thereon; Forming an upper electrode surrounding the dielectric film, etching the second insulating film and the first insulating film to form a spacer on the sidewall of the gate electrode, and simultaneously opening a substrate between the gate electrodes, and source / drain regions on the opened substrate. Forming a step.                     

In order to achieve the above object, another method of the present invention provides a method of manufacturing a semiconductor memory device having a cell and a capacitor, the method comprising: forming a gate electrode on a semiconductor substrate, and sequentially stacking a first insulating film, a second insulating film, and a sacrificial film thereon; Opening the substrate in the capacitor region by patterning the sacrificial film, the second insulating film and the first insulating film, and forming a lower electrode connected to the substrate in the open region of the sacrificial film, the second insulating film and the first insulating film. Removing the sacrificial layer and sequentially forming the dielectric layer and the upper electrode on the lower electrode surface; etching the second insulating layer and the first insulating layer to form spacers on the sidewalls of the gate electrode, and simultaneously forming a substrate between the gate electrodes. Opening and forming a source / drain region in the opened substrate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1I are flowcharts illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention. Referring to these drawings, the manufacturing process of an embodiment of the present invention is as follows.

As shown in FIG. 1A, a device isolation film 12 is formed by performing a shallow trench isolation (STI) process on a silicon substrate as the semiconductor substrate 10. A gate insulating film (not shown) and a gate electrode 14 are formed on the semiconductor substrate. Then, as the LDD ion implantation, the n-dopant is ion-implanted at low concentration to form the n-LDD region 16 and then the spacer material to be formed on the sidewall of the gate electrode on the front surface of the semiconductor substrate. (20) is sequentially thinly stacked. At this time, the first insulating film 18 and the second insulating film 20 are etch-selective materials. For example, the first insulating film 18 is a silicon oxide film, and the second insulating film 20 is a silicon nitride film.

Subsequently, as shown in FIG. 1B, the second insulating layer 20 and the first insulating layer 18 are patterned to open the substrate of the capacitor region by performing a photolithography and an etching process using the lower electrode contact mask. In this case, the area where the substrate surface is opened is indicated by 22.

1C and 1D, a doped polysilicon film is deposited on the upper surface of the semiconductor substrate 10 and patterned to form an open region 22 of the second insulating film 20 and the first insulating film 18. A lower electrode 24 is formed to be perpendicular to the substrate, and an ONO film is deposited as the dielectric film 26 on the lower electrode 24 surface. In this case, the cell transistor region is masked by the first and second insulating layers 18 and 20 for spacers and the punch-through of the transistor is formed before the n + source / drain region is formed. Occurrence is suppressed.

Subsequently, as shown in FIG. 1E, a doped polysilicon film is deposited on the entire upper surface of the semiconductor substrate 10 and patterned to form an upper electrode 28 that surrounds the dielectric film 26 on the second insulating film 20. do.

Then, as shown in FIG. 1F, the second insulating film 20 and the first insulating film 18 are dry-etched to expose the upper surface of the gate electrode 14, and the spacers 20a and 18a are formed on the sidewalls of the gate electrode 14. ) And at the same time open the substrate surface between the gate electrode 14. The n dopant is ion implanted at a high concentration to form the n + source / drain region 30 in the open substrate.

Subsequently, as shown in FIG. 1G, a titanium film Ti is deposited on the entire surface of the resultant as a silicide film and an annealing process is performed to react silicon and the titanium film so as to react with the gate electrode 14, the source / drain region 30, and the upper portion. The silicide film 32 is formed on the surface of the electrode 28 and the unreacted titanium film is removed. In this case, the silicide process is a manufacturing process that is performed to lower the resistance of the gate electrode of the logic circuit. A silicide layer is also formed on the upper electrode to apply an even bias to the entire capacitor.

1H and 1I, an interlayer insulating film 34 is formed on the entire upper surface of the semiconductor substrate 10, and the surface is planarized by a chemical mechanical polishing (CMP) process. Then, after the contact hole is formed in the interlayer insulating film 34, a wiring process is performed to form a contact electrode 36 that is vertically connected to the source / drain region 30 through the contact hole in the interlayer insulating film 34.

2A to 2K are flowcharts illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention. Referring to these drawings, the manufacturing process of another embodiment of the present invention is as follows.

As shown in FIG. 2A, after forming the device isolation layer 102 and the gate insulating layer (not shown) on the silicon substrate as the semiconductor substrate 100, the gate electrode 104 is formed. Next, as the LDD ion implantation, the n-doped layer is ion-implanted at low concentration to form the n-LDD region 105 and the spacer material to be formed on the sidewall of the gate electrode on the entire surface of the semiconductor substrate 100. The two insulating films 108 are sequentially stacked thinly. In this case, the first insulating film 106 and the second insulating film 108 are materials having an etching selectivity. For example, the first insulating film 106 is a silicon oxide film, and the second insulating film 108 is a silicon nitride film.

Subsequently, as shown in FIG. 2B, a silicon oxide film is deposited on the second insulating film 108 as a sacrificial film 110 for a capacitor having a FIN structure.

 Next, as shown in FIG. 2C, the sacrificial layer 110, the second insulating layer 108, and the first insulating layer 106 are patterned by performing a photolithography and an etching process using a lower electrode contact mask to form a substrate in the capacitor region. Open it. At this time, the area where the substrate surface is opened is indicated by 112.

As shown in FIG. 2D, a doped polysilicon film is deposited on the entire upper surface of the semiconductor substrate 100 and patterned to form an open region of the sacrificial layer 110, the second insulating layer 108, and the first insulating layer 106. A lower electrode 114 is formed to be perpendicular to the substrate of 112.

As shown in FIG. 2E, the sacrificial layer 110 is selectively removed to form the lower electrode 114 having the FIN structure.

2F, an ONO film is deposited as the dielectric film 116 on the lower electrode 114 surface. At this time, the cell transistor region is masked by the first and second insulating layers 106 and 108 for spacers in the process of manufacturing the ONO film accompanying the high temperature process and before the n + source / drain region is formed, punch-through of the transistor is performed. Occurrence is suppressed.                     

Subsequently, as shown in FIG. 2G, a doped polysilicon film is deposited on the upper surface of the semiconductor substrate 100 and patterned to form an upper electrode 118 that surrounds the dielectric film 116 on the second insulating film 108. do.

Then, as shown in FIG. 2H, the second insulating layer 108 and the first insulating layer 106 are dry-etched to expose the upper surface of the gate electrode 104, and the spacers 108a and 106a are formed on the sidewalls of the gate electrode 104. And at the same time open the substrate surface between the gate electrode 104. The n dopant is implanted at a high concentration to form the n + source / drain region 120 in the open substrate.

Next, as shown in FIG. 2I, a titanium film Ti is deposited on the entire surface of the resultant as a silicide film and an annealing process is performed to react silicon and the titanium film so that the gate electrode 104, the source / drain region 120, and the upper portion thereof are formed. The silicide layer 122 is formed on the surface of the electrode 118 and the unreacted titanium layer is removed. In this case, the silicide process is a manufacturing process that is performed to lower the resistance of the gate electrode of the logic circuit. A silicide layer is also formed on the upper electrode to apply an even bias to the entire capacitor.

2J and 2K, an interlayer insulating layer 124 is formed on the entire upper surface of the semiconductor substrate 100, and the surface is planarized by a CMP process. After the contact hole is formed in the interlayer insulating layer 124, a wiring process is performed to form a contact electrode 126 vertically connected to the source / drain region 120 through the contact hole in the interlayer insulating layer 124.

As described above, the present invention forms an open region by patterning an insulating film for a spacer of the gate electrode, and after manufacturing a capacitor consisting of a lower electrode, a dielectric film, and an upper electrode in the open region, the insulating film is etched to form a spacer of the gate electrode. At the same time, the substrate surface is opened and a source / drain region is formed in the opened substrate.

Therefore, the present invention uses the spacer of the sidewall of the gate electrode as a side insulating film between the capacitors to reduce the interlayer insulating film manufacturing process compared to the general DRAM, and the height of the capacitor is low, the height difference between the DRAM and logic circuit is reduced, which is advantageous for the planarization of the interlayer insulating film.

In addition, the present invention prevents the punch-through characteristics of the transistor from deteriorating by forming a source / drain region after the ONO film production process involving a high temperature process. In addition, in the present invention, since the silicide is formed on the upper part of the capacitor, an even bias may be applied to the entire capacitor.

Therefore, the present invention has an advantage of improving the yield and reliability of SoC devices in which the memory cells and logic circuits are one-chip.

Claims (8)

In the method of manufacturing a semiconductor memory device having a cell and a capacitor, Forming a gate electrode over the semiconductor substrate and sequentially stacking a first insulating film and a second insulating film thereon; Patterning the second insulating layer and the first insulating layer to open a substrate in the capacitor region; Forming a lower electrode connected to the substrate of the open portion of the second insulating film and the first insulating film and a dielectric film thereon; Forming an upper electrode surrounding the dielectric layer on the second insulating layer; Etching the second insulating film and the first insulating film to form a spacer on sidewalls of the gate electrode and simultaneously opening a substrate between the gate electrodes; And Forming a source / drain region in the open substrate, And forming a silicide layer on surfaces of the gate electrode, the source / drain region, and the upper electrode after forming the source / drain region. The method of claim 1, wherein after forming the gate electrode, And forming an LDD region on the surface of the semiconductor substrate. The method of claim 1, wherein the first insulating layer and the second insulating layer are materials having an etching selectivity. delete In the method of manufacturing a semiconductor memory device having a cell and a capacitor, Forming a gate electrode on the semiconductor substrate and sequentially stacking a first insulating film, a second insulating film, and a sacrificial film on the semiconductor substrate; Patterning the sacrificial layer, the second insulating layer, and the first insulating layer to open a substrate in the capacitor region; Forming a lower electrode connected to a substrate of an open portion of the sacrificial layer, the second insulating layer, and the first insulating layer; Removing the sacrificial layer and sequentially forming a dielectric layer and an upper electrode on the exposed lower electrode surface and the sacrificial layer to which the sacrificial layer is removed; Etching the second insulating film and the first insulating film to form a spacer on sidewalls of the gate electrode and simultaneously opening a substrate between the gate electrodes; And And forming a source / drain region on the open substrate. The method of claim 5, wherein after forming the gate electrode, And forming an LDD region on the surface of the semiconductor substrate. The method of claim 5, wherein the first insulating layer and the second insulating layer are materials having an etch selectivity. The method of claim 5, wherein after forming the source / drain regions, And forming a silicide film on the gate electrode, the source / drain region, and the upper electrode surface.

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