KR100880838B1 - Method for manufacturing semiconductor device with recess gate - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor device having a recess gate, the method of manufacturing a semiconductor device of the present invention comprises the steps of: forming a hard mask pattern having an opening for a recess on a semiconductor substrate; Forming a recess by etching the semiconductor substrate using the hard mask pattern as an etch barrier; Forming a gate insulating film on the recess surface; Forming a first gate electrode filling a portion of the recess and the opening to a point downwardly downward from a surface of the hard mask pattern; Forming a first insulating layer pattern filling the remainder of the opening on the first gate electrode; Removing the hard mask pattern; And forming a source / drain region in the semiconductor substrate by performing an impurity implantation process using the first insulating layer pattern as a mask, wherein the method of manufacturing a semiconductor device according to the present invention is used to form a recess. The lowermost layer of the gate pattern is first patterned using a hard mask pattern to form a lower gate electrode, and subsequently, source / drain regions are formed in the semiconductor substrates on both sides of the lower gate electrode, and then an upper layer, patterning, etc. of the gate pattern is formed. By performing the subsequent process of, it is possible to solve the problem caused by the misalignment between the recess and the gate and the shorting of the landing plug contact and the gate to improve the electrical characteristics and the process yield of the device.

Recess gate, misalign, short

Description

A method of manufacturing a semiconductor device having a recess gate {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH RECESS GATE}

1A and 1B illustrate a manufacturing method and a problem of a semiconductor device having a recess gate according to the prior art;

2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20 semiconductor substrate 21 device isolation film

22: opening 23: buffer oxide film pattern

24: hard mask pattern 25: recess

26 gate insulating film 27 polysilicon film for gate electrode

27a: polysilicon gate electrode 28a: first insulating film pattern

29 source / drain region 30a: second insulating film pattern

31 metal film for gate electrode 31a metal gate electrode

32: insulating film for gate hard mask 32a: gate hard mask

33: gate spacer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a method for manufacturing a semiconductor device having a recess gate.

One of the most important parameters in the fabrication of transistors in semiconductor devices is the threshold voltage (Vt). The threshold voltage is changed depending on the thickness of the gate oxide layer, the channel doping concentration, the oxide charge, the gate electrode material, and the like. Recently, as semiconductor devices are highly integrated, manufacturing of semiconductor devices having high speeds and low operating voltages is required, and a threshold voltage is also required.

However, as the size of the semiconductor device decreases as the semiconductor device is highly integrated, a short channel effect occurs due to a decrease in the channel length of the transistor. This short channel effect causes various problems, such as changing the threshold voltage to be different from the theoretical value, making it difficult to control the device and causing a drain induced barrier lowering (DIBL) caused by a hot carrier.

In order to solve this problem, a recess gate process capable of increasing the channel length of a transistor by forming a recess by etching a gate predetermined region of a semiconductor substrate active region and forming a gate on the recess is manufactured. It became.

1A and 1B are views for explaining a method and a problem of a semiconductor device having a recess gate according to the prior art.

A method of manufacturing a semiconductor device having a recess gate according to the prior art will be described with reference to FIGS. 1A and 1B as follows. In this case, the same or similar parts in FIGS. 1A and 1B use the same reference numerals.

First, the device isolation layer 11 is formed on the semiconductor substrate 10 to form an active region of the semiconductor substrate 10.

Subsequently, after forming a hard mask pattern (not shown) exposing the recessed region on the semiconductor substrate 10, the hard mask pattern is etched using an etching barrier to etch the active region of the semiconductor substrate 10. (12) is formed.

Subsequently, after removing the hard mask pattern, the gate insulating layer 13 is formed on the entire surface of the semiconductor substrate 10 including the recess 12.

Subsequently, the polysilicon film 14 for the gate electrode, the metal film 15 for the gate electrode, and the insulating film 16 for the gate hard mask are sequentially formed on the gate insulating film 13, and then the photoresist film pattern for gate patterning ( The gate pattern 100 is formed by sequentially etching the insulating film 16 for the gate hard mask, the metal film 15 for the gate electrode, and the polysilicon film 14 for the gate electrode.

Subsequently, gate spacers 17 are formed on both sidewalls of the gate pattern 100, and source / drain regions 18 are formed in the semiconductor substrate 11 on both sides of the gate pattern 100.

As a result of this process, it is possible to form a recess gate in which a part is embedded in the recess and the rest protrudes on the surface of the semiconductor substrate.

However, such a recess gate forming method has the following problems.

Referring to FIG. 1A, when mis-alignment occurs between the photoresist pattern for gate patterning and the recess 12, the gate pattern 100 is asymmetrically formed around the recess 12. This results in asymmetrical formation of the source / drain regions 18, which causes deterioration of the electrical characteristics of the device.

In addition, referring to FIG. 1B, as the height of the gate pattern 100 increases, the gate hard mask insulating layer 16 may be inclined during etching to form the gate pattern 100. The inclination of the gate hard mask insulating film 16 affects the etching of the gate electrode metal film 15 and the gate electrode polysilicon film 14. A part of the polysilicon film 14 for the lower gate electrode is exposed (see "A"). This causes a shorting of the landing plug contact and the polysilicon film 14 for the gate electrode formed in a subsequent process.

The present invention has been proposed to solve the above-mentioned problems of the prior art, by using a hard mask pattern used for forming a recess to first pattern the bottom layer of the gate pattern to form a bottom gate electrode, and subsequently to the bottom gate electrode. After the source / drain regions are formed in the semiconductor substrates on both sides, a subsequent process such as forming and patterning the upper layer of the gate pattern is performed to solve the problem of misalignment between the recess and the gate, and the problem of landing plug contact and gate shorting. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device having a recess gate capable of improving the electrical characteristics and process yield of the device.

A method of manufacturing a semiconductor device having a recess gate of the present invention for achieving the above object comprises the steps of forming a hard mask pattern having an opening for a recess on a semiconductor substrate; Forming a recess by etching the semiconductor substrate using the hard mask pattern as an etch barrier; Forming a gate insulating film on the recess surface; Forming a first gate electrode filling a portion of the recess and the opening to a point downwardly downward from a surface of the hard mask pattern; Forming a first insulating layer pattern filling the remainder of the opening on the first gate electrode; Removing the hard mask pattern; And forming a source / drain region in the semiconductor substrate by performing an impurity implantation process using the first insulating layer pattern as a mask.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to an embodiment of the present invention.

As shown in FIG. 2A, the device isolation layer 21 is formed on the semiconductor substrate 20 to form an active region of the semiconductor substrate 20.

Subsequently, a hard mask pattern 24 having an opening 22 exposing the region to be recessed is formed on the semiconductor substrate 20. In this case, the hard mask pattern 24 may be formed of a nitride film, and a buffer oxide film pattern 23 may be interposed below the hard mask pattern 24.

As shown in FIG. 2B, the recess 25 is formed by etching the semiconductor substrate 20 in which the hard mask pattern 24 is exposed as an etching barrier.

As shown in FIG. 2C, after the gate insulating film 26 is formed on the surface of the recess 25, the polysilicon film 27 for the gate electrode is formed on the entire structure of the resultant product including the hard mask pattern 24. To form.

As shown in FIG. 2D, a blanket etch is performed on the polysilicon film 27 for the gate electrode to a point downwardly downward from the surface of the hard mask pattern 24, thereby forming the recess 25 and the opening. The polysilicon film 27 for gate electrodes is embedded in a part of (22). Hereinafter, the polysilicon film 27 for gate electrodes embedded in a part of the recess 25 and the opening 22 is referred to as a polysilicon gate electrode 27a.

As described above, the polysilicon gate electrode 27a that forms the bottom of the gate pattern is first formed using the hard mask pattern 24, thereby preventing misalignment of the recess 25 and the polysilicon gate electrode 27a. can do.

Subsequently, a first insulating layer 28 is formed on the hard mask pattern 24 and the polysilicon gate electrode 27a to serve as a mask in a subsequent impurity implantation process. At this time, the first insulating film 28 is preferably made of an oxide film.

As shown in FIG. 2E, a CMP (Chemical Mechanical Polishing) process or a blanket etching process is performed on the first insulating layer 28 until the hard mask pattern 24 is exposed, thereby filling the rest of the opening 22. The first insulating film pattern 28a is formed. That is, by using the hard mask pattern 24, a stacked structure of the polysilicon gate electrode 27a and the first insulating layer pattern 28a aligned with the recess 25 may be formed.

As shown in Fig. 2F, the hard mask pattern 24 and the buffer oxide film pattern 23 are removed. That is, when the buffer oxide film pattern 23 is interposed below the hard mask pattern 24, the buffer oxide film pattern 23 may be removed as shown in this drawing. However, the buffer oxide film pattern 23 is not necessarily removed, and other embodiments may exist in which only the hard mask pattern 24 is removed and the buffer oxide film pattern 23 is left.

Subsequently, an impurity implantation process is performed using the first insulating layer pattern 28a as a mask to form the source / drain regions 29 in the active regions of the semiconductor substrate 20 on both sides of the polysilicon gate electrode 27a.

As such, the source / drain region 29 may be symmetrically formed by implanting impurities using the polysilicon gate electrode 27a and the first insulating layer pattern 28a aligned with the recess 25.

 Subsequently, a second insulating film 30 is formed on the entire structure of the resultant product including the polysilicon gate electrode 27a and the first insulating film pattern 28a. At this time, the second insulating film 30 is preferably made of an oxide film.

As shown in FIG. 2G, a planarization process (for example, CMP) is performed on the first insulating film pattern 28a and the second insulating film 30 until the polysilicon gate electrode 27a is exposed to form polysilicon. A second insulating layer pattern 30a having a planarized surface with the polysilicon gate electrode 27a is formed on the semiconductor substrate 20 on both sides of the gate electrode 27a.

As shown in FIG. 2H, the gate electrode metal film 31 and the gate hard mask insulating film 32 are sequentially formed on the polysilicon gate electrode 27a and the second insulating film pattern 30a.

As shown in FIG. 2I, the gate hard mask insulating film 32 and the gate electrode metal film 31 are etched using a gate mask (not shown) to etch the metal gate electrode 31a and the gate hard mask 32a. ) To form a laminated structure.

As a result of the process of this figure, the gate pattern 200 in which the polysilicon gate electrode 27a, the metal gate electrode 31a, and the gate hard mask 32a are sequentially stacked is formed. At this time, even when the gate hard mask 32a and / or the metal gate electrode 31a are inclined during etching for forming the gate pattern 200, the preformed polysilicon gate electrode 27a is not affected. Therefore, it is possible to prevent the following shorting of the landing plug contact and the polysilicon gate electrode 27a.

As illustrated in FIG. 2J, an insulating film for the gate spacer is formed on the entire surface of the resultant in which the gate pattern 200 is formed, and then a blanket etching is performed until the second gate pattern 30a is exposed, thereby performing the metal gate electrode 31a. And gate spacers 33 on both sidewalls of the gate hard mask 32a. At this time, the gate spacer 33 is preferably made of an oxide film.

Subsequently, although not shown in the drawing, the second insulating layer pattern 30a of the portion exposed by the gate pattern 200 and the gate spacer 33 may be removed in a subsequent process. As a result, the second insulating film pattern 30a remaining on both sidewalls of the polysilicon gate electrode 27a serves as the gate spacer 33.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In the above-described method of manufacturing a semiconductor device having a recess gate according to the present invention, a bottom gate electrode is first patterned using a hard mask pattern used to form a recess to form a bottom gate electrode, and the bottom gate is successively formed. After the source / drain regions are formed in the semiconductor substrates on both sides of the electrode, subsequent processes such as formation and patterning of the upper layer of the gate pattern are performed, resulting in misalignment between the recesses and the gates, and shortening of landing plug contacts and gates. By solving the problem can improve the electrical characteristics and process yield of the device.

Claims (15)

Forming a hardmask pattern having openings for recesses on the semiconductor substrate; Forming a recess by etching the semiconductor substrate using the hard mask pattern as an etch barrier; Forming a gate insulating film on the recess surface; Forming a first gate electrode filling a portion of the recess and the opening to a point downwardly downward from a surface of the hard mask pattern; Forming a first insulating layer pattern filling the remainder of the opening on the first gate electrode; Removing the hard mask pattern; And Forming a source / drain region in the semiconductor substrate by performing an impurity implantation process using the first insulating layer pattern as a mask; Method for manufacturing a semiconductor device comprising a. The method of claim 1, After the source / drain region forming step, Forming a second insulating film pattern having a surface planarized with the first gate electrode on the semiconductor substrate on both sides of the first gate electrode while removing the first insulating film pattern; Sequentially forming an insulating film for a second gate electrode and an insulating film for a gate hard mask on the first gate electrode and the second insulating film pattern; And Selectively etching the gate hard mask insulating layer and the second gate electrode conductive layer to form a stacked structure of a second gate electrode and a gate hard mask Method of manufacturing a semiconductor device further comprising. The method of claim 2, After the step of forming a stacked structure of the second gate electrode and the gate hard mask, Forming an insulating film for a gate spacer on the entire surface of the resultant product; And Forming a gate spacer on both sidewalls of the second gate electrode and the gate hard mask by performing a blanket etching process until the second insulating layer pattern is exposed; Method of manufacturing a semiconductor device further comprising. The method according to claim 1 or 2, The hard mask pattern is made of a nitride film Method of manufacturing a semiconductor device. The method of claim 4, wherein A buffer oxide layer pattern is interposed below the hard mask pattern. Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The first gate electrode is made of a polysilicon film Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The first gate electrode forming step, Forming a conductive film for the first gate electrode on the entire structure of the resultant including the hard mask pattern; And Blanket etching the conductive film for the first gate electrode to a point downwardly downward from a surface of the hard mask pattern; Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The first insulating film pattern is made of an oxide film Method of manufacturing a semiconductor device. The method according to claim 1 or 2, The first insulating film pattern forming step, Forming a first insulating layer on the hard mask pattern and the first gate electrode; And Performing a CMP process or a blanket etching on the first insulating layer until the hard mask pattern is revealed. Method of manufacturing a semiconductor device. The method of claim 5, The hard mask pattern removing step, Removing the buffer oxide pattern Method of manufacturing a semiconductor device. The method of claim 5, The hard mask pattern removing step, The buffer oxide layer pattern is left while the hard mask pattern is removed. Method of manufacturing a semiconductor device. The method of claim 2, The second insulating film pattern is made of an oxide film Method of manufacturing a semiconductor device. The method according to claim 2 or 12, wherein The second insulating film pattern forming step, Forming a second insulating film on an entire structure of a resultant product including the first gate electrode and the first insulating film pattern; And Performing a planarization process until the first gate electrode is exposed. Method of manufacturing a semiconductor device. The method of claim 2, The conductive film for the second gate electrode is a metal film Method of manufacturing a semiconductor device. The method of claim 3, The insulating film for the gate spacer is an oxide film Method of manufacturing a semiconductor device.

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