KR20060080718A - Method for forming semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, and in forming a recess gate capable of solving a short channel effect, a misalignment between a recess gate region and a gate is performed. The present invention relates to a method of forming a semiconductor device in which an oxide spacer is formed on a sidewall of a hard mask nitride layer pattern forming a recess gate region in order to solve the problem of the contact and short-circuit with a contact in a subsequent process.

Description

Method of forming a semiconductor device {METHOD FOR FORMING SEMICONDUCTOR DEVICE}

1 is a cross-sectional view showing a problem of the recess gate forming method according to the prior art.

2A-2K are cross-sectional views illustrating a method of forming a recess gate in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In particular, in forming a recess gate capable of solving a short channel effect, a misalignment between a recess gate region and a gate is performed. The present invention relates to a method of forming a semiconductor device in which an oxide spacer is formed on a sidewall of a hard mask nitride layer pattern that forms a recess gate region and a gate is formed to solve the problem of a) and a short circuit with a contact in a subsequent process.

One of the most important parameters in the manufacture of transistors in semiconductor devices is the threshold voltage (Vt). The threshold voltage is a variable that depends on the gate oxide thickness, the channel doping concentration, the oxide charge, and the material used for the gate. As the size of the device decreases as the threshold voltage, various phenomena appearing that do not coincide with theoretical values. The problem currently encountered is the short channel effect that occurs as the gate channel length decreases.

As semiconductor devices are highly integrated, nanoscale devices require faster devices and devices that operate at lower operating voltages of 1 to 2V. Accordingly, threshold voltages also require lower voltages.

However, when the threshold voltage becomes lower, it becomes impossible to control the device due to the short channel effect. In addition, the short channel effect has a problem of causing a drain induced built-in leak (DIBL) phenomenon due to a hot carrier.

In order to reduce the short channel effect, various researches are underway, but the solution to satisfy this problem is still incomplete due to the high integration of semiconductor devices.

The direction currently being studied is to find a solution by adjusting the doping concentration, but this is not the solution for the ultimate short channel effect. Currently known research methods include super steep retrograde channels (SSRs), near ion implant channels (Vertically Abrupt Channel Doping), and ion implant channels (Laterally Abrupt Channel Doping). A method of forming a channel having a halo structure through a large angle tilt implant has been studied.                         

However, the reduction of the short channel effect through the gate oxide thickness and the channel concentration has a fundamental limitation.

Recently, in order to overcome the fundamental limitation, the channel length can be increased by the recess gate.

1 is a cross-sectional view illustrating a problem of a method of forming a recess gate according to the related art.

Referring to FIG. 1, after forming an isolation layer 25 defining an active region 20 on a semiconductor substrate 10, the recess gate region 70 is formed by etching the active region 20 of a gate predetermined region. do. Next, after the gate oxide film 80, the gate polysilicon layer 85, the conductive layer 90 and the hard mask layer 95 are formed on the entire surface of the semiconductor substrate, a process of exposing and developing the photoresist pattern for forming the gate is performed. Perform. In this case, a gate is asymmetrically formed around the recess gate region 70 by misalignment of the recess gate region 70 and the photoresist pattern (not shown). For this reason, the source / drain regions 55 on both sides of the gate are asymmetrically formed in a subsequent process, which causes deterioration of the electrical characteristics of the semiconductor device. In addition, when the landing plug contact is formed, a problem may occur in that the contact and the gate are short-circuited, and the size of the contact is not constant.

As described above, the method of forming a semiconductor device according to the related art uses a method of increasing a channel length by forming a recess gate in order to overcome a problem caused by a short channel effect. However, the problem caused by the misalignment of the recess gate region and the gate and the short-circuit with a contact in a subsequent process have caused a problem of deterioration of the electrical characteristics of the semiconductor device and a decrease in formation yield.

The present invention provides an oxide spacer on a sidewall of a hard mask nitride layer pattern forming a recess gate region, thereby solving the problem of misalignment between the recess gate region and the gate. It is an object of the present invention to provide a method for forming a semiconductor device that can solve the problem of shorting with a contact in a subsequent step.

The semiconductor device according to the present invention for achieving the above object,

(a) forming a hard mask nitride layer pattern exposing a recess gate region on a semiconductor substrate including an isolation layer defining an active region;

(b) implanting impurity ions into the exposed semiconductor substrate using the hard mask nitride film pattern as an ion implantation mask to form an LDD region;

(c) forming an oxide spacer on sidewalls of the hard mask nitride layer pattern;

(d) recessing the semiconductor substrate using the hard mask nitride layer pattern and the oxide layer spacer as an etch mask to form a recess gate region;

(e) forming a gate oxide film in the recess gate region;

(f) forming a gate polysilicon layer filling the recess gate region over the entire surface;

(g) planarizing etching the gate polysilicon layer, the hard mask nitride layer pattern and the oxide spacer of a predetermined thickness;

(h) forming a metal layer and a hard mask layer on the entire surface of the semiconductor substrate and then forming a gate by a photolithography process using a gate mask;

(i) removing the hard mask nitride layer pattern and implanting impurities to form source / drain regions.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2K are cross-sectional views illustrating a method of forming a recess gate according to the present invention.

Referring to FIG. 2A, a buffer oxide layer 130 and a hard mask nitride layer are formed on a semiconductor substrate 100 having an isolation layer 125 defining an active region 120, and then expose a recess gate region. The hard mask nitride layer pattern 140 is formed, and the buffer oxide layer 130 is etched using the hard mask nitride layer pattern 140 as an etch mask to expose a central portion of the active region 120 of the semiconductor substrate 100. In this case, after forming the shallow trench isolation (STI) device isolation layer 125, it is preferable to perform well ion implantation and channel ion implantation in the active region 120. In addition, the pattern for forming the recess gate may be formed by etching the hard mask nitride layer and the buffer oxide layer using a photoresist pattern in which the buffer oxide layer and the hard mask nitride layer are stacked and the recess gate predetermined region is exposed.                     

Referring to FIG. 2B, ion implantation is performed to form a lightly doped drain (LDD) region 150 in the semiconductor substrate 100 exposing the hard mask nitride layer pattern 140 as an ion implantation mask. At this time, the LDD region 150 serves to prevent hot carriers due to the short channel effect.

Referring to FIG. 2C, an oxide layer 160 for forming a spacer is formed on a surface of the hard mask nitride layer pattern 140 for forming the exposed semiconductor substrate 100 and the recess gate region.

Referring to FIG. 2D, the oxide layer 160 for forming the spacer is etched to form the oxide spacer 165 on the sidewall of the hard mask nitride layer pattern 140, and the hard mask nitride layer pattern 140 and the oxide spacer 165 are etched. The semiconductor substrate 100 is recessed with a mask to form a recess gate region.

Referring to FIG. 2E, a gate oxide layer 180 is formed in the recess gate region 170.

Referring to FIG. 2F, a gate polysilicon layer 185 may be formed to fill the recess gate region 170.

Referring to FIG. 2G, the gate polysilicon layer 185 is planarized by a CMP process until the hard mask nitride layer pattern 140 is exposed. After the hard mask nitride layer pattern 140 and the oxide spacer 165 are exposed, the gate polysilicon layer 185 and the hard mask nitride layer pattern 140 and the oxide spacer 165 are polished together to reach a predetermined gate height. It is preferable to etch until flattening.                     

Referring to FIG. 2H, the metal layer 190 and the hard mask layer 195 are sequentially disposed on the hard mask nitride layer pattern 140, the oxide spacer 165, and the gate polysilicon layer 185 exposed in the step of FIG. 2G. Laminated.

Referring to FIG. 2I, a gate is formed by etching the hard mask layer 195 and the metal layer 190 by a photolithography process using a gate mask (not shown). At this time, the process margin of aligning the gate mask and the recess gate region 170 by the thickness of the oxide spacer 165 is increased. Therefore, it is possible to prevent the gate formed due to misalignment asymmetrically.

2J and 2K, the hard mask nitride layer pattern 140 remaining on the semiconductor substrate 100 is removed, and gates are formed on sidewalls of the hard mask layer 195, the metal layer 190, and the oxide spacer 165. The spacer 175 is formed. Next, an impurity implantation process is performed to form the source / drain regions 155. As described above, since the gate spacer 175 and the oxide spacer 165 are formed to protect the gate polysilicon layer 185, the contact plug and the gate polysilicon layer 185 may be shorted in a subsequent contact formation process. It can prevent electrical problem.

As described above, in the method of forming a semiconductor device according to the present invention, a process of forming an oxide spacer and forming a gate on a sidewall of a hard mask nitride film pattern forming a recess gate region is performed in the recess gate forming process. Misalignment problems and subsequent short circuits with contact plugs can be prevented. Therefore, the process margin for forming a highly integrated semiconductor device is increased, thereby providing an effect of improving electrical characteristics and refresh characteristics of the semiconductor device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (2)

(a) forming a hard mask nitride layer pattern exposing a recess gate region on a semiconductor substrate including an isolation layer defining an active region; (b) implanting impurity ions into the exposed semiconductor substrate using the hard mask nitride layer pattern as an ion implantation mask to form an LDD region; (c) forming oxide spacers on sidewalls of the hard mask nitride layer pattern; (d) recessing the semiconductor substrate using the hard mask nitride layer pattern and the oxide layer spacer as an etch mask to form a recess gate region; (e) forming a gate oxide film in the recess gate region; (f) forming a gate polysilicon layer filling the recess gate region over the entire surface; (g) planarizing etching the gate polysilicon layer, the hard mask nitride layer pattern and the oxide spacer of a predetermined thickness; (h) forming a metal layer and a hard mask layer on the entire surface of the semiconductor substrate and then forming a gate by a photolithography process using a gate mask; And (i) forming a source / drain region by removing the hard mask nitride layer pattern and implanting impurities. The method of claim 1, And forming a gate spacer on sidewalls of the hard mask layer, the metal layer, and the oxide film spacer before performing the impurity implantation process in step (i).

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