KR101002047B1 - A method for forming a transistor of a semiconductor device - Google Patents
A method for forming a transistor of a semiconductor device Download PDFInfo
- Publication number
- KR101002047B1 KR101002047B1 KR20030052749A KR20030052749A KR101002047B1 KR 101002047 B1 KR101002047 B1 KR 101002047B1 KR 20030052749 A KR20030052749 A KR 20030052749A KR 20030052749 A KR20030052749 A KR 20030052749A KR 101002047 B1 KR101002047 B1 KR 101002047B1
- Authority
- KR
- South Korea
- Prior art keywords
- oxide film
- spacer
- film
- forming
- nitride
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 49
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 150000004767 nitrides Chemical class 0.000 claims abstract description 32
- 125000006850 spacer group Chemical group 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 13
- 239000004215 Carbon black (E152) Substances 0.000 claims description 6
- 229930195733 hydrocarbon Natural products 0.000 claims description 6
- -1 hydrocarbon fluoride Chemical class 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000002230 thermal chemical vapour deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to a method for forming a transistor of a semiconductor device, to prevent the deterioration of the electrical characteristics of the gate insulating film due to the high integration of the semiconductor device to improve the characteristics of the transistor.
In the present invention, the first oxide film, the nitride film and the second oxide film for the insulating film spacer of the gate electrode are formed by the LTCVD method, and the second oxide film and the nitride film are etched by the anisotropic etching process to form the second oxide film spacer and the nitride film spacer. The first oxide film exposed by the second oxide film spacer and the nitride film spacer is removed by a wet method to form the first oxide film spacer, thereby forming the first oxide film, the nitride film and the second oxide film for the spacer at a high deposition rate at a low temperature, It is a technology for improving the characteristics and reliability of semiconductor devices by forming insulating film spacers without damage.
Description
1A and 1B are cross-sectional views showing a transistor forming method of a semiconductor device according to an embodiment of the prior art.
2A to 2D are cross-sectional views showing a transistor forming method of a semiconductor device in accordance with an embodiment of the present invention.
<Description of Signs of Major Parts of Drawings>
11,31:
15,35 polysilicon layer for
17
21,43: high concentration impurity junction region 37: first oxide film
41: second oxide film
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a transistor of a semiconductor device, and in particular, to prevent the deterioration of characteristics of the semiconductor device by a subsequent heat treatment process. (lightly doped drain, hereinafter referred to as LDD) The present invention relates to a method of forming an insulating film spacer to form a structure.
In order to prevent deterioration of electrical characteristics of the device due to high integration of the semiconductor device, a transistor having an LDD structure is formed.
1A and 1B are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to the prior art.
Referring to FIG. 1A, a trench type isolation layer (not shown) defining an active region is formed on the
The
The stacked structure is etched by a photolithography process using a gate electrode mask (not shown) to form a gate electrode.
The
An
Referring to FIG. 1B, the
At this time, the anisotropic etching process is accompanied by a transient etching, so that the
In a subsequent process, a high concentration of
As described above, in the method of forming a transistor of a semiconductor device according to the related art, thermal stress is applied to a semiconductor substrate due to a high deposition temperature and a slow deposition rate during a deposition process of an oxide film and a nitride film used as an insulating film spacer. In addition, there is a problem in that loss of the semiconductor substrate occurs during the anisotropic etching process for forming the insulating film spacer to reduce the characteristics and reliability of the device, thereby making it difficult to high integration of the semiconductor device.
The present invention is to solve the problems of the prior art, by using low thermal chemical vapor deposition (hereinafter referred to as LTCVD) by forming the insulating layers used as the insulating film spacer at a high deposition rate at a low temperature It is an object of the present invention to provide a method for forming a transistor of a semiconductor device that can prevent deterioration of device characteristics and thereby improve characteristics and reliability of the semiconductor device.
In order to achieve the above object, a method of forming a transistor of a semiconductor device according to the present invention,
Forming a gate electrode on the semiconductor substrate;
Forming an LDD junction region by a low concentration impurity ion implantation process using the gate electrode as a mask;
Forming a first oxide film, a nitride film and a second oxide film on predetermined thicknesses over the entire surface including the gate electrode;
Anisotropically etching the second oxide film to form a second oxide film spacer;
Anisotropically etching the nitride film to form a second oxide film spacer;
Etching the exposed portion of the first oxide film by a wet method to form a first oxide film spacer;
Using the first oxide spacer, the nitride spacer and the second oxide spacer as a mask to form a high concentration impurity junction region on the semiconductor substrate by a high concentration impurity ion implantation process;
The first oxide film, the nitride film and the second oxide film are formed using the LTCVD method,
The first oxide film is formed to a thickness of 100 ~ 150 Å,
The nitride film is formed to a thickness of 200 ~ 300 Å,
The second oxide film is formed to a thickness of 500 ~ 800 Å,
The anisotropic etching process of the second oxide film is performed to have a high etching selectivity difference with the nitride film by using a hydrocarbon fluoride etching gas having a high C / F ratio,
The anisotropic etching process of the nitride film is performed using an etching gas of hydrocarbon fluoride,
The etching process of the first oxide film may be performed using an HF solution.
Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
2A to 2D are cross-sectional views illustrating a method of forming a transistor of a semiconductor device according to the present invention.
Referring to FIG. 2A, a trench type isolation layer (not shown) defining an active region is formed on the
A gate electrode is formed on the
In this case, the gate electrode is formed by stacking the
Next, a low concentration of the
A predetermined thickness of each of the
At this time, the stacked structure of the
Referring to FIG. 2B, the
Here, the anisotropic etching process is performed using a hydrocarbon fluoride etching gas having a high ratio of C / F to have a high etching selectivity difference with the
Referring to FIG. 2C, the
Referring to FIG. 2D, the
Subsequently, a high concentration impurity junction region is formed on the semiconductor substrate by a high concentration impurity ion implantation process using the
As described above, the transistor forming method of the semiconductor device according to the present invention can reduce the stress caused by the heat induced during the deposition process to prevent deterioration of the characteristics of the device, and the gas can be adjusted to control the CD of the insulating film spacer LDD It is possible to freely adjust the junction area and prevent damage to the substrate, thereby improving the characteristics and reliability of the device.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20030052749A KR101002047B1 (en) | 2003-07-30 | 2003-07-30 | A method for forming a transistor of a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20030052749A KR101002047B1 (en) | 2003-07-30 | 2003-07-30 | A method for forming a transistor of a semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20050014228A KR20050014228A (en) | 2005-02-07 |
| KR101002047B1 true KR101002047B1 (en) | 2010-12-17 |
Family
ID=37225393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR20030052749A KR101002047B1 (en) | 2003-07-30 | 2003-07-30 | A method for forming a transistor of a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR101002047B1 (en) |
-
2003
- 2003-07-30 KR KR20030052749A patent/KR101002047B1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| KR20050014228A (en) | 2005-02-07 |
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