KR20070014309A - Method for fabricating transistor of semiconductor device - Google Patents

Abstract

A method for fabricating a transistor in a semiconductor device is provided to form a junction region in a source/drain region by performing an ion implantation process in a bitline region. A first ion implantation process for defining a well is performed on a semiconductor substrate(111). A first photoresist pattern(117) to which a bitline contact region is exposed is formed on the resultant structure. A second ion implantation process(119) is performed by using the first photoresist pattern as an ion implantation mask wherein a C-halo implantation process for forming a C-halo implantation region is performed and a low-density implantation process for forming a low-density source/drain junction region is performed. A second photoresist pattern to which a gate region is exposed is formed on the resultant structure. An etch process using the second photoresist pattern as an etch mask is performed to form a recess gate region in an active region of the semiconductor substrate. A gate pattern and a sidewall spacer are formed on the resultant structure. A third ion implantation process is performed by using the gate pattern and the sidewall spacer as an etch mask.

Description

Method for fabricating transistor of semiconductor device {Method for Fabricating Transistor of Semiconductor Device}

1A-1E are process schematic diagrams illustrating a conventional transistor manufacturing method.

2A-2F are process schematic diagrams illustrating a transistor fabrication method of the present invention.

<Brief description of the main parts of the drawing>

1, 111: semiconductor substrate 3, 113: device isolation region

5, 117, 123: photoresist pattern 7, 127: gate oxide film

9, 129: polycrystalline silicon layer 9-1, 129-1: polycrystalline silicon pattern

11, 131: metal layer 11-1, 131-1: metal layer pattern

13, 133: hard mask film 13-1, 133-1: hard mask film pattern

15, 135: spacer 17: ion implantation process

19, 139: source region 21, 141: drain region

23, 137: polyplug 115: primary ion implantation process

119: secondary ion implantation process 121: ion implantation region

125: recess gate region 136: tertiary ion implantation process

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a transistor of a semiconductor device, wherein a C-halo implantation process and a low concentration ion implantation process for a bit line contact region of a semiconductor substrate are first formed before forming a gate pattern to form a uniform junction region. A method of forming a transistor of an element.

As the field of application of semiconductor devices expands today, there is an urgent need for development of process equipment or process technologies for manufacturing high-capacity semiconductor devices with low manufacturing costs and improved integration and electrical properties. In this regard, various studies have been conducted to obtain devices that perform stable operations by improving cell structures, photo-lithography process conditions, physical property limits of wiring forming materials and insulating film forming materials, and the like.

On the other hand, when a transistor having a reduced physical dimension such as a gate line line width of a semiconductor device or a dielectric film thickness of a gate line due to high integration of a semiconductor device is manufactured, a depletion region of a source / drain region is formed in a channel. Penetrating into, caused a short channel effect that reduces the effective channel length.

As a result of this, it is not only difficult to secure the data retention time of the semiconductor device, but also the subsequent process margin is reduced to increase the junction leakage current.

In order to improve the short channel effect, (i) a method of reducing the thickness of the gate insulating film, (ii) forming a recessed channel region under the gate line to secure an effective channel length for the gate line width, or ( iii) In order to form source / drain regions by implanting impurity ions into a silicon or wafer specific portion under the gate, a method of forming a shallow junction region in order to reduce the depletion region as much as possible has been introduced.

A method of forming a transistor including the (ii) recessed channel gate region in the prior art will be described in detail with reference to the accompanying drawings 1A to 1E.

Referring to FIG. 1A, an isolation region 3 is formed on a semiconductor substrate 1, and then a photoresist film (not shown) is formed on the entire structure.

Exposure and development of the photoresist film (not shown) are performed to form a photoresist pattern 5 including an opening through which a portion of the active region of the semiconductor substrate 1 is exposed, as shown in FIG. 1B. Next, the semiconductor substrate 1 is etched using the photoresist pattern 5 as an etching mask to form a recess gate region.

Subsequently, after removing the photoresist pattern 5 of FIG. 1B, a gate oxide film 7 is formed on the entire structure, as shown in FIG. 1C, and a polycrystalline silicon layer 9 and a metal layer 11 are formed thereon. And a stacked structure in which the hard mask film 13 is sequentially deposited.

The photolithography process of the lamination structure of FIG. 1C is performed to form a polycrystalline silicon layer pattern 9-1, a metal layer pattern 11-1, and a hard mask layer pattern 13-1 as shown in FIG. 1D. After forming the gate pattern, a nitride film is formed on the entire surface of the obtained structure and etched to form sidewall spacers 15.

By using the gate spacer 15 and the gate pattern as an ion implantation process mask, various steps of ion implantation process 17 such as a C-halo process and a low concentration impurity ion implantation or a high concentration impurity ion implantation process for the semiconductor substrate 1 are performed. Next, the source region 19 and the drain region 21 as shown in FIG. 1E are formed.

In this case, the C-halo implantation process, which is one of the various ion implantation processes, is a technique generally used in the fabrication of a CMOS device, and is generally implanted at a 30 to 450 tilt angle to place a dopant directly under the gate electrode.

In addition, a polysilicon layer is formed on the entire surface of the structure to form a poly plug 23 on the source / drain region.

As described above, in a transistor fabrication process including a recess gate region in the related art, misalignment between the recess gate and the gate pattern is different because the substrate specificity etched with the exposure and etching equipment in each etching process step is different. Occurs.

In addition, as the semiconductor devices are increasingly integrated, the effective channel length of the transistor including the recess gate region is also reduced, so that the overlapping area between the source and drain regions is further increased, so that a stable etching process cannot be performed, so that sidewall spacers and the like are not available. The structure of is poorly formed.

Due to such a problem, when performing an ion implantation process such as a C-halo implantation process, as shown in FIG. 1E, the C-halo region that determines the cell voltage VT is formed with a nonuniform profile 21.

As a result, the loading capacitance of the semiconductor device is increased to decrease the transistor speed, and a leakage current occurs between the storage node and the bit line node in a subsequent process, thereby causing a refresh error of the semiconductor device. .

Accordingly, the present inventors have completed the present invention by developing a transistor forming method for forming a stable junction area to perform a stable operation that can overcome the above-mentioned conventional problems without expensive equipment development.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the conventional transistor formation method, and is capable of forming a uniform junction region by performing a C-halo implantation process and a low concentration impurity ion implantation process before the gate pattern formation process. An object of the present invention is to provide a method for forming a transistor of a semiconductor device of concept.

In order to achieve the above object, in the present invention

Performing primary ion implantation to define a well on a semiconductor substrate;

Forming a first photoresist pattern exposing bit line contact regions on the front surface of the structure;

Performing a secondary ion implantation process using the first photoresist pattern as a mask for ion implantation process;

Forming a second photoresist pattern exposing a gate region on the entire surface of the structure;

Forming a recess gate region in an active region of a semiconductor substrate by performing an etching process using the second photoresist pattern as an etching mask;

Forming a gate pattern and sidewall spacers on the structure including the recess gate regions; And

A method of forming a transistor in a semiconductor device, the method including performing a third ion implantation process using the gate pattern and sidewall spacers as an etching mask.

In this case, the secondary ion implantation process may include performing a C-halo implantation process for forming a C-halo implantation region and then performing a low concentration ion implantation process for forming a low concentration source / drain junction region.

In addition, the tertiary ion implantation process may be a step of performing a high concentration ion implantation process for forming a high concentration source / drain region, and may further include performing a general ion implantation process before the sidewall spacer formation process.

Hereinafter, the present invention will be described in detail with reference to the drawings.

First, referring to FIG. 2A, an isolation region 113 is formed on a semiconductor substrate 111, and then a mask layer (not shown) is formed on the entire surface of the semiconductor substrate to form an N-type electric field. A primary ion implantation process 115 is performed to inject boron (B) ions for threshold voltage control of the effect transistor.

A photoresist layer (not shown) is formed on the entire structure of FIG. 2A, and then a development and etching process is performed to form a first photoresist pattern 117 exposing the bit line contact region as shown in FIG. 2B. do.

Subsequently, a secondary ion implantation process 119 is performed to form the ion implantation region 121 using the first photoresist pattern 117 as an ion implantation mask.

The secondary ion implantation process may include a low concentration ion implantation process of forming a low concentration source / drain junction region after the C-halo implantation process of forming a C-halo implantation region.

After removing the first photoresist pattern 117 of FIG. 2B, a photoresist layer (not shown) is formed on the entire surface of the semiconductor substrate 111 on which the ion implantation region 121 is formed, and an exposure and development process is performed to form a gate. The photoresist pattern 123 in which the region is exposed is formed.

An etching process using the photoresist pattern 123 as an etching mask is performed to form the recess gate region 125 on the active region of the semiconductor substrate as shown in FIG. 2C.

After the photoresist pattern 123 of FIG. 2C is removed, an oxidation process is performed on the entire surface including the recess gate region 125 to form a gate oxide layer 127 as shown in FIG. 2D.

At this time, the gate oxide film has a thickness of 55 to 75 kPa, preferably 65 kPa.

In addition, a multilayer structure in which a polycrystalline polysilicon layer 129, a metal layer 131, and a hard mask nitride layer 133 are sequentially formed on the gate oxide layer 127 is formed.

In this case, the polycrystalline polysilicon layer is formed to 800 ~ 900 Å, preferably 850 Å thickness, the metal layer is formed to 900 ~ 1100 Å, preferably 1000 Å thickness, the hard mask nitride film is formed of 1100 ~ 1300 Å, preferably 1200 Å thickness. do.

The photolithography process is performed on the stacked structure of FIG. 2D to the polycrystalline polysilicon layer pattern 129-1, the metal layer pattern 131-1, and the hard mask nitride layer pattern 133-1 as shown in FIG. 2E. A gate pattern is formed.

At this time, even if an alignment error occurs between the recess gate and the gate pattern, since the C-halo region for determining the cell VT is already uniformly formed by the secondary ion implantation process, stable loading capacitance can be obtained. have. In addition, leakage current caused by field differences between the storage node and the bit line node can be improved in subsequent processes.

Next, an insulating film is formed on the entire surface of the structure including the gate pattern and then etched to form sidewall spacers 135.

A third ion implantation process 136 using the gate pattern and the gate spacer 135 of FIG. 2E as a mask for an ion implantation process is performed to form a source region 139 and a drain region 141 as shown in FIG. 2F. Form.

In this case, the tertiary ion implantation process is a high concentration ion implantation process for forming a high concentration source / drain region, and a general ion implantation process may be performed before the sidewall spacer 135 formation process.

All the ion implantation process carried out in the present invention is preferably carried out under the general process conditions used in the conventional ion implantation process.

Subsequently, an insulating film (not shown) is formed on the entire surface of the structure to fill all the gaps between the gate patterns, and a plug having the source / drain regions 139/141 opened by an etching process using a landing plug contact mask (not shown). After forming a contact (not shown), a poly layer is formed on the entire surface of the structure including the plug contact (not shown) and polished to form a poly plug 137.

In addition, the present invention provides a semiconductor device manufactured using the above method.

As described above, in the present invention, an ion implantation process may be performed on the bit line region before forming the gate pattern to obtain a junction region of a uniform source / drain region, so that an alignment error between the recess gate region and the gate pattern may occur. Even if sidewall spacers are poorly formed during the etching process, stable cell VT can be obtained to obtain an improved loading capacitance. In addition, the leakage current caused by the field difference between the storage node and the bit line node in the subsequent process can be improved.

As described above, in the present invention, since the ion implantation process may be performed on the bit line region before formation, the junction region of the uniform source / drain region may be formed, and thus, not only the loading capacitance but also the field difference between the subsequent storage node and the bit line node. The leakage current can be improved.

Claims (5)

Performing primary ion implantation to define a well on a semiconductor substrate; Forming a first photoresist pattern exposing bit line contact regions on the front surface of the structure; Performing a secondary ion implantation process using the first photoresist pattern as a mask for ion implantation process; Forming a second photoresist pattern exposing a gate region on the entire surface of the structure; Forming a recess gate region in an active region of a semiconductor substrate by performing an etching process using the second photoresist pattern as an etching mask; Forming a gate pattern and sidewall spacers on the structure including the recess gate regions; And And performing a tertiary ion implantation process using the gate pattern and the sidewall spacers as an etch mask. The method of claim 1, The secondary ion implantation process may include performing a C-halo implantation process for forming a C-halo implantation region, and then performing a low concentration ion implantation process for forming a low concentration source / drain junction region. A transistor forming method of a semiconductor device. The method of claim 1, The third ion implantation process is a transistor forming method of a semiconductor device, characterized in that for performing a high concentration ion implantation process for forming a high concentration source / drain region. The method of claim 1, And performing a general ion implantation process before the sidewall spacer formation process. A semiconductor device manufactured using the method of claim 1.

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