KR20110091944A - The method for manufacturing semiconductor device - Google Patents

The method for manufacturing semiconductor device Download PDF

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Publication number
KR20110091944A
KR20110091944A KR1020100011313A KR20100011313A KR20110091944A KR 20110091944 A KR20110091944 A KR 20110091944A KR 1020100011313 A KR1020100011313 A KR 1020100011313A KR 20100011313 A KR20100011313 A KR 20100011313A KR 20110091944 A KR20110091944 A KR 20110091944A
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KR
South Korea
Prior art keywords
gate pattern
cell region
gate
forming
spacer
Prior art date
Application number
KR1020100011313A
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Korean (ko)
Inventor
정인승
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020100011313A priority Critical patent/KR20110091944A/en
Publication of KR20110091944A publication Critical patent/KR20110091944A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a short between a contact and a gate pattern on a dummy cell area by securing a SAC(Self-Aligned Contact) margin through spacer materials on the sidewall and top of the gate pattern. CONSTITUTION: A gate pattern(280) is formed on a semiconductor substrate(200) including a cell region(2000a) and a dummy cell(2000b). The first insulating layer is formed on the surface including the gate pattern. A first insulation layer is etched using a mask which partially exposes the sidewall and top of the gate pattern as an etch mask. A spacer(315) is formed on the sidewall and top of the gate pattern. A second insulation layer(320) is formed on the surface including the spacer.

Description

The method for manufacturing semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving short failing between a contact and a gate pattern of a dummy cell region.

One of the most important parameters in the manufacture of transistors of semiconductor devices is the threshold voltage (Vt).

The threshold voltage is a variable that depends on the gate oxide thickness, the channel doping concentration, the oxide charge and the material used for the gate.

As the size of the device decreases, the threshold voltage is inconsistent with theoretical values. The problem currently encountered is the short channel effect that occurs as the gate channel length decreases.

In general, a process of forming a junction area in a semiconductor device manufacturing process forms a light doped drain (LDD) junction before a source / drain junction, in this case, after a gate is formed. Selective oxidation, LDD ion implantation, spacer formation, source drain ion implantation, and rapid thermal annealing (RTA) are performed in this order.

Among the semiconductor devices including the cell region and the dummy cell region, the outermost dummy gate CD (Critical Dimension) is largely formed to form an accurate pattern of the main cell region.

In the case where the outermost dummy gate is partially overlapped with the active region and the device isolation region of the cell region, the lower recess region of each region causes a failure due to the landing plug and short of the upper region. There is a problem.

1A and 1B are cross-sectional views illustrating a problem of a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, an isolation layer 120 defining an active region 110 is formed on a semiconductor substrate 100 having a cell region 1000a and a dummy cell 1000b region.

Next, after the photoresist film is formed on the semiconductor substrate 100, a photoresist pattern (not shown) is formed by an exposure and development process using a mask for forming a recess region. The recessed region 130 is formed by etching the active region 110 and the device isolation layer 120 using the photoresist pattern as a mask.

Next, after the gate polysilicon layer 140, the gate metal layer 150, and the gate hard mask layer 160 are sequentially stacked on the entire surface including the recess region 130, a gate pattern mask is formed as an etch mask. The gate hard mask layer 160, the gate metal layer 150, and the gate polysilicon layer 140 are etched until the substrate 100 is exposed to form the gate pattern 180. In this case, the gate pattern 180 preferably includes spacers 170 formed on sidewalls of the gate pattern 180.

Here, the width X between the gate pattern 180 ′ of the dummy cell region 1000b is wider than the width Y between the gate pattern 180 of the cell region 1000a. Therefore, the loss of the insulating layer 190 and the spacer 170 between the gate pattern 180 ′ of the dummy cell region 1000b is large in the subsequent process of forming a contact (landing plug contact 195). There is a problem that the amount of such loss is excessive and the short-circuit failure between the contact 195 and the lower gate pattern 180 'is continuously generated (see A of FIG. 1B).

In order to solve the above-mentioned conventional problems, the present invention is subsequently formed by forming a spacer material on the sidewalls and the top of the gate pattern of the dummy cell region to make the width between the gates of the dummy cell region equal to the gate width of the cell region. Provided is a method of manufacturing a semiconductor device capable of preventing a short between a contact and a gate pattern of a dummy cell region by securing a self-aligned contact (SAC) margin during the process.

The present invention provides a method of forming a gate pattern on a semiconductor substrate including a cell region and a dummy cell region. Etching the first insulating layer with an etch mask using a mask that partially exposes a portion thereof, forming a spacer on sidewalls and an upper portion of the gate pattern, forming a second insulating layer on the entire surface including the spacer, and contacting And etching the second and first insulating layers until the semiconductor substrate is exposed by a mask, and then filling a conductive material to form a contact.

Preferably, the first and second insulating films are formed of a boro-phospho silicate glass (BPSG) film.

Preferably, forming the spacer on the sidewalls and the upper portion of the gate pattern comprises depositing a spacer material on the entire surface including the gate pattern of the dummy cell region and the spacer material until the first insulating layer is exposed. Etching back.

Preferably, the spacer is formed of a nitride film (Nitride).

The method may further include forming a bit line connected to the contact after the forming of the contact.

Preferably, the width between the gate pattern of the dummy cell region and the width of the gate pattern of the cell region are the same.

The present invention forms a spacer material on the sidewalls and the top of the gate pattern of the dummy cell region to make the width between the gates of the dummy cell region the same as the gate width of the cell region. It is possible to prevent the short between the contact and the gate pattern of the dummy cell region.

1A and 1B are cross-sectional views illustrating a problem of a method of manufacturing a semiconductor device according to the prior art.
2A to 2F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

Referring to FIG. 2A, an isolation layer 220 defining an active region 210 is formed on a semiconductor substrate 200 having a cell region 2000a and a dummy cell 2000b region. In this case, the device isolation layer 220 may be formed of a spin on dielectric (SOD) insulation layer.

Next, after the photoresist film is formed on the semiconductor substrate 200, a photoresist pattern (not shown) is formed by an exposure and development process using a mask for forming a recess region. The recessed region 230 is formed by etching the active region 210 and the device isolation layer 220 using the photoresist pattern as a mask.

Next, the gate polysilicon layer 240, the gate metal layer 250, and the gate hard mask layer 260 are sequentially stacked on the entire surface including the recess region 230, and then a gate pattern mask is formed as an etch mask. The gate pattern 280 is formed by etching the gate hard mask layer 260, the gate metal layer 250, and the gate polysilicon layer 240 until the substrate 200 is exposed. In this case, the gate pattern 280 preferably includes spacers 270 formed on sidewalls of the gate pattern 280.

Next, an insulating film 290 is deposited on the entire surface including the gate pattern 280. In this case, the insulating film 290 is preferably formed of a boro-phospho silicate glass (BPSG) film.

Next, after the photoresist film is formed on the insulating film 290, the photoresist pattern is exposed and developed by using a mask 300 that exposes the dummy gate pattern 280 ′ of the dummy cell region 2000b. To form.

Referring to FIG. 2B, the insulating layer 290 is etched using the photoresist pattern as an etching mask. In this case, the insulating layer 290 is partially etched between the dummy gate patterns 280 ′ of the dummy cell region 2000b without completely removing the insulating layer 290 until the lower semiconductor substrate 200 is exposed. It is preferable. That is, the insulating film 290 of the dummy cell region 2000b and the insulating film 290 of the cell region 2000a have steps.

Referring to FIG. 2C, the spacer material 310 is deposited on the entire surface including the insulating layer 290. In this case, the spacer material 310 may be formed of a nitride film.

Referring to FIG. 2D, the spacer material 310 is etched back until the insulating layer 290 is exposed to form a spacer on the sidewalls and the top of the dummy gate pattern 280 ′ of the dummy cell region 2000b. (Spacer 315) is formed. Here, by forming the spacers 315 between the dummy gate patterns 280 'of the dummy cell region 2000b, the width A between the dummy gate patterns 280' of the dummy cell region 2000b is the cell region 2000a. Self-aligned contact (SAC) margin can be secured by the same or similar width (B) between the gate patterns 280 of the c) and a short defect between the contact and the dummy gate pattern during the subsequent process can be prevented.

Referring to FIG. 2E, an insulating film 320 is further deposited on the entire surface including the spacer 315. In this case, the insulating film 320 is preferably formed of a boro-phospho silicate glass (BPSG) film.

Referring to FIG. 2F, after the photoresist film is formed on the entire surface including the insulating layer 320, a photoresist pattern (not shown) is formed by an exposure and development process using a contact mask. Using the photoresist pattern as a mask, the insulating layer 320 is etched until the semiconductor substrate 200 is exposed to form a contact region (not shown). A contact 330 is formed by filling a conductive material in the contact region.

Thereafter, a bit line 340 connected to the contact 330 is formed.

As described above, the present invention forms a spacer material on the sidewall and the top of the gate pattern of the dummy cell region to make the width between the gates of the dummy cell region equal to the gate width of the cell region. -Aligned Contact Provides a margin to prevent short between the contact and the gate pattern of the dummy cell area.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (6)

Forming a gate pattern on the semiconductor substrate including the cell region and the dummy cell region;
Forming a first insulating film on the entire surface including the gate pattern;
Etching the first insulating layer with an etch mask using a mask partially exposing sidewalls and an upper portion of the gate pattern in the dummy cell region;
Forming a spacer on sidewalls and top of the gate pattern;
Forming a second insulating film on the entire surface including the spacers; And
Etching the second and first insulating layers until the semiconductor substrate is exposed with a contact mask, and then filling a conductive material to form a contact
Method for manufacturing a semiconductor device comprising a. The method of claim 1,
And the first and second insulating layers are formed of a boro-phospho silicate glass (BPSG) film. The method of claim 1,
Forming the spacer
Depositing a spacer material on the entire surface including the gate pattern of the dummy cell region; And
And etching back the spacer material until the first insulating layer is exposed. The method of claim 3, wherein
The spacer is a method of manufacturing a semiconductor device, characterized in that formed by the nitride (Nitride). The method of claim 1,
And forming a bit line connected to the contact after the forming of the contact. The method of claim 1,
And a width between the gate patterns of the dummy cell region and a width between the gate patterns of the cell region is the same.
KR1020100011313A 2010-02-08 2010-02-08 The method for manufacturing semiconductor device KR20110091944A (en)

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KR1020100011313A KR20110091944A (en) 2010-02-08 2010-02-08 The method for manufacturing semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9379001B2 (en) 2013-03-05 2016-06-28 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9379001B2 (en) 2013-03-05 2016-06-28 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same

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