CN103730343A - Semiconductor device structure and manufacturing method thereof - Google Patents
Semiconductor device structure and manufacturing method thereof Download PDFInfo
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- CN103730343A CN103730343A CN201210383005.8A CN201210383005A CN103730343A CN 103730343 A CN103730343 A CN 103730343A CN 201210383005 A CN201210383005 A CN 201210383005A CN 103730343 A CN103730343 A CN 103730343A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000011248 coating agent Substances 0.000 claims description 66
- 238000000576 coating method Methods 0.000 claims description 66
- 238000000034 method Methods 0.000 claims description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 57
- 239000000463 material Substances 0.000 description 12
- 239000012212 insulator Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention discloses a semiconductor device structure and a manufacturing method of the semiconductor device structure. The manufacturing method of the semiconductor device structure comprises the steps of providing a semiconductor substrate; forming a covering layer on the semiconductor substrate, wherein the covering layer is provided with an opening, first regions and a second region of the semiconductor substrate are exposed by the opening, the first regions are arranged on the two sides of the second region respectively, and the first regions correspond to a region of overlap between a grid electrode and a source electrode and a region of overlap between the grid electrode and a drain electrode respectively; forming a first grid oxide layer on the first regions and the second region arranged on the semiconductor substrate; removing the portion, arranged on the second region, of the first grid oxide layer; forming a second grid oxide layer on the second regions, wherein the thickness of the second grid oxide layer is smaller than that of the first grid oxide layer. According to the manufacturing method of the semiconductor device structure, the frequency of the phenomenon that GIDL currents are generated at the position of overlap between the grid electrode and the source electrode and/or the position of overlap between the grid electrode and the drain electrode can be reduced, even the phenomenon that the GIDL currents are generated at the position of overlap between the grid electrode and the source electrode and/or the position of overlap between the grid electrode and the drain electrode can be avoided, performance of a central region of a channel is ensured, and then the purpose that performance of an MOS device is not affected is achieved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of semiconductor device structure and preparation method thereof.
Background technology
Owing to having very large overlapping region between the grid of metal oxide semiconductor field effect tube (Metal Oxide Semiconductor Field Effect Transistor, MOSFET) and drain electrode.As shown in Figure 1, A represented region in region is the overlapping region between grid 101 and drain electrode 103.Take NMOSFET as example, after grid 101 applies voltage, drain electrode 103 electromotive forces in NMOSFET than grid 101 electromotive forces corrigendums to, in the A of region, the effect due to grid 101 voltages can produce hole, the hole forming will be moved through depletion region in substrate 100, and forming substrate current, this electric current is commonly called grid induction drain leakage (Gate-induced drain leakage, GIDL) electric current.Otherwise, after grid applies voltage, grid potential in PMOSFET than drain potentials corrigendum to, in grid 101 and overlapping between 103 of draining, the effect due to grid 101 voltages can produce electronics, electronics will move and form GIDL electric current through depletion region in substrate.
Along with day by day dwindling of dimensions of semiconductor devices, the thickness of gate oxide is more and more thinner, and the electrical potential difference between grid 101 and drain electrode 103 is larger, causes GIDL electric current to increase.In the deep-submicron epoch, numerous integrity problems that GIDL electric current causes become further serious.For example, GIDL electric current may affect reliability and the power consumption of undersized MOSFET, GIDL electric current also has material impact to the erasable operation of the memory devices such as electricallyerasable ROM (EEROM) (Electrically Erasable Programmable Read-Only Memory, EEPROM) simultaneously.
For fear of the overlapping between grid and source/drain, produce GIDL electric current, can increase the thickness of the gate oxide layers of grid 101, to reduce the electric field between grid 101 and source electrode 102/ drain electrode 103, and then reduce GIDL electric current.Yet, although it is favourable to avoiding producing GIDL electric current to increase the thickness of gate oxide layers, but damaged the performance of MOS device.
Therefore, need a kind of manufacture method of semiconductor device, to solve problems of the prior art.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The manufacture method that the invention discloses a kind of semiconductor device structure, comprising: Semiconductor substrate a) is provided; B) in described Semiconductor substrate, form the cover layer with opening, described opening exposes first area and the second area of described Semiconductor substrate, described first area is positioned at the both sides of described second area, and described first area is corresponding to the overlapping region of grid and source electrode and drain electrode; C) the described first area in described Semiconductor substrate and described second area form first grid oxide skin(coating); D) remove the described first grid oxide skin(coating) on described second area; And e) on described second area, form second gate oxide skin(coating), the thickness of described second gate oxide skin(coating) is less than the thickness of described first grid oxide skin(coating).
Preferably, described cover layer comprises the oxide skin(coating) being formed in described Semiconductor substrate and is formed on the nitride layer on described oxide skin(coating).
Preferably, the thickness of described oxide skin(coating) is less than or equal to the thickness of described first grid oxide skin(coating), and is more than or equal to the thickness of described second gate oxide skin(coating).
Preferably, described d) step comprises: on described cover layer, on described first grid oxide skin(coating) and on the sidewall of described opening, form the first polysilicon layer; And adopt dry etch process to carry out etching to described the first polysilicon layer and described first grid oxide skin(coating), to form the first clearance wall on the sidewall of described opening, described the first clearance wall covers described first area and exposes described second area.
Preferably, described method is at described e) also comprise after step: the second polysilicon layer that forms the remainder that fills up described opening in described Semiconductor substrate; Remove described cover layer, to form described grid.
Preferably, described method also comprises after forming described grid: carry out shallow doping ion implantation technology, to form shallow doped region in the described Semiconductor substrate in described grid both sides; In described grid both sides, form the second clearance wall; Carry out source-drain electrode ion implantation technology, to form described source electrode and described drain electrode in the described Semiconductor substrate in described grid both sides.
Preferably, described first grid oxide layer and described second gate oxide layer are to adopt thermal oxidation method to form.
Preferably, the thickness of described first grid oxide skin(coating) is 30 dust-500 dusts.
Preferably, the thickness of described second gate oxide skin(coating) is 20 dust-200 dusts.
The present invention also provides a kind of semiconductor device structure, and described semiconductor device structure adopts any method as mentioned above to form.
The present invention is by forming respectively the different gate oxide layers of thickness at corresponding grid from the first area of the overlapping region of source electrode and drain electrode and the second area of corresponding channel region, when can reduce, even avoid the overlapping generation GIDL electric current between grid and source/drain, guarantee the performance of raceway groove central area, and then reach the object that the performance of MOS device is not exerted an influence.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the schematic diagram that forms the principle of GIDL electric current;
Fig. 2 makes the process chart of semiconductor device structure according to one embodiment of the present invention;
Fig. 3 A-3N is according to the cutaway view of the device that in the technological process of one embodiment of the present invention making semiconductor device, each step obtains.
Embodiment
Next, in connection with accompanying drawing, the present invention is more intactly described, shown in the drawings of embodiments of the invention.But the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties.
Fig. 2 makes the process chart of semiconductor device structure according to one embodiment of the present invention, Fig. 3 A-3N is according to the cutaway view of the device that in the technological process of one embodiment of the present invention making semiconductor device, each step obtains.Below in conjunction with Fig. 2 and Fig. 3 A-3N, describe method of the present invention in detail.
First, execution step 201, provides Semiconductor substrate.
As shown in Figure 3A, provide Semiconductor substrate 300.Semiconductor substrate 300 can be at least one in following mentioned material: stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.In Semiconductor substrate 300, can be defined active area.In addition, in Semiconductor substrate 300, can be formed with isolation structure (not shown), described isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure etc.In order to simplify, only with a blank, represent Semiconductor substrate 300 herein.
Then, execution step 202 forms the cover layer with opening, the first area of opening exposing semiconductor substrate and second area in Semiconductor substrate, first area is positioned at the both sides of second area, and first area is corresponding to the overlapping region of grid and source electrode and drain electrode.
As shown in Figure 3 B, in Semiconductor substrate 300, be formed with the cover layer 310 with opening 320, first area A and the second area B of opening 320 exposing semiconductor substrates 300.Cover layer 310 can be that any materials of being commonly used by this area is made, and cover layer 310 can be single layer structure, also can be sandwich construction, as long as it can form the opening 320 of exposing semiconductor substrate 300 within it, and can independently the part between opening 320 be removed in subsequent technique.First area A is positioned at the both sides of second area B.First area A is corresponding to the overlapping region of grid (not shown) to be formed and source electrode (not shown) to be formed and drain electrode (not shown), and second area B is corresponding to the channel region of grid below to be formed.Hereinafter will engage an execution mode provided by the invention is described in detail the formation method of grid, source electrode and drain electrode.
Preferably, cover layer 310 comprises the oxide skin(coating) 301 being formed in Semiconductor substrate 300 and is formed on the nitride layer 302 on oxide skin(coating) 301.Nitride layer 302 has higher etching selection ratio with the polycrystalline silicon material forming subsequently, therefore can guarantee preferably to obtain predetermined etching pattern.Below nitride layer 302, forming oxide skin(coating) 301 can avoid, in the process of removing nitride layer 302, Semiconductor substrate 300 is caused to damage.Consider the effect of oxide skin(coating) 301 in above-mentioned technical process, preferably, the thickness of oxide skin(coating) 301 can be suitable with the thickness of the first grid oxide skin(coating) forming subsequently and second gate oxide skin(coating), for example the thickness of oxide skin(coating) 301 can be less than or approximate the thickness of first grid oxide skin(coating), and is greater than or approximates the thickness of second gate oxide skin(coating).
Then, execution step 203, the first area in Semiconductor substrate and second area form first grid oxide skin(coating).
As shown in Figure 3 C, on the surface of the Semiconductor substrate in opening 320 300, form first grid oxide skin(coating) 303.First grid oxide skin(coating) 303 covers on first area A and second area B.As example, first grid oxide skin(coating) 303 can make to adopt thermal oxidation method to form.Because first grid oxide skin(coating) 303 is mainly used in forming the gate oxide layers of the overlapping region of grid and source electrode and drain electrode, therefore, the thickness of first grid oxide skin(coating) 303 can be relatively large, for example, can be 30 dust-500 dusts.
Then, execution step 204, removes the first grid oxide skin(coating) on second area.
The method of the first grid oxide skin(coating) on removal second area has multiple, and according to an aspect of the present invention, this removal method comprises the following steps:
As shown in Figure 3 D, on cover layer 310, form the first polysilicon layer 304 on first grid oxide skin(coating) 303 and on the sidewall of opening 320.That is to say, on the semiconductor device structure obtaining in step 203, form the first polysilicon layer 304 that covers this semiconductor device structure.As example, the formation method of the first polysilicon layer 304 can comprise chemical vapour deposition technique, physical vaporous deposition, magnetron sputtering method or atomic layer deposition method etc.Because the first polysilicon layer 303 forms and covers the upper clearance wall of first area A for the etching technics through subsequently, therefore, should, according to the area of the overlapping region of grid to be formed and source electrode and drain electrode, the thickness of the first polysilicon layer 303 be reasonably set.
As shown in Fig. 3 E, adopt dry etch process to carry out etching to the first polysilicon layer 303 and first grid oxide skin(coating) 304, to form the first clearance wall 305, the first clearance walls 305 on the sidewall at opening 320, cover first area A and expose second area B.The etching gas that this dry etch process is used can be the gas that etch polysilicon material and oxide material are often used respectively, for the technological parameter of etching technics, those skilled in the art can carry out choose reasonable according to the size characteristics of each parts on the semiconductor device of actual fabrication.As long as this dry etch process can make the first clearance wall 305 after etching cover first area A and expose second area B.
Finally, execution step 205 forms second gate oxide skin(coating) on second area, and the thickness of this second gate oxide skin(coating) is less than the thickness of first grid oxide skin(coating).
The thickness of second gate oxide skin(coating) can be relatively little, for example, can be 20 dust-200 dusts.Method provided by the invention is by first removing the first grid oxide layer of second area, and then at second area, again forming the second gate oxide skin(coating) that thickness is less than first grid oxide skin(coating) can be so that controls the thickness of second gate oxide skin(coating) exactly.
As example, second gate oxide skin(coating) can adopt thermal oxidation method to form.Reference is according to an above-mentioned embodiment that aspect provides of the present invention, as shown in Fig. 3 F, because the first clearance wall 305 comprises thinner first grid oxide skin(coating) and the first thicker polysilicon layer, therefore, when adopting thermal oxidation method to form second gate oxide skin(coating), on the second area B in Semiconductor substrate 300, form second gate oxide skin(coating) 306, second gate oxide skin(coating) 306 also can cover side and the upper surface of the exposure of the first clearance wall 305.Due to the channel region of second area B corresponding to grid below, the thickness that therefore makes the thickness of the second gate oxide skin(coating) 306 on second area B be less than the first grid oxide skin(coating) on the A of first area can guarantee the performance of raceway groove central area.
The present invention is by forming respectively the different gate oxide layers of thickness at corresponding grid from the first area of the overlapping region of source electrode and drain electrode and the second area of corresponding channel region, when can reduce, even avoid the overlapping generation GIDL electric current between grid and source/drain, guarantee the performance of raceway groove central area, and then reach the object that the performance of MOS device is not exerted an influence.
Further, according to another aspect of the present invention, method provided by the invention is further comprising the steps of after forming second gate oxide skin(coating): the second polysilicon layer that forms the remainder that fills up opening in Semiconductor substrate; And removal cover layer, to form grid.
As shown in Fig. 3 G, on the semiconductor device structure forming in upper step, form polysilicon material layer 307.Polysilicon material layer 307 fills up the remainder of opening 320, and covers the polysilicon material layer 307 beyond opening 320.The formation method of polysilicon material layer 307 can comprise chemical vapour deposition technique, physical vaporous deposition, magnetron sputtering method or atomic layer deposition method etc.
As shown in Fig. 3 H, adopt flatening process (for example chemical mechanical milling tech) to remove opening 320 polysilicon material layer 307 in addition, to form the second polysilicon layer 308 of the remainder that fills up opening 320 in Semiconductor substrate 300.
When cover layer 310 comprises oxide skin(coating) 301 and nitride layer 302, the step of removing cover layer 310 comprises: first, as shown in Fig. 3 I, remove nitride layer 302, the method for removing nitride layer 302 is for example dry etching or wet etching; Then, as shown in Fig. 3 J, remove oxide skin(coating) 301, to form grid, grid comprises the first clearance wall 305, the second polysilicon layer 308 and is positioned at second gate oxide skin(coating) 306 between the two.Because this step is relevant with the structure and material of cover layer 310, therefore, the structure and material of the cover layer 310 that those skilled in the art can adopt according to it selects suitable technique that cover layer 310 is removed.
In addition, the method also comprises after forming grid: carry out shallow doping ion implantation technology, to form shallow doped region 309A and 309B(in the Semiconductor substrate 300 in grid both sides as shown in Fig. 3 K); In grid both sides, form the second clearance wall 312(as shown in Fig. 3 L); Carry out source-drain electrode ion implantation technology, to form source electrode 311A and drain electrode 311B(in the Semiconductor substrate 300 in grid both sides as shown in Fig. 3 M).
Further, as shown in Fig. 3 N, the method is also included in the upper metal silicide 313 that forms of grid and source electrode 311A and drain electrode 311B.Particularly, can on the semiconductor device structure shown in Fig. 3 M, form metal level, for example nickel (Ni); Then carry out thermal annealing, so that grid and source electrode 311A and the drain electrode 311B metal level surperficial with it react, form metal silicide 313; Finally, remove the metal level not reacting of remainder.
Another aspect according to the present invention, also provides a kind of semiconductor device structure, and this semiconductor device structure is to adopt above-mentioned method described in any to form.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device structure, is characterized in that, comprising:
A) provide Semiconductor substrate;
B) in described Semiconductor substrate, form the cover layer with opening, described opening exposes first area and the second area of described Semiconductor substrate, described first area is positioned at the both sides of described second area, and described first area is corresponding to the overlapping region of grid and source electrode and drain electrode;
C) the described first area in described Semiconductor substrate and described second area form first grid oxide skin(coating);
D) remove the described first grid oxide skin(coating) on described second area; And
E) on described second area, form second gate oxide skin(coating), the thickness of described second gate oxide skin(coating) is less than the thickness of described first grid oxide skin(coating).
2. manufacture method as claimed in claim 1, is characterized in that, described cover layer comprises the oxide skin(coating) being formed in described Semiconductor substrate and is formed on the nitride layer on described oxide skin(coating).
3. method as claimed in claim 2, is characterized in that, the thickness of described oxide skin(coating) is less than or equal to the thickness of described first grid oxide skin(coating), and is more than or equal to the thickness of described second gate oxide skin(coating).
4. manufacture method as claimed in claim 1, is characterized in that, described d) step comprises:
On described cover layer, on described first grid oxide skin(coating) and on the sidewall of described opening, form the first polysilicon layer; And
Adopt dry etch process to carry out etching to described the first polysilicon layer and described first grid oxide skin(coating), to form the first clearance wall on the sidewall of described opening, described the first clearance wall covers described first area and exposes described second area.
5. manufacture method as claimed in claim 4, is characterized in that, described method is at described e) also comprise after step:
In described Semiconductor substrate, form the second polysilicon layer of the remainder that fills up described opening;
Remove described cover layer, to form described grid.
6. method as claimed in claim 5, is characterized in that, described method also comprises after forming described grid:
Carry out shallow doping ion implantation technology, to form shallow doped region in the described Semiconductor substrate in described grid both sides;
In described grid both sides, form the second clearance wall;
Carry out source-drain electrode ion implantation technology, to form described source electrode and described drain electrode in the described Semiconductor substrate in described grid both sides.
7. the method for claim 1, is characterized in that, described first grid oxide layer and described second gate oxide layer are to adopt thermal oxidation method to form.
8. the method for claim 1, is characterized in that, the thickness of described first grid oxide skin(coating) is 30 dust-500 dusts.
9. the method for claim 1, is characterized in that, the thickness of described second gate oxide skin(coating) is 20 dust-200 dusts.
10. a semiconductor device structure, is characterized in that, described semiconductor device structure is to adopt in claim 1-9 the method described in any to form.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111627992A (en) * | 2020-06-05 | 2020-09-04 | 福建省晋华集成电路有限公司 | Grid structure and manufacturing method thereof |
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| US20070145496A1 (en) * | 2005-12-28 | 2007-06-28 | Eun Jong Shin | Semiconductor device and method of manufacturing the same |
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| US20030082861A1 (en) * | 2001-10-29 | 2003-05-01 | Nec Corporation | Method for fabricating a MOSFET |
| US20070145496A1 (en) * | 2005-12-28 | 2007-06-28 | Eun Jong Shin | Semiconductor device and method of manufacturing the same |
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| CN111627992A (en) * | 2020-06-05 | 2020-09-04 | 福建省晋华集成电路有限公司 | Grid structure and manufacturing method thereof |
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| CN103730343B (en) | 2016-08-03 |
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