CN102194749B - Method for making complementary type metal-oxide semiconductor device - Google Patents
Method for making complementary type metal-oxide semiconductor device Download PDFInfo
- Publication number
- CN102194749B CN102194749B CN 201010124461 CN201010124461A CN102194749B CN 102194749 B CN102194749 B CN 102194749B CN 201010124461 CN201010124461 CN 201010124461 CN 201010124461 A CN201010124461 A CN 201010124461A CN 102194749 B CN102194749 B CN 102194749B
- Authority
- CN
- China
- Prior art keywords
- oxide layer
- layer
- grid
- etching
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention provides a method for making a complementary type metal-oxide semiconductor device, which comprises the following steps of: a, providing a first device and a second device with the type opposite to that of the first device, wherein the first device is provided with a first grid electrode, the second device is provided with a second gird electrode, first oxidization layers are formed above the first device and the second device, and high-stress layers are formed above the first oxidization layers; b, using the first oxidization layers as etching stop layers and removing the high-stress layer above the first device; c, annealing; d, using the first oxidization layers as etching stop layers and removing the high-stress layer above the first device; e, forming a mask layer above the second device; and f, etching the oxidization layer above the first device so that the top of the first oxidization layer above the first device is aligned to the top of the residual first oxidization layer above the second device, and then removing the mask layer.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly make the method for CMOS (Complementary Metal Oxide Semiconductor) device.
Background technology
The making of integrated circuit need to form a large amount of circuit elements according to the circuit layout of appointment on given chip area.Consider service speed, power consumption and cost-efficient excellent specific property, CMOS (CMOS (Complementary Metal Oxide Semiconductor)) technology is one of the most promising method for making complicated circuit at present.When using the integrated circuit of COMS fabrication techniques complexity, there are millions of transistors (for example, N channel transistor and p channel transistor) to be formed on the substrate that comprises crystalline semiconductor layer.No matter be N channel transistor or p channel transistor, the CMOS transistor all contains so-called PN junction, and PN junction is by following both interface formation: the drain/source region of high-concentration dopant and be disposed at this drain region and this source area between the counter-doping raceway groove.
In the CMOS transistor arrangement, use near the conductance that is formed at channel region and controls channel region by thin dielectric layer with the gate electrode of this channel region separation, for example control the current drive capability of conducting channel.After applying suitable control voltage formation conducting channel on gate electrode, the conductance of channel region depends on the mobility of doping content and most electric charge carriers.For the given extension of transistor width direction, the conductance of channel region depends on the distance between source area and drain region for channel region, and this distance also is known as channel length.Therefore, the conductance of channel region is the principal element that determines the CMOS performance of transistors.Therefore, the channel resistance rate that reduces channel length and reduce to be associated with channel length becomes to improve the important design criteria of integrated circuit operation speed.
Yet, thereby reducing channel length, lasting reduction transistor size can bring problems, for example the controllability of raceway groove reduces (this is also referred to as short-channel effect).These problems must be overcome, and progressively reduce the resulting advantage of CMOS transistor channel length in order to avoid exceedingly balance out.In addition, continuing to reduce critical size (for example, transistorized grid length) also needs the technology that adapts or the more complicated technology of exploitation to be used for compensate for short channel effects, therefore can be more and more difficult from technological angle.Proposed at present to improve transistorized switching speed from another angle, namely by increase the electronic carrier mobility of raceway groove for given channel length.The method of this raising carrier mobility can avoid or delay at least with the technique that is associated of device scaled size in many problems of running into.
An effective mechanism that is used for increasing charge carrier mobility is the lattice structure that changes in raceway groove, for example pass through producing stretching or compression stress near channel region in order to produce corresponding strain in raceway groove, and stretching or compression can cause respectively the change of electronics and hole mobility.For example, with regard to the crystal orientation of standard, produce along orientation the mobility that uniaxial tensile strain can increase electronics in channel region, wherein, depend on the size and Orientation of elongation strain, can increase mobility and reach 50 or more percent.The increase of mobility can directly change into the raising of conductance.On the other hand, with regard to the channel region of P transistor npn npn, uniaxial compressive can increase the mobility in hole, thereby improves the conductance of P transistor npn npn.It seems at present, is extremely promising method for the next-generation technology node in introduction of stress in production of integrated circuits or strain gauge technique.Because, it is the semi-conducting material of a kind of " novel " that strained silicon can be considered, this make manufacturing speed faster semiconductor device become may and do not need the in addition expensive novel semiconductor material of exploitation, simultaneously also can compatible institute at present the general semiconductor technology manufacturing technology of use.
Generation stretching or compression stress have several modes near transistorized channel region, such as using permanent stress cover layer, wall element etc. to produce external stresses, in order to produce needed strain in raceway groove.Although these methods seem very effective prospect that also has very much, but for such as provide with contact layer, clearance wall (spacer) etc. external stress to the raceway groove when producing needed strain, apply the technique that external stress produces strain and may depend on the efficient of answering force transfer mechanism.Therefore, for different transistor types, must provide different stress cover layers, this can cause increasing a plurality of extra processing steps.Particularly, if the processing step that increases is lithography step, whole production cost is significantly increased.
Therefore, the technology in channel region generation strain of more generally using at present is the technology of a kind of being called as " stress memory (SMT) ".In the intermediate fabrication stage of semiconductor device, form a large amount of amorphized areas near gate electrode, then form stressor layers above transistor area, under the existence of this stressor layers, can make this amorphized areas recrystallization.During being used for making the annealing process of lattice recrystallization, under the stress that this stressor layers produces, strained lattice can be grown up and produce to crystal.After recrystallization, removable this stressor layers (therefore this stressor layers is also referred to as " sacrifice " stressor layers), and still can keep some dependent variables in the lattice part of recrystallization.Although the mechanism that this effect produces is understood at present not yet fully, but great many of experiments confirms, this strain can produce the strain of a certain degree in the polysilicon gate electrode that covers, even after the layer (being sacrificial stress layer) of initiation stress removed, still can exist.Because grid structure after removing this primary stress layer is still being kept some dependent variable, corresponding strain also can be transferred to the crystal block section of growing up again, thereby also can keep certain a part of initial strain.
This stress memory technique is conducive to be combined with other " permanent " strain initiating accident sequence, for example is subjected to the contact etching stopping layer of stress, strained embedded semiconductor material etc., in order to increase the whole efficiency of strain initiating mechanism.But, this may need extra lithography step to carry out composition to the extra sacrificial stress layer relevant with transistor types, thereby whole production cost is increased.Stress memory technique can bring out the channel region of stress and MOSFET, improves whereby the element characteristics of advanced technologies (for example 65 nanometer technologies).
Early stage cmos element is comprised of metal gate layers, gate silicon oxide dielectric layer and semiconductor silicon substrate.But because most metal is not good for the adhesive force of silica, present grid layer is made mainly with polysilicon greatly.But, use polysilicon but to derive other problem, for example element efficiency is because of the too high variation of resistance of polysilicon.So currently used mode is to carry out silicification technics after element forms, with formation layer of metal silicide on grid layer and source/drain regions, thus the resistance of reduction element.On the other hand, usually can divide into major component district and periphery circuit region on a wafer, wherein be arranged in the element in major component district such as comprising memory cell, ESD protection circuit etc.Due to the element that is arranged in the major component district, the element in periphery circuit region needs higher resistance.Therefore, when carrying out above-mentioned silicification technics, need one deck barrier layer will not need to form the partial coverage of metal silicide.The zone that particularly covers due to the barrier layer does not need additionally to cover other rete again, can avoid the generation of silicification reaction, so the barrier layer is called again the self-aligned silicide barrier layer.Self-aligned silicide (SAB) technique is a kind of technique of making the self-aligned silicide barrier layer commonly used in semiconductor fabrication, it can produce low-impedance silicide on the surface of source electrode, drain electrode and grid, thereby significantly reduces this regional spurious impedance.
The method of traditional employing SMT and SAB fabrication techniques cmos device is as shown in Figure 1A to 1G.
At first, as shown in Figure 1A, one substrate 101 is provided, this substrate 101 has thereon and to form and by shallow trench spaced PMOS device 103 and nmos device 104, PMOS device 103 and the common cmos device that consists of of nmos device 104, have trench liner layer 133 on the bottom of shallow trench and sidewall, and be filled with insulant layer 134 in shallow trench.The first grid 130 of PMOS device 103 and the second grid 131 of nmos device 104 are formed at respectively PMOS device 103 and nmos device 104 zones.First grid 130 comprises first grid oxide layer 105A and first grid material layer 106A, and second grid 131 comprises second gate oxide layer 105B and second grid material layer 106B.First grid oxide layer 105A and second gate oxide layer 105B are formed in substrate 101.First grid material layer 106A and second grid material layer 106B are formed at respectively on first grid oxide layer 105A and second gate oxide layer 105B, and the material of gate material layers can be but be not limited to polysilicon.Form clearance wall insulating barrier 109A, 109A ' on the sidewall of first grid 130, form clearance wall insulating barrier 109B, 109B ' on the sidewall of second grid 131, material can be but be not limited to silica.Deposition and etching form gap parietal layer 108A, the 108A ' of PMOS device 103 and gap parietal layer 108B, the 108B ' of nmos device 104, and the material of gap parietal layer can be but be not limited to silicon nitride.Carry out ion implantation technology, form the source of PMOS device 103/ drain electrode 107A, 107A's ' and nmos device 104 source/ drain electrode 107B, 107B '.
Then, as shown in Figure 1B, deposition the first oxide layer 110 above total, material can be but be not limited to silica, thickness is approximately 120～140 dusts.Then, form one deck high stress layer 111 above the first oxide layer 110.
Then, as shown in Fig. 1 C, coating one deck photoresist layer 140 above nmos device 104 zones namely exposes PMOS device 103 zones, and take the first oxide layer 110 as etching barrier layer, etching is removed the high stress layer 111 of PMOS device 103 tops, zone.Then carry out annealing steps, stress is remembered in nmos device 104 zones.
Next, as shown in Fig. 1 D, remove photoresist layer 140 in the ashing mode, and take the first oxide layer 110 as etching barrier layer, etching is removed at the regional remaining high stress layer 111 of nmos device 104.
Then, as shown in Fig. 1 E, deposition forms the second oxide layer 112 above total, and material can be but be not limited to silica, and thickness is approximately 180～220 dusts, is preferably 200 dusts.
Then, as shown in Fig. 1 F, deposition forms the figuratum photoresist layer (not shown) of tool above the second oxide layer 112, and carries out etching technics, remove part the second oxide layer 112 and the first oxide layer 110, to reserve the position that will form metal level in the future.Then after removing the figuratum photoresist layer (not shown) of tool, the position of reserving on first grid 130 and second grid 131 forms metal level 113A and 113B.
At last, as shown in Fig. 1 G, etching is removed remaining the second oxide layer 112 and remaining the first oxide layer 110.
Yet above-mentioned traditional employing SMT and the method for SAB combination are made the situation generation that cmos device can cause overetch, and this does not expect.This be due to, when removing the high stress layer 111 in PMOS device 103 zones take the first oxide layer 110 as the etching barrier layer etching, in order to guarantee that this regional high stress layer can thoroughly be removed, can adopt the method for over etching.That is, also to continue etching a period of time even etched into the first oxide layer 110.And when etching is removed the high stress layer 111 in nmos device 104 zones, the first oxide layer 110 above PMOS device 103 zones also is etched in this process and removes a part, like this, when whole high stress layer 111 all is removed, the first oxide layer 110B thickness partly that the thickness that the first oxide layer 110A part that PMOS device 103 keeps above can occur and nmos device 104 keep above differs a lot of situation, as shown in Figure 2.like this when proceeding to the step of removing whole remaining the first oxide layer 110A and 110B, for the first oxide layer 110A and the 110B that thoroughly clears all, when the first oxide layer 110B layer removal above nmos device 104 zone when clean, PMOS device 103 zones are because the first oxide layer 110A is less than the first oxide layer 110B thickness, the over etching situation can occur, it is first grid 130, clearance wall insulating barrier 109A and 109A ', gap parietal layer 108A and 108A ', substrate 101 and insulant 134 all might be subject to damage to a certain extent, the deviation that causes the device critical size, can reduce the overall performance of semiconductor device like this, reduce yields, this situation does not wish to see.
In addition, due to when removing the high stress layer 111 in nmos device 104 zones, PMOS device 103 zones expose, and because also be coated with high stress layer 111 on nmos device 104 this moment, nmos device 104 differs too many with the height of PMOS device 103, it is excessive that total rises and falls, and can't form the figuratum photoresist of tool, the first oxide layer 110A on eating away PMOS device 103 in the same time not when stopping the high stress layer 111 of removing nmos device 104 zones.Therefore, need a kind of method, can effectively solve the problem that deviation appears in the critical size that causes due to over etching, in order to improve the overall performance of semiconductor device, improve yields.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The problem that occurs deviation in order to solve the critical size that causes due to over etching, the present invention proposes a kind of method of making the CMOS (Complementary Metal Oxide Semiconductor) device, comprise the following steps: a: provide the first device and second device opposite with described the first type of device, described the first device has first grid, described the second device has second grid, the top of described the first device and the second device is formed with the first oxide layer, and the top of described the first oxide layer is formed with high stress layer; B: take described the first oxide layer as etching barrier layer and remove the described high stress layer of described the second device top; C: carry out annealing process; D: take described the first oxide layer as etching barrier layer and remove the described high stress layer of described the first device top; E: form mask layer above described the second device; F: the described oxide layer of etching described the first device top, make the top of remaining described the first oxide layer above top and described second device of described the first oxide layer of described the first device top concordant, then remove described mask layer.
Preferably, also comprise the following steps: g: deposition the second oxide layer above remaining described the first oxide layer; H: the second oxide layer on the described first grid of etching and described second grid and described remaining described the first oxide layer, expose described first grid and described second grid; I: form metal level on described first grid and described second grid; J: remove remaining all described the first oxide layer and described the second oxide layers.
Preferably, the method for the described oxide layer above described etching the first device is etch back process.
Preferably, the thickness of described formation the first oxide layer is 125～145 dusts.
Preferably, the thickness of described formation the first oxide layer is 130 dusts.
Preferably, the thickness of described formation high stress layer is 450～550 dusts.
Preferably, the thickness of described formation high stress layer is 500 dusts.
Preferably, described the first device and described the second device are selected from nmos device or PMOS device.
According to the present invention, can effectively solve the problem that deviation appears in the critical size that causes due to over etching, in order to improve the overall performance of semiconductor device, improve yields.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A to Fig. 1 G is the method for traditional employing SMT and SAB fabrication techniques cmos device;
Fig. 2 is the schematic diagram that in traditional making cmos device technique, deviation appears in the first oxidated layer thickness;
Fig. 3 A to Fig. 3 H is the method according to employing SMT of the present invention and SAB fabrication techniques cmos device;
Fig. 4 A and 4B make according to the employing SMT of the embodiment of the present invention and the process chart of SAB fabrication techniques cmos device.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and be implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, in order to illustrate that the present invention is that the technique of how making cmos device by improvement solves the problem that over etching causes in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
With reference to Fig. 3 A to Fig. 3 H, show the generalized section according to employing SMT of the present invention and SAB fabrication techniques cmos device 300.
At first, as shown in Figure 3A, one substrate 301 is provided, this substrate 301 has thereon and to form and by shallow trench spaced PMOS device 303 and nmos device 304, PMOS device 303 and the common cmos device 300 that consists of of nmos device 304, have trench liner layer 333 on the bottom of shallow trench and sidewall, and be filled with insulant layer 334 in shallow trench.The first grid 330 of PMOS device 303 and the second grid 331 of nmos device 304 are formed at respectively PMOS device 303 and nmos device 304 zones.First grid 330 comprises first grid oxide layer 305A and first grid material layer 306A, and second grid 331 comprises second gate oxide layer 305B and second grid material layer 306B.First grid oxide layer 305A and second gate oxide layer 305B are formed in substrate 301.First grid material layer 306A and second grid material layer 306B are formed at respectively on first grid oxide layer 305A and second gate oxide layer 305B, and gate material layers can be but be not limited to polysilicon.Form clearance wall insulating barrier 309A, 309A ' on the sidewall of first grid 330, form clearance wall insulating barrier 309B, 309B ' on the sidewall of second grid 331, material can be but be not limited to silica.Deposition and etching form gap parietal layer 308A, the 308A ' of PMOS device 303 and gap parietal layer 308B, the 308B ' of nmos device 304, and the material of gap parietal layer can be but be not limited to silicon nitride.Inject respectively p-type ion and N-shaped ion, form the source of PMOS device 303/drain electrode 307A, 307A's ' and nmos device 304 source/drain electrode 307B, 307B '.
Then, as shown in Fig. 3 B, form one deck the first oxide layer 310 with CVD method deposition above total, material can be but be not limited to silica, and thickness is approximately 125～145 dusts, is preferably 130 dusts, and the effect of this layer is as follow-up etching barrier layer.Then, form one deck high stress layer 311 in atmospheric pressure chemical vapour deposition (SACVD) mode above the first oxide layer 310, material can be but be not limited to silicon nitride, and thickness is approximately 450～550 dusts, is preferably 500 dusts.
Then, as shown in Figure 3 C, coating one deck photoresist layer 340 above nmos device 304 zones namely covers nmos device 304 zones, exposes PMOS device 303 zones.Take the first oxide layer 310 as etching barrier layer, first adopt the dry etching method to carry out the main etching step, then adopt wet etching method to carry out the over etching step, etching is removed the high stress layer 311 of PMOS device 303 tops, zone.After this etching process was completed, the first remaining part of oxide layer 310 was divided into the first oxide layer 310A in PMOS device 303 zones and the first oxide layer 310B in nmos device 304 zones.Then carry out annealing steps, stress is remembered in nmos device 304 zones.The annealing process temperature range is 1000～1100 degrees centigrade, and preferred temperature is approximately 1030～1040 degrees centigrade.
Then, as shown in Fig. 3 D, adopt the method for ashing to remove photoresist layer 340.Then, take the first oxide layer 310A and 310B as etching barrier layer, first adopt the dry etching method to carry out the main etching step, then adopt wet etching method to carry out the over etching step, remove remaining high stress layer 311 in order to etching.At this moment, the first about 15～25 dusts of oxide layer 310A residue, the second about 110～125 dusts of oxide layer 310B residue.
Then, as shown in Fig. 3 E, at PMOS device 303 zone coating one deck mask layers 341, material can be but be not limited to photoresist, the first oxide layer 310B to nmos device 304 zones eat-backs, and makes the consistency of thickness of the first oxide layer 310A in its thickness and PMOS device 303rd district.Etch back process can be selected the dry etching method, also can adopt wet etching method.
Next, as shown in Fig. 3 F, remove mask layer 341, and deposit in the SACVD mode above total and form the second oxide layer 312, material can be but be not limited to silica, and thickness is approximately 190～210 dusts.
Then, as shown in Fig. 3 G, deposition forms the figuratum photoresist layer (not shown) of tool above the second oxide layer 312, and carry out the techniques such as etching, remove first grid 330 and the second oxide layer 312 and the first oxide layer 310A and 310B above second grid 331, expose first grid 330 and second grid 331, to reserve the position that will form metal level in the future.Then the position of reserving on first grid 330 and second grid 331 forms metal level 313A and 313B, material can be chosen as tungsten, titanium or other suitable materials, and generation type is such as being chemical vapour deposition (CVD) (CVD), physical vapour deposition (PVD) (PVD) etc.Then remove the figuratum photoresist layer (not shown) of tool in the mode of ashing.
Then, as shown in Fig. 3 H, etching is removed remaining the second oxide layer 312 and remaining the first oxide layer 310A and 310B.Lithographic method can be selected the dry etching method, also can adopt wet etching method.
Will be according to the made cmos device of above-mentioned technique, owing to before deposition the second oxide layer 312, the first oxide layer 310B on nmos device 304 zones being eat-back, make the consistency of thickness of the first oxide layer 310A on itself and PMOS device 303 zones, the problem of deviation is appearred in the subregion that occurs with regard to the traditional fabrication cmos device can not occur the time like this by over etching so that device critical size, improve widely the overall performance of semiconductor device, improved the yields of device.
The flow chart of Fig. 4 A and 4B shows the technological process of making according to employing SMT and the SAB fabrication techniques cmos device of the embodiment of the present invention.In step 401, provide the PMOS device and and nmos device, the PMOS device has first grid, nmos device has second grid.In step 402, form one deck the first oxide layer at the PMOS device with above nmos device, form high stress layer above the first oxide layer.In step 403, take the first oxide layer as etching barrier layer, etching is removed the high stress layer of PMOS device area top.In step 404, carry out annealing process.In step 405, take the first oxide layer as etching barrier layer, etching is removed remaining high stress layer.In step 406, form one deck mask layer at the PMOS device area, the first oxide layer to the nmos device zone is eat-back, make the consistency of thickness of remaining the first oxide layer in its thickness and PMOS device region top, namely the top of remaining described the first oxide layer above the top of the first oxide layer of the first device top and the second device is concordant.In step 407, remove mask layer.In step 408, forming the second oxide layer above remaining the first oxide layer on nmos device zone and PMOS device area.In step 409, the second oxide layer on etching first grid and second grid and remain the first oxide layer is exposed first grid and second grid.In step 410, the position of reserving on first grid and second grid forms metal level.In step 411, remove remaining all the first oxide layer and the second oxide layers.
The elimination of making according to embodiment as above the semiconductor device of the leakage current drift phenomenon that produces due to the oxide stripping technology can be applicable in multiple integrated circuit (IC).For example memory circuitry according to IC of the present invention, as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM) or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (8)
1. a method of making the CMOS (Complementary Metal Oxide Semiconductor) device, comprise the following steps:
A: the first device and second device opposite with described the first type of device are provided, described the first device has first grid, described the second device has second grid, the top of described the first device and the second device is formed with the first oxide layer, and the top of described the first oxide layer is formed with high stress layer;
B: take described the first oxide layer as etching barrier layer and remove the described high stress layer of described the second device top;
C: carry out annealing process;
D: take described the first oxide layer as etching barrier layer and remove the described high stress layer of described the first device top;
E: form mask layer above described the second device;
F: the described oxide layer of etching described the first device top, make the top of remaining described the first oxide layer above top and described second device of described the first oxide layer of described the first device top concordant, then remove described mask layer.
2. the method for claim 1, also comprise the following steps:
G: deposition the second oxide layer above remaining described the first oxide layer;
H: the second oxide layer on the described first grid of etching and described second grid and described remaining described the first oxide layer, expose described first grid and described second grid;
I: form metal level on described first grid and described second grid;
J: remove remaining all described the first oxide layer and described the second oxide layers.
3. the method for claim 1, is characterized in that, the method for the described oxide layer above described etching the first device is etch back process.
4. the method for claim 1, is characterized in that, the thickness of described formation the first oxide layer is 125 ~ 145 dusts.
5. method as described in claim 1 or 4, is characterized in that, the thickness of described formation the first oxide layer is 130 dusts.
6. the method for claim 1, is characterized in that, the thickness of described formation high stress layer is 450 ~ 550 dusts.
7. method as described in claim 1 or 6, is characterized in that, the thickness of described formation high stress layer is 500 dusts.
8. the method for claim 1, is characterized in that, described the first device and described the second device are selected from nmos device or PMOS device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010124461 CN102194749B (en) | 2010-03-11 | 2010-03-11 | Method for making complementary type metal-oxide semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010124461 CN102194749B (en) | 2010-03-11 | 2010-03-11 | Method for making complementary type metal-oxide semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102194749A CN102194749A (en) | 2011-09-21 |
| CN102194749B true CN102194749B (en) | 2013-06-12 |
Family
ID=44602574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010124461 Active CN102194749B (en) | 2010-03-11 | 2010-03-11 | Method for making complementary type metal-oxide semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102194749B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10418356B2 (en) * | 2017-12-21 | 2019-09-17 | Nanya Technology Corporation | Diode structure and electrostatic discharge protection device including the same |
| CN110047862B (en) * | 2019-04-29 | 2021-04-30 | 上海华力微电子有限公司 | Method for forming CMOS image sensor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1971882A (en) * | 2005-11-10 | 2007-05-30 | 国际商业机器公司 | Method of providing a dual stress memory technique and related structure |
| CN101320713A (en) * | 2007-06-05 | 2008-12-10 | 国际商业机器公司 | Semi-conductor structure and its method |
-
2010
- 2010-03-11 CN CN 201010124461 patent/CN102194749B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1971882A (en) * | 2005-11-10 | 2007-05-30 | 国际商业机器公司 | Method of providing a dual stress memory technique and related structure |
| CN101320713A (en) * | 2007-06-05 | 2008-12-10 | 国际商业机器公司 | Semi-conductor structure and its method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102194749A (en) | 2011-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4937263B2 (en) | Technology for forming a distorted drain / source region recessed in NMOS and PMOS transistors | |
| US10170475B2 (en) | Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region | |
| CN101292334B (en) | Strained silicon mos device with box layer between the source and drain regions | |
| US10038075B2 (en) | Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region | |
| JP5544367B2 (en) | Recessed drain and source areas combined with advanced silicide formation in transistors | |
| US8357573B2 (en) | Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by creating a patterning non-uniformity at the bottom of the gate electrode | |
| JP2012504327A (en) | Transistor with buried Si / Ge material with reduced offset to channel region | |
| US8198152B2 (en) | Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials | |
| US7919379B2 (en) | Dielectric spacer removal | |
| JP2000196090A (en) | Double-gate soi device and manufacture thereof | |
| US10629734B2 (en) | Fabricating method of fin structure with tensile stress and complementary FinFET structure | |
| US7074657B2 (en) | Low-power multiple-channel fully depleted quantum well CMOSFETs | |
| US9214463B2 (en) | Methods of forming metal silicide regions on a semiconductor device | |
| CN102194749B (en) | Method for making complementary type metal-oxide semiconductor device | |
| TW201417190A (en) | Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface | |
| CN102024706B (en) | Method for manufacturing semiconductor device | |
| CN102376646B (en) | Method for improving surface morphology of dual-stress nitride | |
| CN102044492B (en) | Method for manufacturing semiconductor device | |
| CN102130054B (en) | Method for improving divergence of cut-off leakage current of semiconductor device | |
| CN102044437B (en) | Method for manufacturing semiconductor device | |
| KR100914973B1 (en) | Method for forming semiconductor device | |
| CN102024705B (en) | Semiconductor and method for producing same | |
| TWI353038B (en) | Method for fabricating strained-silicon cmos trans | |
| CN102456621A (en) | Semiconductor device structure and method for manufacturing same | |
| CN101071823A (en) | Semiconductor element and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20130106 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20130106 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |