JPH0897415A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent deterioration of gate breakdown strength due to cleaning before polysilicon deposition and to improve reliability by forming a buried contact hole after forming a first polysilicon film on a gate oxide film and by carrying out the precleaning thereafter. CONSTITUTION: A gate oxide film 22 is covered with a first polysilicon film 23 and it is precleaned in the state. Thereby, it is possible to prevent the gate oxide film 22 from being cut to deteriorate gate breakdown strength, unlike conventional methods, Furthermore, an inverted T-type MOS transistor can be formed readily by using a first polysilicon film and making it remain immediately below a spacer SiO2 film 33. Meanwhile, since a first polysilicon film piece 23A which is made electrically integral with a gate electrode exists on a low concentration source/drain layer in an inverted T-type gate MOS transistor, deterioration of conductance by hot carrier effect can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a MOS transistor and a buried contact.

[0002]

2. Description of the Related Art A buried contact directly connects polysilicon and a diffusion layer and is used to reduce a pattern area. FIG. 7 is a circuit diagram of a static RAM showing an example of using buried contacts, which is used for connecting the source of the transfer transistor Q1 and the gate polysilicon of the cell transistor Q2.

A conventional method of manufacturing a semiconductor device will be described below with reference to FIG.
It will be described with reference to FIGS. As shown in FIG. 8, a gate oxide film 2 of about 150Å is formed on a P-type Si substrate 1, and the gate oxide film 3 is wet-etched by using the resist film 3 having a predetermined opening as a mask to form a buried contact hole 4 And the Si substrate 1 is exposed.

Next, as shown in FIG. 9, after removing the resist film 3, the polysilicon film 5 is deposited by using a low pressure CVD apparatus, and phosphorus is doped at a high concentration. At this time, phosphorus in the polysilicon film diffuses into the Si substrate 1 through the buried contact hole 4 to form the n ⁺ diffusion layer 6. After that, S is formed on the polysilicon film 5.
The iO2 film 7 is deposited using a low pressure CVD apparatus.

Next, as shown in FIG. 10, the polysilicon film 5 and the SiO2 film 7 are patterned to form a polysilicon wiring 8 and a gate electrode 9. Then, as shown in FIG. 11, by implanting phosphorus ions,
Low concentration source / drain layer 10 of MOS transistor,
11 is formed. At this time, the low concentration source layer 10 and n +
The diffusion layer overlaps with each other and is electrically connected to each other. Then, as shown in FIG. 12, after forming a spacer SiO2 film 12 on the sidewalls of the polysilicon wiring 8 and the gate electrode 9, arsenic ions are ion-implanted to form high-concentration source / drain layers 13 and 14. .

Through the above manufacturing steps, the transfer transistor Q1 and the buried contact portion shown in FIG. 7 are formed. Although not shown, the polysilicon wiring 8 is extended to serve as the gate electrode of the cell transistor Q2.

[0007]

By the way, in the step of depositing the polysilicon film 5 (FIG. 9), the natural oxide film formed on the Si substrate 1 in the buried contact hole 4 portion is removed. , A step of cleaning the surface before deposition (hereinafter referred to as pre-cleaning) is performed.

However, since such pre-cleaning is performed using an HF aqueous solution, the surface of the gate oxide film 2 is also shaved at the same time, and there is a problem that the gate breakdown voltage of the MOS transistor deteriorates. This is presumably because the gate oxide film 2 is thinned by about 20Å and pinholes are generated in the oxide film by the pre-cleaning. The present invention
The present invention has been made in view of the above problems, and it is an object of the present invention to prevent deterioration of the gate breakdown voltage due to pre-deposition cleaning of polysilicon and to provide a highly reliable semiconductor device.

[0009]

According to a method of manufacturing a semiconductor device of the present invention, after forming a first polysilicon film 23 on a gate oxide film 22, a buried contact hole 24 is formed and then pre-cleaning is performed. I did it. Further, the first polysilicon film piece 23A is left directly under the spacer SiO2 film 33 and the gate electrode 29, and the polysilicon film piece 23A and the gate electrode 29 are integrated to form a so-called inverse T-type gate electrode. .

[0010]

According to the present invention, the first layer on the gate oxide film 22 is
Since it is covered with the polysilicon film 23, it is possible to prevent the gate oxide film 22 from being scraped and the gate breakdown voltage from being deteriorated. Furthermore, since the first polysilicon film 23 is used and left under the spacer SiO2 film 33, there is an advantage that an inverse T-type MOS transistor can be easily formed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS. First,
As shown in FIG. 1, a gate oxide film 22 of about 150Å is formed on a P-type Si substrate 21, and a first polysilicon film 23 of about 500Å is formed on the entire surface of the gate oxide film 22 by using a low pressure CVD apparatus. It is formed and heavily doped with phosphorus by the thermal diffusion method. Next, as shown in FIG. 2, the first polysilicon film 23 and the gate oxide film 22 are selectively etched to form a buried contact hole 24.

Next, as shown in FIG. 3, pre-cleaning is performed using an HF aqueous solution to clean the surface of the Si substrate 21 exposed at the buried contact 24 with the HF aqueous solution, and then the low pressure CVD apparatus is used to form the Si substrate. A second polysilicon film 25 of about 1000 Å is deposited on the entire surface of 21. Then, the second polysilicon film 25 is heavily doped with phosphorus by a thermal diffusion method. At this time, phosphorus in the second polysilicon film 25 is buried in the contact hole 2
4 and diffuses into the Si substrate 21 to form the n + diffusion layer 26. Then, using a low pressure CVD apparatus, about 1000 Å of the first SiO 2 is deposited on the second polysilicon film 25.
The film 27 is formed. As described above, according to this embodiment, since the pre-cleaning is performed in the state where the gate oxide film 22 is covered with the first polysilicon film 23, the gate oxide film 22 is scraped and the gate breakdown voltage is increased as in the conventional case. It is possible to prevent deterioration.

Next, as shown in FIG. 4, the second polysilicon film 25 and the SiO2 film 27 are selectively etched to form a polysilicon wiring 28 and a gate electrode 29. For the etching, for example, a microwave dry etching device is used, and CHF3 + is used as an etching gas.
By introducing O2 gas, first etching the first SiO2 film 27, and then using the remaining first SiO2 film 27 as a mask, introducing SF6 + C2Cl3F3 gas and etching the second polysilicon film 25. Done.

After that, phosphorus ions are accelerating voltage 100 Ke.
Ion implantation is performed under the conditions of V and an implantation amount of 2E13 / cm @ 2 to form the low-concentration source / drain layers 30 and 31 on both sides of the gate electrode 29 in a self-aligned manner. At this time, the low-concentration source layer 30 and the n ⁺ diffusion layer 26 overlap each other and are electrically connected to each other. Next, as shown in FIG. 5, a low pressure CVD apparatus was used to cover the entire surface of the second
The SiO2 film 32 is deposited. Then, as shown in FIG. 6, the entire surface of the second SiO 2 film 32 is etched to remove the polysilicon wiring 28 and the gate electrode 29.
A spacer SiO2 film 33 is formed on the side wall of the. And
The spacer SiO2 film 33 and the second SiO2 film 32
Using the as a mask, the first polysilicon film 23 is removed by etching. As a result, unnecessary portions of the first polysilicon film 23 are removed and the spacer SiO2 film 33 is removed.
The first polysilicon film piece 23A is left immediately below the gate electrode 29, and as a result, the polysilicon film piece 23A and the gate electrode 29 are integrated to form a so-called inverse T-type gate electrode. . After that, arsenic ions are accelerated at an acceleration voltage of 70 KeV and an implantation amount of 5E15 / cm.
Ion implantation is performed under the condition 2 to form the high concentration source / drain layers 34 and 35 in a self-aligned manner. As a result, the LDD structure MO having the inverse T-shaped gate is formed.
A semiconductor device is formed in which the S transistor and its source are connected to the polysilicon wiring 28 by the buried contact.

According to the above manufacturing method, the gate oxide film 2
Since the pre-cleaning is performed in the state where 2 is covered with the first polysilicon film 23, it is possible to prevent the gate breakdown voltage from being deteriorated and the gate breakdown voltage being deteriorated as in the conventional case. Furthermore, there is an advantage that the inverse T-type MOS transistor can be easily formed by using the first polysilicon film and leaving it just under the spacer SiO2 film 33. In the inverse T-type MOS transistor, the low concentration source / drain layer 3
Since the first polysilicon film pieces 23A electrically integrated with the gate electrodes are present on 0 and 31, the deterioration of the conductance due to the hot carrier effect can be prevented.

Through the above manufacturing steps, the portion of the transfer transistor Q1 and the buried contact shown in FIG. 7 is formed as in the conventional example. Although not shown, the polysilicon wiring 28 is also extended to serve as the gate electrode of the cell transistor Q2, which is similar to the conventional example.

[0017]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the pre-cleaning is performed with the gate oxide film 22 covered with the first polysilicon film 23. It is possible to prevent the gate oxide film 22 from being scraped and the gate breakdown voltage from deteriorating, and it is possible to manufacture a highly reliable semiconductor device.

Furthermore, the first polysilicon film 2 is also provided.
3 is used and left under the spacer SiO2 film 33 and the gate electrode 29, there is an advantage that an inverse T-type MOS transistor can be easily formed. As a result, the low concentration source / drain layer 3
Since the first polysilicon film piece 23A electrically integrated with the gate electrode 29 is present on 0 and 31, it is possible to prevent the conductance from being deteriorated due to the hot carrier effect.

[Brief description of drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a sixth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 7 is a circuit diagram of a static RAM showing an example of use of buried contacts.

FIG. 8 is a first cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 9 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 10 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 11 is a fourth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 12 is a fifth cross-sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/11 H01L 27/10 381

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device having a MOS transistor and a buried contact for connecting a source of the MOS transistor and a polysilicon wiring, wherein a buried contact hole is formed after a gate oxide film is covered with a polysilicon film. By forming it, the gate oxide film is prevented from being scraped by cleaning, and a part of the polysilicon film is left directly under the gate electrode of the MOS transistor and the spacer SiO2 film, thereby forming an inverse T-type MOS transistor. A method of manufacturing a semiconductor device, comprising: 2. A step of forming a gate oxide film 22 on a semiconductor substrate 21 of one conductivity type, a step of forming a first polysilicon film 23 on the gate oxide film 22, and a first polysilicon film 23. And a step of selectively etching the gate oxide film 22 to form a buried contact hole 24, a step of cleaning the surface of the substrate 21 exposed in the buried contact hole 24, and a second polysilicon layer on the entire surface of the substrate 21. A step of forming the film 25, and a step of doping the second polysilicon film 25 with an impurity of opposite conductivity type and diffusing the impurity into the substrate 21 from the buried contact hole 24 to form a diffusion layer 26 of opposite conductivity type. , A step of forming the first SiO 2 film 27 on the second polysilicon film 25, and the step of forming the second polysilicon film 25 and the first SiO 2 film 27.
A step of selectively etching the polysilicon to form a polysilicon wiring 28 and a gate electrode 29; a step of forming low concentration source / drain layers 30 and 31 of opposite conductivity type by ion implantation on both sides of the gate electrode 29; A step of forming a spacer SiO2 film 33 on the sidewalls of the silicon wiring 28 and the gate electrode 29; etching the first polysilicon film 23 using the spacer SiO2 film 33 as a mask;
2 A step of leaving the first polysilicon film piece 23A immediately below the film 33, and a step of forming high-concentration source / drain layers 34 and 35 of opposite conductivity type by ion implantation are provided. Production method.