JPH06181318A - Semiconductor non-volatile memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress a drain leak current by a method wherein the thickness of the memory insulating film, which comes in contact with the source and drain of the second conductivity type high density impurity layer provided on the semiconductor substrate of the region where a memory gate electrode is aligned, is formed thicker than the part inside a channel which does not come in contact with the source and drain of the high density impurity layer. CONSTITUTION:A MOS gate electrode 1 is provided on a MOS insulating film 24, and a memory insulating film 23, consisting of a memory oxide film 4, a nitride film 5 and a top oxide film 6, is formed. A memory gate 2 is formed on the region of the memory insulating film 23 and a sacrificial oxide film 41. A high density inpurity layer 9 is formed, as a second conductivity type source region and a drain region, on a substrate 8 of the region located between the MOS gate electrode 1 and the memory gate electrode 2 and also between the MOS gate electrode 1 and a field oxide film 7. AS a result, the electric field between the memory gate electrode 2 and a drain can be alleviated, and the drain withstand voltage of the memory transistor can also be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory element and a method for manufacturing the same, and more particularly to improvement of drain withstand voltage of the semiconductor nonvolatile memory element, stabilization of memory characteristics, and high reliability.

[0002]

2. Description of the Related Art Generally, since a MOS transistor is required for rewriting and reading information in a nonvolatile memory element, a MOS transistor and a memory transistor are formed in the same element region.

In the manufacturing process of this non-volatile memory element, the method of forming the MOS gate electrode of the MOS transistor and the memory gate electrode of the memory transistor includes the following gate electrode forming step.

The manufacturing process of the nonvolatile memory element in the conventional example will be described with reference to the sectional views of FIGS.

First, as shown in FIG. 7, a field oxide film 7 is formed in a field region 11 around a device region 10 of a semiconductor substrate 8 of the first conductivity type by using a selective oxidation method. Next, a memory oxide film 4, a nitride film 5 and a top oxide film 6 are sequentially formed on the entire surface. Then, the memory device area 1
A resist 13 which is a photosensitive material is formed on 2.

Next, as shown in FIG. 8, the memory oxide film 4 and the nitride film are formed by a so-called photo-etching technique in which the top oxide film 6, the nitride film 5 and the memory oxide film 4 are etched using the resist 13 as a mask. 5 and the top oxide film 6 are formed as the memory insulating film 23.

After that, a gate oxide film 3 is formed on the entire surface,
A polycrystalline silicon film is formed as the gate electrode material 14 on the entire surface by the chemical vapor deposition method. Further, a resist 13 is formed on the memory element region 12 and the MOS element region 15.

Thereafter, as shown in FIG. 9, the gate electrode material 14 made of a polycrystalline silicon film is etched using the resist 13 as an etching mask to form the MOS gate electrode 1 and the memory gate electrode 2 of the MOS transistor.

Next, as shown in FIG. 10, a second conductivity type high-concentration impurity layer 9 serving as a source and a drain is formed using the MOS gate electrode 1 and the memory gate electrode 2 as a mask to form a nonvolatile memory element. To form.

[0010]

The memory insulating film 23 of the semiconductor nonvolatile memory element formed by the conventional manufacturing method described with reference to FIGS. 7 to 10 is the memory oxide film 4, the nitride film 5 and the top. The oxide film 6 is formed. Therefore, when the MOS transistor is turned on during data reading, the read voltage is applied to the drain of the memory transistor.

In this case, in the written state of the memory transistor, that is, in the state where electrons are injected into the memory insulating film 23, the band of the drain is bent by the high vertical electric field from the memory gate electrode 2.

As a result, a leak current in the "off" state of the memory transistor occurs due to the band-to-band tunneling of electrons in the valence band to the conduction band.

Further, there is a problem that the drain breakdown voltage of the memory transistor is lowered due to the generation of leak current due to the high voltage between the memory gate electrode 2 and the drain.

Further, the insulating film between the memory gate electrode 2 and the drain is composed of a thin memory insulating film 23. Therefore, as the number of times of reading increases, electrons accelerated by the electric field at the time of reading are injected into the memory insulating film 23, which deteriorates the memory insulating film 23 and deteriorates memory transistor characteristics.

An object of the present invention is to solve the above problems and provide a structure of a semiconductor nonvolatile memory element in which a drain leak current is suppressed and a manufacturing method thereof.

[0016]

In order to achieve the above object, the present invention employs a semiconductor nonvolatile memory element and a manufacturing method thereof described below.

According to the structure of the semiconductor nonvolatile memory element of the present invention, in the semiconductor nonvolatile memory element having the memory gate electrode provided on the first conductivity type semiconductor substrate via the memory insulating film, the memory gate electrodes are aligned. The film thickness of the memory insulating film in contact with the source and drain of the second-conductivity-type high-concentration impurity layer provided in the region of the semiconductor substrate is thicker than the inside of the channel not in contact with the source and drain of the high-concentration impurity layer. .

According to the method of manufacturing a semiconductor nonvolatile memory element of the present invention, a field oxide film is formed in a field region around an element region of a semiconductor substrate of the first conductivity type, a sacrificial oxide film is formed in the element region, and a photo oxide film is formed. By the etching technique, the step of removing the sacrificial oxide film in the memory element region, the step of sequentially forming the memory oxide film, the nitride film, and the top oxide film, and by the photoetching technique, both sides of the memory element region in the channel direction are removed. , Composed of a sacrificial oxide film, a memory oxide film, a nitride film and a top oxide film,
A step of removing a top oxide film, a nitride film, a memory oxide film and an oxide film in a region wider than the memory element region, a step of forming a gate oxide film in the element region and forming a gate electrode material, and a photoetching process. A step of simultaneously forming a MOS gate electrode and a memory gate electrode by a technique, a step of forming a second-conductivity-type high-concentration impurity layer in an element region in a region aligned with the gate electrode, and a multilayer mainly composed of silicon dioxide. The method is characterized by including a step of forming a wiring insulating film, a step of forming a multilayer wiring insulating film by a photoetching technique, and a step of forming a wiring metal.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. First, the structure of the semiconductor nonvolatile memory element according to the present invention will be described with reference to the sectional view of FIG.

The semiconductor nonvolatile memory element of the present invention is an MO
A MOS gate electrode 1 formed on the S insulating film 24,
Further, a region formed by the memory insulating film 23 including the memory oxide film 4, the nitride film 5, and the top oxide film 6,
The memory gate electrode 2 is formed on the region formed by the memory insulating film 23 including the sacrificial oxide film 41, the memory oxide film 4, the nitride film 5, and the top oxide film 6.

Next, a manufacturing method for forming the structure of the semiconductor nonvolatile memory element of the present invention described with reference to FIG. 1 will be described. 2 to 6 are sectional views showing a manufacturing method for manufacturing the structure of the nonvolatile memory element of the present invention in the order of steps.

First, as shown in FIG. 2, the field region 1 around the element region 10 of the semiconductor substrate 8 of the P type conductivity type.
1, a field oxide film 7 having a thickness of 700 nm is formed by a so-called selective oxidation process in which an oxidation resistant film such as a silicon nitride film is used as a mask for oxidation.

Next, oxidation treatment is performed in a mixed gas of oxygen and nitrogen to form a sacrificial oxide film 41 of a silicon dioxide film having a thickness of about 20 nm on the entire surface of the element region 10.

Next, a resist 13 which is a photosensitive material is formed on the entire surface, exposed and developed using a predetermined photomask, and the resist 13 on the memory element area 12 which is an area for forming a memory element. To form an opening.

Then, the sacrificial oxide film 41 is removed by etching with a hydrofluoric acid buffer solution using the resist 13 as a mask. Then, the resist 13 used as the etching mask is removed.

Next, as shown in FIG. 3, an oxidation treatment is performed in a mixed gas of oxygen and nitrogen, and the memory oxide film 4 made of a silicon dioxide film having a thickness of about 2 nm is formed on the sacrificial oxide film 41. It is formed in the memory element region 12 in the opening.

Next, a nitride film 5 made of a silicon nitride film is formed to a thickness of about 9 nm on the entire surface including the memory oxide film 4 by chemical vapor deposition.

Further, an oxidization process is performed in an oxidizing atmosphere to oxidize the nitride film 5, and a top oxide film 6 made of a silicon dioxide film is formed on the nitride film 5.

Next, a resist 13 is formed on the entire surface, exposed and developed using a predetermined photomask to form a memory gate electrode having a width of about 0.3 μm wide from both ends of the memory element region 12. A resist 13 is formed on the memory element region 12.

After that, the top oxide film 6 is etched with a hydrofluoric acid buffer solution using the resist 13 as an etching mask. Further, the nitride film 5, the memory oxide film 4, and the sacrificial oxide film 41 are etched by a dry etching method using a mixed gas of SF ₆ + CHF ₃ + He.

As a result, a region composed of the memory oxide film 4, the nitride film 5 and the top oxide film 6 and a region composed of the sacrificial oxide film 41, the memory oxide film 4, the nitride film 5 and the top oxide film 6 are formed. The memory insulating film 23 configured by is formed.

Next, as shown in FIG. 4, a gate oxide film 3 made of a silicon dioxide film having a thickness of about 30 nm is formed on the entire surface. Further, as the gate electrode material 14, a polycrystalline silicon film having a thickness of about 400 nm is formed on the entire surface by a chemical vapor deposition method using monosilane as a reaction gas.

After that, a resist 13 is formed on the entire surface,
Exposure and development processing is performed using a predetermined photomask to form a resist 13 on the memory element region 12 which is a region for forming the memory gate electrode 2 and the MOS element region 15 which is a region for forming the MOS gate electrode 1. Form.

Thereafter, as shown in FIG. 5, the gate electrode material 14 is formed by using the resist 13 as an etching mask.
The polycrystalline silicon film is etched by a dry etching method using a mixed gas of SF ₆ + O ₂ as an etching gas.

As a result, the MOS composed of the gate oxide film 3 is formed.
On the insulating film 24, the MOS gate electrode 1 of the MOS transistor, the region including the memory oxide film 4, the nitride film 5, and the top oxide film 6, the sacrificial oxide film 41, the memory oxide film 4, and the nitride film 5. The memory gate electrode 2 of the memory transistor is simultaneously formed on the memory insulating film 23 including the region including the top oxide film 6.

Next, using the MOS gate electrode 1 and the memory gate electrode 2 as a mask for ion implantation, phosphorus, which is an N-type impurity having a conductivity type opposite to that of the semiconductor substrate 8, has an acceleration energy of 50 keV and an ion implantation amount of 3. 5 × 10 ¹⁵ ato
Ion implantation is performed at about ms / cm ² .

As a result, as the source and drain regions of the second conductivity type, between the MOS gate electrode 1 and the memory gate electrode 2, between the memory gate electrode 2 and the field oxide film 7, and the MOS gate electrode 1 is formed. And the field oxide film 7 in the region between the semiconductor substrate 8 and the high concentration impurity layer 9
To form.

Next, as shown in FIG. 6, a multi-layered wiring insulating film 16 mainly composed of silicon dioxide is formed. After that, a contact window 17 is formed in the insulating film 16 for multilayer wiring by using a photoetching technique, and further, the wiring metal 1
A nonvolatile memory element is obtained by forming aluminum as 8.

In the above description, the memory insulating film 23 is used.
As an example of using the multilayer film including the sacrificial oxide film 41, the memory oxide film 4, the nitride film 5, and the top oxide film 6 as the multilayer film constituting the above, the sacrificial oxide film 41 is
Not only a normal sacrificial oxide film formed after the selective oxidation treatment but also an insulating oxide film, a nitride film or the like can be used.

[0040]

As is apparent from the above description, in the semiconductor non-volatile memory element structure of the present invention and the manufacturing method thereof, the memory transistor, which has been a problem in the conventional structure, has a band at the time of reading data in the written state. In this structure, the leakage current in the “off” state of the memory transistor due to the inter-tunneling is that the memory insulating film below the memory gate electrode in contact with the drain is composed of the sacrificial oxide film, the memory oxide film, the nitride film, and the top oxide film. Therefore, the high vertical electric field from the memory gate electrode is relaxed and reduced.

The effect of the present invention will be described with reference to the graph of FIG. FIG. 11 shows the gate voltage (Vg) and the drain current (Id) in the data write state of the semiconductor nonvolatile memory element manufactured by the manufacturing method of the present invention and the semiconductor nonvolatile memory element manufactured by the manufacturing method shown in the conventional example. This is a comparison of characteristics. In the graph of FIG. 11, the broken line represents the characteristic in the conventional example, and a leak current due to band-to-band tunneling flows even when the gate voltage is 0V. On the other hand, in the characteristics of the semiconductor nonvolatile memory element according to the present invention, the leak current is reduced as shown by the solid line. Therefore, the electric field between the memory gate electrode and the drain is relaxed, and the drain breakdown voltage of the memory transistor is improved.

Further, even when the characteristics of the memory transistor are deteriorated by the charge injection into the memory insulating film due to the increase in the number of readings, the electric field between the memory gate electrode and the drain is relaxed, and the charge into the memory insulating film is reduced. It becomes possible to prevent the injection, and it is possible to prevent the deterioration of the memory transistor characteristics due to the deterioration of the memory insulating film.

As a result of the above, according to the present invention, it is possible to improve the drain breakdown voltage, realize the stabilization of the memory characteristics, and obtain a highly reliable semiconductor nonvolatile memory element.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure of a semiconductor nonvolatile memory element according to an example of the present invention.

FIG. 2 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory element in the example of the present invention.

FIG. 3 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory element according to the example of the present invention.

FIG. 4 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory element in the example of the present invention.

FIG. 5 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory element in the example of the present invention.

FIG. 6 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory element in the example of the present invention.

FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor nonvolatile memory element in a conventional example.

FIG. 8 is a cross-sectional view showing a method for manufacturing a semiconductor nonvolatile memory element in a conventional example.

FIG. 9 is a cross-sectional view showing a method for manufacturing a semiconductor nonvolatile memory element in a conventional example.

FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor nonvolatile memory element in the conventional example.

FIG. 11 is a graph showing characteristics of a gate voltage and a drain current during data writing in the semiconductor nonvolatile memory element of the present invention and the semiconductor nonvolatile memory element of the conventional example.

[Explanation of symbols]

 1 MOS gate electrode 2 memory gate electrode 7 field oxide film 8 semiconductor substrate 9 high-concentration impurity layer 12 memory element region 15 MOS element region 41 sacrificial oxide film

Claims (2)

[Claims] 1. A semiconductor non-volatile memory element comprising a memory gate electrode provided on a first conductivity type semiconductor substrate via a memory insulating film, wherein the second conductivity type is provided on the semiconductor substrate in a region where the memory gate electrode is aligned. The region in contact with the high concentration impurity layer of is composed of a memory insulating film and a sacrificial oxide film,
A semiconductor nonvolatile memory element, wherein a region separated from the high-concentration impurity layer is made of a memory insulating film. 2. A sacrificial oxide film in a memory device region is formed by forming a field oxide film in a field region around a device region of a first conductivity type semiconductor substrate, forming a sacrificial oxide film in the device region, and using a photoetching technique. Of the sacrificial oxide film, the memory oxide film and the nitride film on both sides in the channel direction of the memory element region by the photoetching technique and the step of sequentially forming the memory oxide film, the nitride film and the top oxide film. A step of removing the top oxide film, the nitride film, the memory oxide film, and the sacrificial oxide film in a region wider than the memory element region so that the gate oxide film is formed in the element region. Forming a gate electrode material and forming a MOS gate electrode and a memory gate electrode at the same time by a photo-etching technique; By a step of forming a second-conductivity-type high-concentration impurity layer in the element region in a region where the gate electrode and the memory gate electrode are aligned with each other, a step of forming an insulating film for a multi-layer wiring mainly composed of silicon dioxide, and a photoetching technique A step of forming a contact window in the insulating film for multilayer wiring,
A method of manufacturing a semiconductor nonvolatile memory element, comprising the step of forming a wiring metal.